CN102122613A - Method for forming self-aligning metal silicide - Google Patents
Method for forming self-aligning metal silicide Download PDFInfo
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- CN102122613A CN102122613A CN2010100225670A CN201010022567A CN102122613A CN 102122613 A CN102122613 A CN 102122613A CN 2010100225670 A CN2010100225670 A CN 2010100225670A CN 201010022567 A CN201010022567 A CN 201010022567A CN 102122613 A CN102122613 A CN 102122613A
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Abstract
The invention relates to a method for forming self-aligning metal silicide, which comprises the following steps of: providing a semiconductor substrate, wherein at least one silicon region is arranged on the surface of the semiconductor substrate; processing the edge region of the semiconductor substrate by utilizing a plasma; removing a natural oxide layer of the silicon region; forming a metal layer in the silicon region; forming a protective layer on the metal layer surface; and annealing the semiconductor substrate provided with the metal layer to form a metal silicide layer. The method for forming the self-aligning metal silicide can reduce particle pollution and improve the forming quality and yield of the self-aligning metal silicide.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly the formation method of self-aligned metal silicate.
Background technology
In semiconductor fabrication, metal silicide is widely used in source/drain contact and contacts with grid and reduce contact resistance owing to having lower resistivity and having good adhesiveness with other materials.High-melting point metal and silicon react and fuse the formation metal silicide, can form the metal silicide of low-resistivity by a step or multistep annealing process.Along with the raising of semiconductor process technology, particularly at 90nm and following technology node thereof, in order to obtain lower contact resistance, the alloy of nickel and nickel becomes the main material that forms metal silicide.
At disclosed application number is the formation method that discloses a kind of self-aligned metal silicate in 200780015617.9 the Chinese patent application, and this method selects nickel alloy as the material that forms metal silicide.Fig. 1 to Fig. 3 has provided the cross-sectional view in this method formation each stage of self-aligned silicide.
As shown in Figure 1, the semiconductor-based end 100, at first be provided, be formed with a plurality of MOS transistor (being example only among Fig. 1) at described the semiconductor-based end 100, be formed with isolated area 110 between the adjacent MOS transistor, be filled with insulating material in the described isolated area 110 with a MOS transistor; Described MOS transistor comprises: be formed on the gate dielectric layer 104 at the semiconductor-based end 100, the gate electrode 103 that on described gate dielectric layer 104, forms, the side wall 105 that forms in the both sides of described gate electrode 103 and gate dielectric layer 104, source electrode 101 that described gate electrode 103 both sides form at semiconductor-based the end 100 and drain electrode 102.
As shown in Figure 2, form metal level 106 on the surface at the described semiconductor-based end 100, described metal level 106 covers described source electrode 101, drain electrode 102, grid 103 and side wall 105, and the material of described metal level 106 is the nickel platinum alloy.Further, can form protective layer 107 on metal level 106, the material of described protective layer 107 is titanium nitride (TiN), is used for preventing that metal level 106 is oxidized, and the formation of protective layer 107 is optionally, can be left in the basket.
As shown in Figure 3, to carrying out annealing process in the described semiconductor-based end 100, by annealing, described source electrode 101, drain electrode 102, grid 103 lip-deep metal level 106 materials and described source electrode 101, drain 102 and grid 103 in the silicon materials generation metal silicide layer that reacts, be respectively 101a, 102a, 103a.The metal level 106 that will not react by selective etch is removed afterwards, makes metal silicide layer 101a, the 102a, the 103a that form be exposed to the surface at the described semiconductor-based end 100.
The common surface of metal silicide that existing technology forms has particle contamination, causes yield of devices to reduce.
Summary of the invention
The problem that the present invention solves is to lower the metal silicide particle contamination.
For addressing the above problem, the invention provides a kind of formation method of self-aligned metal silicate, comprising: the semiconductor-based end is provided, and described semiconductor-based basal surface has a silicon area at least; Using plasma is handled described semiconductor-based feather edge zone; Remove the natural oxidizing layer of described silicon area; Form metal level at described silicon area; Form protective layer at described layer on surface of metal; To annealing at the described semiconductor-based end that is formed with metal level, form metal silicide layer.
Optionally, described fringe region is greater than 0 millimeter and smaller or equal to 2 millimeters zone along the semiconductor-based feather edge of radial direction of described semiconductor-based end distance.
Optionally, using plasma is handled described semiconductor-based feather edge zone and is specifically comprised: select plasma etching equipment for use, adopt CF
4, SF
6Or CF
4With SF
6Mist was handled fringe region of the described semiconductor-based ends 200 3 seconds to 5 minutes.
Optionally, select plasma etching equipment for use, CF
4Flow is 10SCCM to 200SCCM, handles fringe region of the described semiconductor-based ends 200 3 seconds to 5 minutes.
Optionally, select plasma etching equipment for use, SF
6Flow is 10SCCM to 200SCCM, handles fringe region of the described semiconductor-based ends 200 3 seconds to 5 minutes.
Optionally, select plasma etching equipment for use, CF
4Flow is 10SCCM to 200SCCM, SF
6Flow is 10SCCM to 200SCCM, handles fringe region of the described semiconductor-based ends 200 3 seconds to 5 minutes.
Optionally, the formation technology of described metal level is physical gas-phase deposition.
Optionally, the material of described metal level is Ti, Co or Ni.
Optionally, the material of described protective layer is TiN.
Optionally, the formation technology of described protective layer is physical gas-phase deposition.
Optionally, also comprise step: remove protective layer and unreacted metal layer thereof.
Compared with prior art, the present invention has the following advantages: the present invention is by carrying out plasma treatment to semiconductor substrate 200 edges, reduce in the follow-up self-aligned metal silicate technology in other zones at the semiconductor-based end 200 and form particle contaminations, improved the yield of self-aligned metal silicate technology, and adopt plasma treatment fringe region of the described semiconductor-based ends 200, described fringe region takes into full account the yield of production practicality and product greater than 0 millimeter and smaller or equal to 2 millimeters.
Description of drawings
By the more specifically explanation of the preferred embodiments of the present invention shown in the accompanying drawing, above-mentioned and other purpose, feature and advantage of the present invention will be more clear.Reference numeral identical in whole accompanying drawings is indicated identical part.Painstakingly do not draw accompanying drawing, focus on illustrating purport of the present invention by actual size equal proportion convergent-divergent.
Fig. 1 to Fig. 3 is the process schematic diagram that prior art forms self-aligned silicide;
Fig. 4 is the schematic flow sheet of formation method of the self-aligned metal silicate of one embodiment of the present of invention;
Fig. 5 to Figure 11 is the process schematic diagram of formation method of the self-aligned metal silicate of one embodiment of the present of invention.
Embodiment
By background technology as can be known, the common surface of metal silicide that existing technology forms has particle contamination, cause yield of devices to reduce, for this reason, the present inventor is through a large amount of experiments, find that above-mentioned particle contamination mainly is in the layer metal deposition process, the semiconductor-based feather edge zone of depositing metal layers is crude, has than multi-fault and burr, in the depositing metal layers process, described metal ion is deposited on semiconductor-based feather edge and is easy to drop, and forms particle contamination.
For this reason, the present inventor proposes a kind of formation method of self-aligned metal silicate of optimization, comprising:
The semiconductor-based end is provided, and described semiconductor-based basal surface has a silicon area at least;
Using plasma is handled described semiconductor-based feather edge zone;
Remove the natural oxidizing layer of described silicon area;
Form metal level at described silicon area;
Form protective layer at described layer on surface of metal;
To annealing at the described semiconductor-based end that is formed with metal level, form metal silicide layer.
A lot of details have been set forth in the following description so that fully understand the present invention.But the present invention can implement much to be different from alternate manner described here, and those skilled in the art can do similar popularization under the situation of intension of the present invention, so the present invention is not subjected to the restriction of following public concrete enforcement.
Secondly, the present invention utilizes schematic diagram to be described in detail, when the embodiment of the invention is described in detail in detail; for ease of explanation; the profile of expression device architecture can be disobeyed general ratio and be done local the amplification, and described schematic diagram is example, and it should not limit the scope of protection of the invention at this.The three dimensions size that in actual fabrication, should comprise in addition, length, width and the degree of depth.
Fig. 4 is the schematic flow sheet of formation method of the self-aligned metal silicate of one embodiment of the present of invention, and Fig. 5 to Figure 10 is the process schematic diagram of formation method of the self-aligned metal silicate of one embodiment of the present of invention.Below in conjunction with Fig. 4 to Figure 10 the formation method of self-aligned metal silicate of the present invention is described.
Step S101 provides the semiconductor-based end, and described semiconductor-based basal surface has a silicon area at least.
With reference to figure 5, the semiconductor-based end 200, be provided, have a silicon area at least on surface, the described semiconductor-based ends 200.The material at the described semiconductor-based end 200 can be a kind of in monocrystalline silicon, the amorphous silicon, the material at the described semiconductor-based end 200 also can be a silicon Germanium compound, the described semiconductor-based end 200 can also be an epitaxial layer structure on silicon-on-insulator (SOI, Silicon On Insulator) structure or the silicon.
Surface, the described semiconductor-based ends 200 is formed with gate regions 210, and described gate regions 210 comprises gate dielectric layer 211, be formed on the gate polysilicon layer 212 on gate medium surface, be formed on the side wall 213 of described gate dielectric layer 211 and gate polysilicon layer 212 sidewall; Be formed with source area 220 and drain region 230 at described the semiconductor-based end 200.
Described silicon area can be that source area 220 at the described semiconductor-based end 200 is or/and drain region 230; Described silicon area also can be the gate polysilicon layer 212 on surface, the described semiconductor-based ends 200.
In the present embodiment, be that source area 220, drain region 230 and gate polysilicon layer 212 are that example is done exemplary illustrated with described silicon area.
Described silicon area has one deck natural oxidizing layer (not shown) owing to be exposed to extraneous surface.
It needs to be noted, in Fig. 5, just provided the generalized section at the semiconductor-based end 200, in the semiconductor production of reality, the described semiconductor-based end 200, be generally certain specification, for example can be the 150mm specification, the 200mm specification, the semiconductor-based end 200 of 300mm specification or 450mm specification, and the described semiconductor-based end 200, be generally circular, for ease of understanding the present invention, the spy provides the schematic top plan view at the semiconductor-based end 200, please refer to Fig. 6, omitted among Fig. 6 and be formed on the interior or surperficial source area 220 in the semiconductor-based ends 200, drain region 230 and gate polysilicon layer 212.
The present inventor also finds through a large amount of experiments; the fringe region at the described semiconductor-based end 200 has than multi-fault and burr; this is owing to form device on the semiconductor-based end 200; for example in the technology of source area 220, drain region 230 and gate polysilicon layer 212; have technologies such as photoetching, ion injection, deposition; above-mentioned technology usually can have certain residual or there is certain damage at semiconductor substrate 200 edges at fringe region of the semiconductor-based ends 200, thereby forms than multi-fault and burr at edge, the semiconductor-based ends 200.
The metal ion that above-mentioned tomography that is formed on edge, the semiconductor-based ends 200 and burr can adsorb in subsequent technique in the depositing operation forms particle, and the described particle for example silicon area that can drop in other zones at the semiconductor-based end 200 forms particle contamination.
For this reason, the present inventor proposes a kind of processing step of optimization, and as described in step S102, using plasma is handled described semiconductor-based feather edge zone.
The present inventor finds that after further research described tomography and burr are positioned at along radial direction of the described semiconductor-based end, and the semiconductor-based feather edge of distance is greater than 0 millimeter and smaller or equal to 2 millimeters fringe region of the semiconductor-based ends 200.
With reference to figure 7, using plasma is handled 202 fringe regions of the described semiconductor-based ends 200 and is used to remove tomography and the burr that is formed on edge, the semiconductor-based ends 200.
Described fringe region is greater than 0 millimeter and smaller or equal to 2 millimeters zone along radial direction of the described semiconductor-based ends 200 distance edge, the semiconductor-based ends 200.
It needs to be noted, be formed on the device of other positions, the semiconductor-based ends 200, in the using plasma processing procedure, can adopt the baffle plate 201 shield portions plasmas corresponding with the described semiconductor-based end 200 for fear of plasma damage.Described baffle plate 201 shapes are consistent with the semiconductor-based end 200, are circle.The difference of the radius of described baffle plate 201 and radius of the semiconductor-based ends 200 is greater than 0 millimeter and smaller or equal to 2 millimeters, described baffle plate 201 is arranged in plasma treatment procedure at semiconductor-based the end 200, and the center line of baffle plate 201 and the center line at the semiconductor-based end 200 are overlapping.
The employing plasma treatment of the present invention 202 described semiconductor-based ends 200 fringe region, described fringe region is greater than 0 millimeter and smaller or equal to 2 millimeters, taken into full account the yield of production practicality and product, concrete, if the edge is greater than 2 millimeters at the plasma treatment described semiconductor-based ends 200, described plasma will damage other devices at the semiconductor-based end 200, makes the utilance at the semiconductor-based end 200 descend.In other semiconductor product, if the device at the semiconductor-based end 200 and the edge at the semiconductor-based end 200 be greater than 2 millimeters, the edge can be greater than 2 millimeters at the plasma treatment described semiconductor-based ends 200 so.
Described plasma treatment specifically comprises: select plasma etching equipment for use, adopt CF
4, SF
6Or CF
4With SF
6Mist was handled fringe region of the described semiconductor-based ends 200 3 seconds to 5 minutes, was formed on the tomography and the burr at edge, the semiconductor-based ends 200 until removal.
In one embodiment, the concrete technological parameter of described plasma treatment is: select plasma etching equipment for use, CF
4Flow is 10SCCM to 200SCCM, handles fringe region of the described semiconductor-based ends 200 3 seconds to 5 minutes.
In another embodiment, the concrete technological parameter of described plasma treatment is: select plasma etching equipment for use, SF
6Flow is 10SCCM to 200SCCM, handles fringe region of the described semiconductor-based ends 200 3 seconds to 5 minutes.
In another embodiment, the concrete technological parameter of described plasma treatment is: select plasma etching equipment for use, CF
4Flow is 10SCCM to 200SCCM, SF
6Flow is 10SCCM to 200SCCM, handles fringe region of the described semiconductor-based ends 200 3 seconds to 5 minutes.
Step S103 removes the natural oxidizing layer of described silicon area.
The technology of removing the natural oxidizing layer of described silicon area can be that chemical reagent is removed or plasma bombardment is removed technology, and the natural oxidizing layer of removing described silicon area is used to provide the quality of the metal silicide of follow-up formation.
Before the natural oxidizing layer step of removing described silicon area, also comprise carrying out cleaning procedure in the described semiconductor-based end 200.
Described cleaning procedure is used to remove particle and the dust that is formed on the substrate of the semiconductor-based ends 200.
Step S104 forms metal level at described silicon area.
With reference to figure 8, described metal level 240 materials can be Ti, Co or Ni, and the technology of described formation metal level 240 can form technology, for example physical gas-phase deposition for existing metal level.
Described metal level 240 forms metal silicide with the silicon atom of described silicon area in subsequent technique.
Step S105 forms protective layer at described layer on surface of metal.
With reference to figure 9, described protective layer 250 is used to protect described metal level 240, avoids described metal level 240 to be exposed in the air oxidized.
Described protective layer 250 materials can be TiN; The technology of described formation protective layer 250 can form technology, for example physical gas-phase deposition for existing protective layer.
It is to be noted; be exposed in the air oxidized for fear of described metal level 240; the formation technology of described metal level 240 and the formation technology of described protective layer 250 can form in same depositing system, thereby it is oxidized to avoid metal level 240 to be exposed in the air.
Step S106 to annealing at the described semiconductor-based end that is formed with metal level, forms metal silicide layer.
With reference to Figure 10, described annealing process is annealed in quick anneal oven, and described annealing process can be with reference to existing metal silicide annealing process condition, until forming metal silicide layer 260.
With reference to Figure 11; the formation method of described self-aligned metal silicate also comprises removes unnecessary metal level 240; form metal silicide layer among the step S106 and can not consume all metal levels 240 usually; after the completing steps S106; usually also have certain metal level 240 remnants at metal silicide layer; the present invention also comprises and removes protective layer 250 and remove unreacted metal layer 240 after forming metal silicide layer 260.
Described removal protective layer 250 and removal unreacted metal layer 240 are removed technology for existing chemical reagent, here repeat no more.
The present invention is by carrying out plasma treatment to semiconductor substrate 200 edges, other zones at the semiconductor-based end 200 in the attenuating subsequent technique form particle contaminations, improved the yield of self-aligned metal silicate technology, and adopt 0 millimeter to 2 millimeters of plasma treatment fringe region of the described semiconductor-based ends 200, take into full account the yield of production practicality and product.
Though the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art without departing from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (11)
1. the formation method of a self-aligned metal silicate is characterized in that, comprising:
The semiconductor-based end is provided, and described semiconductor-based basal surface has a silicon area at least;
Using plasma is handled described semiconductor-based feather edge zone;
Remove the natural oxidizing layer of described silicon area;
Form metal level at described silicon area;
Form protective layer at described layer on surface of metal;
To annealing at the described semiconductor-based end that is formed with metal level, form metal silicide layer.
2. the formation method of self-aligned metal silicate as claimed in claim 1 is characterized in that, described fringe region is greater than 0 millimeter and smaller or equal to 2 millimeters zone along the semiconductor-based feather edge of radial direction of described semiconductor-based end distance.
3. the formation method of self-aligned metal silicate as claimed in claim 1 is characterized in that, using plasma is handled described semiconductor-based feather edge zone and specifically comprised: select plasma etching equipment for use, adopt CF
4, SF
6Or CF
4With SF
6Mist was handled described semiconductor-based feather edge zone 3 seconds to 5 minutes.
4. the formation method of self-aligned metal silicate as claimed in claim 3 is characterized in that, selects plasma etching equipment for use, CF
4Flow is 10SCCM to 200SCCM, handles fringe region of the described semiconductor-based ends 200 3 seconds to 5 minutes.
5. the formation method of self-aligned metal silicate as claimed in claim 3 is characterized in that, selects plasma etching equipment for use, SF
6Flow is 10SCCM to 200SCCM, handles described semiconductor-based feather edge zone 3 seconds to 5 minutes.
6. the formation method of self-aligned metal silicate as claimed in claim 3 is characterized in that, selects plasma etching equipment for use, CF
4Flow is 10SCCM to 200SCCM, SF
6Flow is 10SCCM to 200SCCM, handles described semiconductor-based feather edge zone 3 seconds to 5 minutes.
7. the formation method of self-aligned metal silicate as claimed in claim 1 is characterized in that, the formation technology of described metal level is physical gas-phase deposition.
8. the formation method of self-aligned metal silicate as claimed in claim 1 is characterized in that, the material of described metal level is Ti, Co or Ni.
9. the formation method of self-aligned metal silicate as claimed in claim 1 is characterized in that, the material of described protective layer is TiN.
10. the formation method of self-aligned metal silicate as claimed in claim 1 is characterized in that, the formation technology of described protective layer is physical gas-phase deposition.
11. the formation method of self-aligned metal silicate as claimed in claim 1 is characterized in that, also comprises
Step: remove protective layer and unreacted metal layer thereof.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2010100225670A CN102122613A (en) | 2010-01-08 | 2010-01-08 | Method for forming self-aligning metal silicide |
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| CN2010100225670A CN102122613A (en) | 2010-01-08 | 2010-01-08 | Method for forming self-aligning metal silicide |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102691066A (en) * | 2012-06-20 | 2012-09-26 | 苏州大学 | Method and device for treating burrs of electrode plate of lithium battery |
| CN102694148A (en) * | 2012-05-28 | 2012-09-26 | 东莞新能源科技有限公司 | Dry-process deburring method for positive plate of lithium ion battery |
| CN102903886A (en) * | 2012-08-13 | 2013-01-30 | 南京大学 | Method for removing battery electrode sheet burr by corroding with dry method |
| CN113078102A (en) * | 2021-03-24 | 2021-07-06 | 长鑫存储技术有限公司 | Method for manufacturing semiconductor structure |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005142227A (en) * | 2003-11-04 | 2005-06-02 | Matsushita Electric Ind Co Ltd | Plasma processing method and processing apparatus |
| US20060079087A1 (en) * | 2004-10-13 | 2006-04-13 | Fujitsu Limited | Method of producing semiconductor device |
| US20070082494A1 (en) * | 2005-10-03 | 2007-04-12 | United Microelectronics Corp. | Method for forming silicide layer |
| US20080311758A1 (en) * | 2007-06-14 | 2008-12-18 | Lam Research Corporation | Methods of and apparatus for protecting a region of process exlusion adjacent to a region of process performance in a process chamber |
-
2010
- 2010-01-08 CN CN2010100225670A patent/CN102122613A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005142227A (en) * | 2003-11-04 | 2005-06-02 | Matsushita Electric Ind Co Ltd | Plasma processing method and processing apparatus |
| US20060079087A1 (en) * | 2004-10-13 | 2006-04-13 | Fujitsu Limited | Method of producing semiconductor device |
| US20070082494A1 (en) * | 2005-10-03 | 2007-04-12 | United Microelectronics Corp. | Method for forming silicide layer |
| US20080311758A1 (en) * | 2007-06-14 | 2008-12-18 | Lam Research Corporation | Methods of and apparatus for protecting a region of process exlusion adjacent to a region of process performance in a process chamber |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102694148A (en) * | 2012-05-28 | 2012-09-26 | 东莞新能源科技有限公司 | Dry-process deburring method for positive plate of lithium ion battery |
| CN102691066A (en) * | 2012-06-20 | 2012-09-26 | 苏州大学 | Method and device for treating burrs of electrode plate of lithium battery |
| CN102903886A (en) * | 2012-08-13 | 2013-01-30 | 南京大学 | Method for removing battery electrode sheet burr by corroding with dry method |
| CN113078102A (en) * | 2021-03-24 | 2021-07-06 | 长鑫存储技术有限公司 | Method for manufacturing semiconductor structure |
| CN113078102B (en) * | 2021-03-24 | 2022-04-29 | 长鑫存储技术有限公司 | Method for manufacturing semiconductor structure |
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