CN102054668A - 电子束正性光刻胶Zep 520 掩蔽介质刻蚀的方法 - Google Patents

电子束正性光刻胶Zep 520 掩蔽介质刻蚀的方法 Download PDF

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CN102054668A
CN102054668A CN2009102367194A CN200910236719A CN102054668A CN 102054668 A CN102054668 A CN 102054668A CN 2009102367194 A CN2009102367194 A CN 2009102367194A CN 200910236719 A CN200910236719 A CN 200910236719A CN 102054668 A CN102054668 A CN 102054668A
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徐秋霞
周华杰
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Ruili Flat Core Microelectronics Guangzhou Co Ltd
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Abstract

一种电子束正性光刻胶Zep 520掩蔽介质刻蚀的方法，在介质瞙上沉积一层α-Si薄膜，然后将电子束直写光刻技术得到的高分辨率Zep 520胶图形作为掩瞙，用氯(Cl)基等离子刻蚀α-Si，将高分辨率Zep 520胶图形转移到其下层的α-Si瞙上，接着去除Zep 520胶，进一步利用具有良好保真性的α-Si瞙图形为掩膜，采用F基反应离子刻蚀介质形成凹槽图形，最后用湿法或干法将α-Si瞙去净即可。本发明提供的方法简单可行，完全与CMOS工艺兼容，不增加专门的设备，成本低，易于在介质中实现高精度的纳米尺度凹槽图形，解决了新结构CMOS器件制备中的一大难题。

Description

电子束正性光刻胶Zep 520 掩蔽介质刻蚀的方法
技术领域
本发明属于纳米尺度的半导体器件制备工艺，具体涉及一种纳米级介质图形制备过程中一种正性电子束光刻胶Zep520不能抗F基反应离子刻蚀的解决方法。为新结构器件制备中介质上纳米尺度凹槽图形的加工成形得以圆满实现。
技术背景
在亚50纳米CMOS集成技术进一步等比例缩小的发展中，为克服平面体硅CMOS固有的越来越严重的短沟道效应和大的漏电流问题，新器件结构层出不穷，如FinFET，多栅/环栅CMOS FET，纳米线等，在这些新结构器件的制备过程中，必然会遇到要在介质中刻蚀出较深的纳米尺度的凹槽图形，要得到这么窄的凹槽，首先需要有高分辨率的电子束光刻胶，Zep520正性电子束光刻胶是首选，采用这种胶的电子束直写光刻可以得到高分辨的纳米尺度的光刻胶掩瞙图形。但采用这种胶其在常规的介质刻蚀工艺中抗刻蚀性能很差，它很快地与氟(F)基等离子体反应，而发生塑性流动，使凹槽胶图形严重毁坏。本发明为使电子束直写光刻Zep 520胶制备的精细图形能在介质中保留下来，首先让Zep 520胶成形在α-Si上，这样就可以采用一种氯(Cl)基等离子体刻蚀α-Si，使Zep 520胶图形首先转移到α-Si上，然后去掉Zep 520胶，用α-Si图形掩蔽介质，在F基反应离子刻蚀中完成介质刻蚀，得到纳米尺度凹槽图形，最后用湿法或干法去掉α-Si即可。这种方法由于与常规的CMOS工艺完全兼容，方便可靠，而且能获得精细的纳米尺度凹槽图形，解决了新结构CMOS器件制备中的一大难题。
发明内容
本发明的目的在于提供一种电子束正性光刻胶Zep 520掩蔽介质刻蚀的方法，以克服介质中凹槽图形制备过程中正性电子束光刻胶Zep 520不能经受F基反应离子刻蚀的问题。
为实现上述目的，本发明提供的方法，是先在介质瞙上沉积一层α-Si薄膜，然后将电子束直写光刻技术得到的高分辨率Zep 520胶图形作为掩瞙，用Cl基等离子刻蚀α-Si(避开了F基等离子体)，将高分辨率Zep 520胶图形转移到其下层的α-Si瞙上，接着去除Zep 520胶，进一步利用具有良好保真性的α-Si瞙图形为掩膜，采用F基反应离子刻蚀介质形成凹槽图形，最后用湿法或干法将α-Si瞙去净即可。本发明提供的方法简单可行，完全与CMOS工艺兼容，不增加专门的设备，成本低，易于在介质中实现高精度的纳米尺度凹槽图形。
详细地说，本发明的制备步骤包括：
1)在需要加工的介质上沉积一层α-Si薄膜，沉积温度520-550℃；
2)清洗，甩干，并在N2保护下进一步在高温炉口烘烤；
3)旋涂Zep 520电子束正性光刻胶；
4)在烘箱内烘烤，温度170-180℃，20-40分钟，这一步骤需要缓慢升降温；
5)电子束直写曝光并显影后，得到高分辨率Zep 520胶纳米尺度凹槽图形；
6)烘烤130-140℃，30-50分钟
7)采用Cl基等离子体，以Zep520胶为掩膜图形，刻蚀α-Si瞙，使Zep520胶图形高保真度地转移到α-Si瞙上；
8)去净Zep 520正性电子束胶；
9)以α-Si瞙为掩膜图形，在F基反应离子体中刻蚀介质层，使α-Si图形高保真度地转移到介质中；
10)去α-Si净，完成了介质中纳米尺度凹槽精细图形的加工。
本发明的效果在于：
1、为克服Zep 520胶不抗F基刻蚀的问题，根据Zep 520胶耐Cl基刻蚀的特性，巧妙地利用α-Si作为中间过渡层，用Cl基等离子刻蚀将Zep520胶图形转移到α-Si上，因为α-Si容易被Cl基等离子体刻蚀，而且刻蚀精度高；
2、利用α-Si为掩膜，采用F基中反应离子刻蚀将高分辨率的α-Si图形转移到介质中，因为在F基反应离子刻蚀中，介质膜对α-Si瞙有很高的刻蚀选择比，这样就能保证精细图形的制备；
3、α-Si瞙的去除不论是湿法还是干法，对介质的腐蚀速率极低，不会对介质图形造成损伤。
附图说明
图1给出了Zep 520电子束正性光刻胶在F基等离子体中刻蚀介质后的SEM剖面照片，Zep 520胶塑性流动并毁坏，介质没法继续刻蚀下去。
图2给出了以α-Si为掩膜用F基反应离子刻蚀介质后剖面照片，介质凹槽图形完好，三层介质已刻蚀净。
图1中：1-Zep 520电子束正胶；2-介质膜；3-硅衬底。
图2中：：1-α-Si膜；2-介质膜；3-硅衬底。
具体实施方式
本发明一种克服电子束正性光刻胶Zep 520不能掩蔽介质刻蚀的方法，其工艺步骤如下：
1)在需要加工的介质上沉积一层α-Si薄膜，α-Si膜厚度120-150纳米，沉积温度520-550℃；
2)清洗，甩干，并在N2保护下800度高温炉口烘30分钟；
3)旋涂Zep 520电子束正性光刻胶，胶厚度400-600纳米；
4)在烘箱内烘烤，温度170-180℃，20-40分钟，需要缓慢升降温；
5)电子束直写曝光并显影后，得到高分辨率Zep 520胶纳米尺度凹槽图形；
6)烘烤130-140℃，30-50分钟
7)采用Cl基等离子体，以Zep 520胶为掩膜图形，刻蚀α-Si瞙，使Zep 520胶图形高保真度地转移到α-Si瞙上；
8)去净Zep 520正性电子束胶；
9)以α-Si瞙为掩膜图形，在CF4/CHF3混合气体中反应离子刻蚀介质层，使α-Si图形高保真度地转移到介质中；
10)采用NH4OH水溶液去净α-Si，完成了介质中纳米尺度凹槽精细图形的加工。

Claims (7)

1.一种电子束正性光刻胶Zep 520掩蔽介质刻蚀的方法，其主要步骤如下：
1)在需要加工的介质上沉积一层α-Si薄膜，沉积温度520-550℃；
2)清洗，甩干，并在N2保护下进一步烘干；
3)旋涂Zep 520电子束正性光刻胶；
4)缓慢升温至170-180℃烘烤20-40分钟，并缓慢降温；
5)电子束直写曝光并显影后，得到Zep 520胶纳米尺度凹槽图形；
6)烘烤130-140℃，30-50分钟；
7)采用氯基等离子体，以Zep 520胶为掩膜图形，刻蚀α-Si瞙，使Zep 520胶图形转移到α-Si瞙上；
8)去净Zep 520正性电子束胶；
9)以α-Si瞙为掩膜图形，在氟基反应离子体中刻蚀介质层，使α-Si图形转移到介质中；
10)去净α-Si，完成了介质中纳米尺度凹槽图形的加工。
2.根据权利要求1所述的方法，其中，步骤1中α-Si瞙厚度视被刻蚀的介质瞙的厚度和瞙质而定，在70-200nm之间。
3.根据权利要求1所述的方法，其中，步骤3中Zep 520胶的胶瞙厚度视α-Si瞙厚度而定，在200-600nm之间。
4.根据权利要求1所述的方法，其中，步骤7中的氯基等离子体为Cl2/He、Cl2/Ar、或Cl2/O2的混合气体源。
5.根据权利要求1所述的方法，其中，步骤8中Zep 520胶的去除用O2等离子体去除，或用湿法3#液(H2SO4∶H2O2＝3∶1-5∶3)去除。
6.根据权利要求1所述的方法，其中，步骤9中F基反应离子体为CF4、CHF3、C3F8、C4F8、NF3或其混合气源。
7.根据权利要求1所述的方法，其中，步骤10中α-Si的去除是用氯基等离子体或NH4OH的水溶液去除。
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