CN102053240A - Reconnaissance receiving processor for synthetic aperture radar signal - Google Patents
Reconnaissance receiving processor for synthetic aperture radar signal Download PDFInfo
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Abstract
The invention relates to a reconnaissance receiving processor for a synthetic aperture radar signal and belongs to the field of radar signal reconnaissance. The reconnaissance receiving processor comprises a display control module, a clock source module, a search-tracking module, a data acquisition module, a signal processing module, a data storage module and a data dump module, wherein the display control module is mutually connected with the clock source module, the data acquisition module, the signal processing module, the data storage module and the data dump module; the clock source module and the data acquisition module are mutually connected; the clock source module and the search-tracking module are mutually connected; the data acquisition module and the search-tracking module are mutually connected; the data acquisition module and the signal processing module are mutually connected; the search-tracking module and the signal processing module are mutually connected; the signal processing module and the data storage module are mutually connected; and the data storage module and the data dump module are mutually connected. The reconnaissance receiving processor combines narrow-band searching with broad-band parameter measurement and widens the working dynamic range of the whole system. The signal searching supports various work modes, and the interference resistance is realized by comparing the searched signal parameters with interested signal parameters.
Description
Technical field
The present invention relates to a kind of synthetic aperture radar (SAR) signal reconnaissance recipient processor, belong to radar signal and scout the field.
Background technology
SAR is a kind of radar that obtains full resolution pricture, utilizes the motion of carrier of radar to simulate wide aperture antenna, and it can find target hidden and camouflage.For under the situation of not losing range resolution, increase investigative range, SAR adopts the linear FM signal with long-pending characteristic of wide bandwidth when big usually.By adopting linear FM signal, SAR not only improves detectivity, and has had low intercepting and capturing.At noncooperative SAR signal, the hyundai electronics reconnaissance system is except requiring to have wide input bandwidth, high sensitivity and resolution, the big dynamic range, also must handling in real time the signal of collecting; The output of receiver simultaneously must digitizing, so as to analyze with digital processing unit, sorting and identification input signal.
Therefore, collect as far as possible the full detail of input signal, in real time handle the input signal collect, export the on-the-spot practicality in desirable numerical information, digit pulse describing word (PDW) and battlefield thereof and become basic demand the modern electronic warfare receiver.
Summary of the invention
The present invention proposes a kind of synthetic-aperture radar signal reconnaissance recipient processor, the SAR signal is carried out investigations to solve existing ferret receiver technology Time Bandwidth is wide inadequately, dynamic range is big inadequately, can not handle the problem that obtains the digit pulse describing word, can not store the magnanimity high-speed data in real time.
A kind of synthetic-aperture radar signal reconnaissance of the present invention recipient processor comprises showing controls module, clock source module, search tracking module, data acquisition module, signal processing module, data memory module, data dump module; It is interconnected to show control module and clock source module, data acquisition module, signal processing module, data memory module and data dump module, clock source module and data acquisition module, clock source module and search tracking module, data acquisition module and the interconnection of search tracking module, data acquisition module and signal processing module, search tracking module and signal processing module, signal processing module and data memory module, data memory module and data dump module interconnects; Show the control module and send drainage pattern, search tracking parameter, signal judgment criterion, thresholding pattern, parameter feedback kind, the data dump parameter command of setting by the operator to data acquisition module, search tracking module, signal processing module, data memory module, data dump module respectively, and received signal the processing module signal processing results and the pulse envelope that report, show; The search tracking module carries out the frequency sweep search signal in the frequency search range that shows the setting of control module, signal trace ripple door trigger data acquisition module is gathered signal; The clock source module provides required high frequency sampled clock signal, the sampling clock that data acquisition module receive clock source provides, baseband I Q signal to the outside input carries out analog to digital conversion, and data are carried out format analysis processing to satisfy the requirement to data of signal processing module and data memory module; Signal processing module receives the raw data that data acquisition module sends, the method that adopts the frequency domain channel multiphase filtering to combine with the phase difference instantaneous frequency measurement is carried out real-time parameter to signal and is measured and form the digit pulse describing word, signal processing module is divided into the I/Q two-way with raw data, then raw data and PDW, envelope data is distributed to data memory module; The data dump module from storage array with data read to FPGA, FPGA merges data in order according to the header of data block, is reduced to original data sequence.
Wherein search module carries out signal search is provided with low-converter according to the minimum value of swept frequency range initial frequency point, and this Frequency point carried out Threshold detection, value of frequency point with current low-converter after detecting adds that the narrow band filter bandwidth is set to the new frequency of low-converter afterwards, again new Frequency point was carried out Threshold detection, the maximal value of so advancing up to swept frequency range is a loop ends, after two circulations Search Results and signal judgment criterion are compared, the bandwidth range that compares measured signal, pulsewidth scope and pulse repetition time scope, when Search Results satisfies judgment criterion, think to search signal, provide tracking gate signal is followed the tracks of; If do not satisfy, then restart search.
Wherein search module directly is provided with and shows the low-converter working frequency points that the control module provides, and judges whether this place exists signal; Maybe the signal message that the signal parameter that searches and other instruments are obtained compares, and judges that whether signal exists.
The clock source module provides 24MHz and 1500MHz clock for respectively search tracking module and data acquisition module.
The search tracking module is supported multiple search work pattern, and when the known signal working frequency points, the search tracking module is directly pointed out search signal in respective tones; When known signal working frequency points and parameter but when uncertain, the first voluntarily search signal of search tracking module is with the signal parameter that searches and known just enter tracking after confirming; When interested in a certain frequency band signals, the search tracking module carries out scanning search by the narrow-band frequency-sweeping mode to this frequency range, judged whether signal, the search tracking module is that stepping progressively is provided with low-converter with the narrow band filter bandwidth in the search rate scope that shows the setting of control module during narrow-band frequency-sweeping, and the signal of the different frequent points of low-converter output was carried out Threshold detection; Whole search rate scope is carried out after the two-pass scan, if scanning result satisfies the signal criterion that shows the setting of control module then provides tracking gate and utilize tracking gate that signal is carried out data acquisition, otherwise in the search rate scope signal is searched for again; In tracing process, if dropout, the search tracking module is remembered tracking according to the information before the dropout to signal, surpasses up to the dropout time and shows just search signal again of threshold value that the control module is provided with.
The tracking gate that data acquisition module reception search tracking module provides is gathered complex signal, this module comprises two synchronous receiving cables, the simulating signal of each receiving cable is earlier by an analog to digital converter, be sent to a deserializer then and reduce data rate, data behind the reduction of speed are written into two high capacity push-up storages and carry out buffer memory, and latter two passage buffer storage data are read in by field programmable gate array and handled.
SAR signal reconnaissance recipient processor workflow of the present invention is as follows: the operator is by showing parameter commands such as control module settings drainage pattern, search tracking parameter, signal judgment criterion, thresholding pattern.The search tracking module is searched for according to the running parameter that receives, measurement result and signal judgment criterion is compared after searching signal, determine be after the signal then with semaphore lock, provide tracking gate afterwards and control the output gain of low-converter in real time.Tracking gate is sent to the enable signal of data acquisition module as data acquisition, enables the i/q signal of base band to be gathered when effective.The data that collect are packaged into the appointment data form and deliver to signal processing module and carry out that real-time parameter is measured and measurement result is generated PDW.Signal processing module is with I/Q raw data, envelope data and handle the PDW that produces in real time and deliver to the data memory module storage, simultaneously the envelope data that extracts and PDW is sent to show the control module and show.The data dump module is handled to computing machine by Optical Fiber Transmission after the data in the data memory module are sorted afterwards.
Beneficial effect of the present invention:
1) the present invention supports multiple signal search to follow the tracks of situation, and the operator can be provided with flexibly according to signal environment, operating experience and information data.
2) the present invention supports the several data memory module, adopts flexibly according to the different of reconnaissance mission, has effectively avoided the storage to invalid data, lays the foundation for improve the efficient of dealing with the work afterwards.
3) the present invention has the signal trace function, when signal can not be detected in real time by the receiver that dies down by force also can with under the signals collecting for the end of job after the researchist use more excellent algorithm to analyze.
4) the present invention has super large bandwidth SAR signal is carried out data acquisition, real-time parameter measurement function, can provide the accurate parameters of broadband SAR signal in real time and form PDW.
5) analog to digital conversion speed of the present invention reaches the Gsps level, and can store the data of GB/s stage speed, and be a minute level lasting storage time.
6) the present invention adopts standardization, modular a plurality of CPCI integrated circuit boards to make up, and has to realize simply advantages such as superior performance.
Description of drawings
Fig. 1 SAR signal reconnaissance of the present invention recipient processor structural drawing;
Fig. 2 search tracking module of the present invention functional block diagram;
Fig. 3 data acquisition module functional block diagram of the present invention;
Fig. 4 signal processing module functional block diagram of the present invention;
Fig. 5 data memory module functional block diagram of the present invention;
Embodiment
For making purpose of the present invention, technical scheme and advantage more clear, technical scheme of the present invention is described in further detail below in conjunction with drawings and Examples.
For sensitivity and the dynamic range that improves system works, system works is taked ' arrowband search, wide-band width measurement ' strategy, in the frequency range that is provided with, scan, utilize high low speed modulus conversion chip of quantization digit and field programmable gate array that the narrow band signal of receiving cable output is handled in each working frequency points, reset new frequency after handling, the intact back of frequency sweep rough measure obtain signal the time wide, bandwidth, PRT information, when these information satisfy the signal decision condition, just think signal is arranged, select suitable working frequency points and wave filter at receive channel this moment, triggering system enters the tracking accepting state, and broadband signal is gathered; Processing to narrow band signal also comprises continuous supervisory signal amplitude, receives the real-time control of passage output gain to achieve a butt joint, and the signal of optimum range is provided for the relatively low hypervelocity modulus conversion chip of quantization digit.The The data frequency domain channel multiphase filtering of collection and the method for phase difference instantaneous frequency measurement are handled in real time, obtained the accurate parameters of SAR signal and form digit pulse describing word (PDW).Store the raw data of gathering, the PDW that produces in real time and envelope into data memory module with the superelevation speed of GB/s level simultaneously, by data dump module data read when needing to analyze afterwards.
The system that present embodiment provides forms (as Fig. 1) by apparent control, clock source, data acquisition, search tracking, signal Processing, data storage, data dump, eight modules of industry control cabinet.Concrete workflow is as follows:
1, running parameter setting
Show the control module and send parameter commands such as drainage pattern, search tracking parameter, signal judgment criterion, thresholding pattern, parameter feedback kind to search tracking, data acquisition, signal Processing, data storage dump module.As select processor operation in all raw data of storage, formulating in the frequency range automatically search signal, narrow band filter bandwidth 10MHz, search tracking frequencies scope 1～12GHz, signal minimum bandwidth 100MHz, signal minimum pulse width 20us, signal minimum pulse repetition period (PRT) 600us, the maximum repetition period 1200us of pulse, search tracking module and real-time parameter and measure and all adopt adaptive threshold.
2, search is followed the tracks of
The 24MHz clock that search tracking module receive clock source module produces is as work clock.This module (as Fig. 2) comprises two receiving cables, and each receiving cable front end all has an ADC (AD6645), to narrowband baseband i/q signal Direct Sampling, sampling rate 24MHz.Digital signal after the sampling is input to DDC chip (ISL5416), and NCO (digital local oscillator) mixing with DDC inside obtains the baseband I Q signal, because present embodiment input is baseband signal, so NCO is set to 0.Carry out CIC filtering extraction, two-stage narrow-band filtering extraction processing afterwards, the narrow band filter bandwidth is 10MHz, 3MHz and 1MHz optional (by showing the setting of control module), the corresponding extraction factor is respectively 1*1*1,1*1*4 and 2*1*4, and sampling rate is reduced to 24Msps, 6Msps and 3Msps respectively.Baseband I Q signal after sampling rate reduces is sent to FPGA (AlteraEP2S60F672).FPGA detects the I/Q data, judges whether this frequency has signal.After having judged current local frequency is added 10MHz, 3MHz or 1MHz (being consistent with the narrow band filter bandwidth), reset the local frequency of front end low-converter.Detect whether signal is arranged after setting up new local frequency, so circulation scans the termination frequency of swept frequency range up to the initial frequency from swept frequency range again.Comprehensive detection result compares the bandwidth of detected signal, pulsewidth, PRT and the judgment criterion that shows the setting of control module, if satisfy the criterion requirement, then thinks to detect the signal that needs, and provides tracking gate to data acquisition module.
The clock of search tracking module receive clock source module, to provide tracking gate all be to realize by sub-miniature A connector to data acquisition module.This module utilizes PMC backboard JN4 interface and signal processing module interconnected, thereby receives the parameter that shows the control module, low-converter is set by signal processing module.Signal trace ripple door trigger data acquisition module is gathered signal.In tracing process, if dropout then provides the memory tracking gate according to the information of several signal periods before losing signal is remembered tracking.Show the maximal memory tracking time that the control module is provided with if continuous memory is followed the tracks of to surpass, the search tracking module will be searched for again to signal.
Because the search tracking module is that narrow band signal is handled, and can adopt the relatively large low speed modulus conversion chip of dynamic range to handle; And data acquisition module is that ultra-broadband signal is gathered, and the hypervelocity modulus conversion chip dynamic range that is adopted is less relatively.The search tracking module is monitored the signal amplitude of low-converter output all the time, to realize real-time control to the low-converter output gain, the signal that amplitude the best is provided to data acquisition module sends to the gain control amount signal processing module for parameter measurement and processing reference use afterwards simultaneously with indirect raising system works dynamic range.
3, data acquisition
The sampling clock that data acquisition module receive clock source provides, the baseband I Q signal that the outside is imported carries out analog to digital conversion.For the SAR signal to the super large bandwidth is sampled, analog-to-digital clock is the GHz level, the data transfer rate that produces also is the GB/s level, therefore data after A is gone here and there and changes, and the demultiplexing parallel transmission is to field programmable gate array (FPGA) after the changing down.In FPGA, data are carried out DC processing, and data are carried out format analysis processing to satisfy the requirement to data of signal processing module and data memory module.
Data acquisition module (as Fig. 3) comprises two receiving cables, each receiving cable front end all has an ADC (TS83102), SAR signal sampling to base band, sampling rate 1500Msps, quantization digit 10bit, the digital signal after the sampling is input to string and the conversion that DEMUX (TS81102) carries out 1:8.The data of each receiving cable of conversion back become 8 tunnel parallel (total bit wide 80bit), and speed is reduced to 187.5MHz, delivers to high capacity FIFO (IDT72T40118) and carries out buffer memory.The data of FIFO are sent to FPGA (AlteraEP2S60F672), go direct current, packing to handle.The data of handling are carried out 8:1 also adopts the synchronous mode of differential source to deliver to the signal processing module processing by the CPCI interconnection in string conversion back.Source synchronous clock is 400MHz.
4, signal Processing
Signal processing module receives the raw data that data acquisition module sends.The method that adopts the frequency domain channel multiphase filtering to combine with the phase difference instantaneous frequency measurement is carried out real-time parameter to signal and is measured and form digit pulse describing word (PDW).In order in a processor big bandwidth signal to be realized the high-speed real-time processing, the multiphase filter in the frequency domain channel processing is realized by the thought that resource time division multiplex and parallel processing combine.Make full use of the time-frequency characteristic of SAR signal, obtain the accurate parameters of signal when merging a plurality of channel measurement fructufy.When parameter is measured in real time with raw data by appointment form pack and raw data extracted the back and produce corresponding envelope data bag.
In order to save storage space, reduce parameter measurement working pressure afterwards, signal processing module is supported multiple working method to memory module transmission raw data: all raw data all send, transmission, timed sending when signal parameter changes, and the selection of working method is finished by showing the control module by the operator.PDW and envelope data amount are smaller, carry out storage fully.PDW, envelope and raw data adopt the synchronous form of differential source to be sent to data memory module by also going here and there to change.Part PDW and envelope, system state word are sent to apparent control module and show.Signal processing module has the function of communicating by letter with low-converter with the search tracking module simultaneously.This module will show the parameter of controlling module and be transmitted to search tracking module and low-converter, the status word that the search tracking module is produced and the controlled variable of low-converter is forwarded to respectively shows control module and low-converter.
Signal processing module (as Fig. 4) comprises a slice DSP (TMS320C6455) and a slice FPGA (XilinxVirtex4 XC4VSX55), and the EMIFA bus of FPGA and DSP is interconnected.FPGA receives the data of data acquisition module and utilizes source synchronous clock to store push-up storage (FIFO) into after serial data and the conversion, and local 100MHz clock is divided into three the tunnel with data after FIFO reads.First via data are that unit packs with 16KByte after carrying out format conversion.16360Byte is raw data (a 16360*8/10=13088 sampled point) among the 16KByte, information such as the time that 24 bytes are data, sampling rate, low-converter local oscillator.Second circuit-switched data is sent to the real-time parameter measurement module and carries out the real-time parameter measurement and form the pulse describing word in real time.The real-time parameter high-acruracy survey realizes by the frequency domain digital channelized receiver cascade phase difference instantaneous frequency measurement of one 64 channel.To handle its resource and take into account requirement simultaneously in order to save, fully adopt time-multiplexed thought in the receiver design, adopt 8 needed processor resources of channel to realize the receiver of 64 channels processor processing speed.The Third Road data are in order to form envelope data.Because what show that the control module selects is all raw data of storage, so raw data, PDW, envelope data all are distributed to 4 memory boards storages of data memory module.
FPGA obtains running parameter by the EMIFA interface of DSP from showing the control module.FPGA receives that the parameter that will belong to data acquisition module, search tracking module behind the parameter information is forwarded to each module.Showing the EMIFA interface of control module by DSP reads PDW, envelope and system status information from FPGA and shows.The FPGA of signal processing module and low-converter also have communication interface, and the parameter that the search tracking module produces sends to low-converter by this interface.
The cpci bus of signal processing module by self defined interface is connected with data acquisition module, the JN4 by the PMC interface with search for tracking module and link to each other, the J30J connector by Huada Science ﹠ Technology Co., Ltd., Shaanxi's production is connected with low-converter.
5, data storage dump
Data storage dump module (as Fig. 5) closes the road plate by four memory boards, a blocks of data and a fibre optic plate is formed.Every memory board comprises a slice Xilinx Virtex4 XCVLX25 FPGA and two XilinxSpartan3 FPGA, 96 NAND (Samsung K9WBG08U1A).Virtex4 links to each other with Spartan3 by the IO pin, 48 NAND of every Spartan3 control.The data of sending of signal acquisition module are cached to Virtex4 earlier, and to Spartan3, Spartan3 delivers to the NAND storage with data to Virtex4 with data distribution.During reading of data, data are closed the road plate data are read into FPGA and sort in proper order according to the data in when storage from 4 memory boards, and the data after the ordering are gone out by the Optical Fiber Transmission of fibre optic plate.Whole storage system is supported the memory rate of 2GByte/s and the reading rate of 300MByte/s.
Four memory boards utilize the PCI9656 bridge chip to link to each other with apparent control module by cpci bus, close the road plate by the cpci bus and the data of self defined interface and link to each other.Data are closed the JN4 of road plate by PMC and are connected with fibre optic plate.
More than all modules be installed in the industry control cabinet based on the CPCI standard.Search tracking module, data acquisition module, signal processing module, data memory module adopt self defined interface interconnected by cpci bus.Cabinet uses the 220V alternating current, direct supply is provided for simultaneously each module.Present embodiment adopts the CPCI type industry control cabinet of ELMA company, and display, keyboard and mouse need external, use the 220V alternating current.
The present invention adopts the digital received technology, and the maximum complex signal bandwidth that can gather reaches 1200MHz, and the peak signal pulsewidth of energy acquisition process is 600us, produces PDW in real time.At present this SAR signal reconnaissance recipient processor has been successfully applied in the scouting to the SAR signal.
Claims (6)
1. a synthetic-aperture radar signal reconnaissance recipient processor comprises showing control module, clock source module, search tracking module, data acquisition module, signal processing module, data memory module, data dump module; It is characterized in that: it is interconnected to show control module and clock source module, data acquisition module, signal processing module, data memory module and data dump module, clock source module and data acquisition module, clock source module and search tracking module, data acquisition module and the interconnection of search tracking module, data acquisition module and signal processing module, search tracking module and signal processing module, signal processing module and data memory module, data memory module and data dump module interconnects; Wherein show the control module and send drainage pattern, search tracking parameter, signal judgment criterion, thresholding pattern, parameter feedback kind, the data dump parameter command of setting by the operator to data acquisition module, search tracking module, signal processing module, data memory module, data dump module respectively, and received signal the processing module signal processing results and the pulse envelope that report, show; The search tracking module carries out the frequency sweep search signal in the frequency search range that shows the setting of control module, signal trace ripple door trigger data acquisition module is gathered signal; The clock source module provides required high frequency sampled clock signal, the sampling clock that data acquisition module receive clock source provides, baseband I Q signal to the outside input carries out analog to digital conversion, and data are carried out format analysis processing to satisfy the requirement to data of signal processing module and data memory module; Signal processing module receives the raw data that data acquisition module sends, the method that adopts the frequency domain channel multiphase filtering to combine with the phase difference instantaneous frequency measurement is carried out real-time parameter to signal and is measured and form the digit pulse describing word, signal processing module is divided into the I/Q two-way with raw data, then raw data and PDW, envelope data is distributed to data memory module; The data dump module from storage array with data read to FPGA, FPGA merges data in order according to the header of data block, is reduced to original data sequence.
2. a kind of synthetic-aperture radar signal reconnaissance recipient processor according to claim 1, it is characterized in that: wherein search module carries out signal search is provided with low-converter according to the minimum value of swept frequency range initial frequency point, and this Frequency point carried out Threshold detection, value of frequency point with current low-converter after detecting adds that the narrow band filter bandwidth is set to the new frequency of low-converter afterwards, again new Frequency point was carried out Threshold detection, the maximal value of so advancing up to swept frequency range is a loop ends, after two circulations Search Results and signal judgment criterion are compared, the bandwidth range that compares measured signal, pulsewidth scope and pulse repetition time scope, when Search Results satisfies judgment criterion, think to search signal, provide tracking gate signal is followed the tracks of; If do not satisfy, then restart search.
3. a kind of synthetic-aperture radar signal reconnaissance recipient processor according to claim 1 and 2 is characterized in that: wherein search module directly is provided with and shows the low-converter working frequency points that the control module provides, and judges whether this place exists signal; Maybe the signal message that the signal parameter that searches and other instruments are obtained compares, and judges that whether signal exists.
4. a kind of synthetic-aperture radar signal reconnaissance recipient processor according to claim 1 and 2 is characterized in that: the clock source module provides 24MHz and 1500MHz clock for respectively search tracking module and data acquisition module.
5. a kind of synthetic-aperture radar signal reconnaissance recipient processor according to claim 1 and 2, it is characterized in that: the search tracking module is supported multiple search work pattern, when the known signal working frequency points, the search tracking module is directly pointed out search signal in respective tones; When known signal working frequency points and parameter but when uncertain, the first voluntarily search signal of search tracking module is with the signal parameter that searches and known just enter tracking after confirming; When interested in a certain frequency band signals, the search tracking module carries out scanning search by the narrow-band frequency-sweeping mode to this frequency range, judged whether signal, the search tracking module is that stepping progressively is provided with low-converter with the narrow band filter bandwidth in the search rate scope that shows the setting of control module during narrow-band frequency-sweeping, and the signal of the different frequent points of low-converter output was carried out Threshold detection; Whole search rate scope is carried out after the two-pass scan, if scanning result satisfies the signal criterion that shows the setting of control module then provides tracking gate and utilize tracking gate that signal is carried out data acquisition, otherwise in the search rate scope signal is searched for again; In tracing process, if dropout, the search tracking module is remembered tracking according to the information before the dropout to signal, surpasses up to the dropout time and shows just search signal again of threshold value that the control module is provided with.
6. a kind of synthetic-aperture radar signal reconnaissance recipient processor according to claim 1 and 2, it is characterized in that: the tracking gate that data acquisition module reception search tracking module provides is gathered complex signal, this module comprises two synchronous receiving cables, the simulating signal of each receiving cable is earlier by an analog to digital converter, be sent to a deserializer then and reduce data rate, data behind the reduction of speed are written into two high capacity push-up storages and carry out buffer memory, and latter two passage buffer storage data are read in by field programmable gate array and handled.
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| CN102723977A (en) * | 2012-06-30 | 2012-10-10 | 熊猫电子集团有限公司 | Shortwave eight-channel adaptive array signal processor based on CPCI (Compact Peripheral Component Interconnect) bus |
| CN102723977B (en) * | 2012-06-30 | 2015-05-13 | 熊猫电子集团有限公司 | Shortwave eight-channel adaptive array signal processor based on CPCI (Compact Peripheral Component Interconnect) bus |
| CN103199879A (en) * | 2013-04-11 | 2013-07-10 | 中国电子科技集团公司第十四研究所 | Digital receiver signal detection method |
| CN103869317A (en) * | 2014-04-02 | 2014-06-18 | 清华大学 | Synthetic aperture radar real-time signal processing device |
| CN104536923A (en) * | 2014-11-27 | 2015-04-22 | 成都龙腾中远信息技术有限公司 | Multichannel interference signal acquisition and processing verification system |
| CN109617631A (en) * | 2018-12-28 | 2019-04-12 | 华航高科(北京)技术有限公司 | Reconnaissance system adaptive reception method based on the measurement of digital channelizing instantaneous parameters |
| CN109617631B (en) * | 2018-12-28 | 2021-09-14 | 华航高科(北京)技术有限公司 | Adaptive receiving method of reconnaissance system based on digital channelized instantaneous parameter measurement |
| CN111262600A (en) * | 2020-03-04 | 2020-06-09 | 四川九洲电器集团有限责任公司 | Real-time searching method and device for broadband digital signal frequency |
| CN112904285A (en) * | 2021-02-03 | 2021-06-04 | 北京航空航天大学杭州创新研究院 | Signal acquisition method and device based on FPGA chip |
| CN112904285B (en) * | 2021-02-03 | 2023-12-15 | 北京航空航天大学杭州创新研究院 | Signal acquisition method and device based on FPGA chip |
| CN113219424A (en) * | 2021-04-29 | 2021-08-06 | 中国船舶重工集团公司第七二三研究所 | Parallel output multi-channel instantaneous frequency measurement system |
| CN116087890A (en) * | 2023-04-10 | 2023-05-09 | 北京中科睿信科技有限公司 | Environmental signal acquisition and analysis system and method for improving radar electronic countermeasure performance |
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