CN102723977A - Shortwave eight-channel adaptive array signal processor based on CPCI (Compact Peripheral Component Interconnect) bus - Google Patents
Shortwave eight-channel adaptive array signal processor based on CPCI (Compact Peripheral Component Interconnect) bus Download PDFInfo
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Abstract
The invention provides a shortwave eight-channel adaptive array signal processor based on a CPCI (Compact Peripheral Component Interconnect) bus. The shortwave eight-channel adaptive array signal processor comprises eight A/D (Analog-Digital) chips, two down-conversion chips, an FPGA (Field Programmable Gate Array) chip, a serial configuration element, a CPCI bus and a DSP (Digital Signal Processor) chip. According to the shortwave eight-channel adaptive array signal processor based on the CPCI bus, the adaptive array processing of eight-channel shortwave signals can be realized, and the gain of entire reception of the shortwave signals is increased; and meanwhile, the data transmission and information exchange are carried out by adopting a CPCI bus interface, thus the data transmission speed is high, the slots are standard, digital signals are difficultly disturbed, and the requirements on radiation of the bus are further reduced.
Description
Technical field
The invention belongs to electronic circuit design field, and particularly relevant for a kind of shortwave eight channel adaptive array signal processors based on cpci bus.
Background technology
Short wave communication owing to the time become reasons such as decline, multipath, the phenomenon of communication efficiency difference appears in regular meeting; And the gain through adopting adaptive array can improve the short-wave reception signal.Adaptive array processing technique is mainly used on the mobile communication before; Can make main beam aim at the subscriber signal arrival direction; Secondary lobe or zero falls into and aims at the interference signal arrival direction simultaneously; Thereby bring maximum gain to useful signal, reduce multi-path influence effectively, reach purpose interference signal deletion or inhibition.Along with appearing on the market of high-speed dsp and fpga chip; The operational capability of digital signal processing module is more and more stronger; Make digital signal processing module can receive process multi-channel short-wave reception signal apace,, realize that the adaptive array of short-wave reception signal is handled signal in real time optimization analysis and weighting.Cpci bus has extreme high reliability, impact resistance and vibration resistance property simultaneously, can support more slot.
Summary of the invention
The object of the invention is to provide a kind of shortwave eight channel adaptive array signal processors based on cpci bus that can receive short-wave signal, the realization hf adaptive ARRAY PROCESSING of eight passages and have higher short-wave reception gain and antijamming capability.
For reaching above-mentioned purpose, the present invention proposes a kind of shortwave eight channel adaptive array signal processors based on cpci bus, comprising: 8 A/D chips, 2 down-conversion chips, fpga chip, series arrangement element, cpci bus and dsp chips.Wherein, 8 A/D chips are imported 8 short out ripple intermediate-freuqncy signals respectively, and above-mentioned 8 short out ripple intermediate-freuqncy signals are sampled, and obtain 8 way word signals; 2 down-conversion chips connect four in above-mentioned 8 A/D chips respectively, and every down-conversion chip carries out down-converted to 4 tunnel in the above-mentioned 8 way word signals; Fpga chip connects above-mentioned 2 down-conversion chips, and said fpga chip comprises internal logic control and Filtering Processing is carried out in the output of above-mentioned 2 down-conversion chips; The series arrangement element connects above-mentioned fpga chip, and is used to store the program of fpga chip; Dsp chip connects cpci bus and above-mentioned fpga chip, and from cpci bus input external control order, thereby self-adaptive processing is carried out in the output of said fpga chip, dsp chip returns state information to cpci bus simultaneously.
Inner logic control comprises control A/D chip and down-conversion chip etc.Further, among the present invention, the model of dsp chip is TMS320C6455, and fpga chip adopts Cyclone II FPGA, and the model of A/D chip is AD9244, and the model of down-conversion chip is HSP50216, and the model of series arrangement element is the EPCS16 chip.
The external control order of cpci bus comprises orders such as changing frequency, the mode that changes jobs.These orders are to be sent by the main control module on the cpci bus.Thereby self-adaptive processing is carried out in the output to said fpga chip, and dsp chip is with state information simultaneously; State information comprises in proper working order or fault message etc., these information is returned to main control module through cpci bus help understanding operating state and fault location and passback and give cpci bus.
The output signal of this processor is exactly the baseband digital signal that demodulation produces, and is seen off by cpci bus again.
In sum; This processor can be realized the adaptive array processing of octuple short-wave signal; Improve the gain of whole short-wave reception signal; Adopt the cpci bus interface to carry out transfer of data and information exchange simultaneously, not only data transmission bauds is fast but also the slot standard, thereby digital signal is difficult for being disturbed having reduced the requirement to total beta radiation.
Description of drawings
Fig. 1 is the theory diagram based on the shortwave eight channel adaptive array signal processors of cpci bus of the embodiment of the invention.
Fig. 2 is based on the self-adaptive processing flow process of the shortwave eight channel adaptive array signal processors of cpci bus among Fig. 1.
Embodiment
In order more to understand technology contents of the present invention, special act specific embodiment also cooperates appended graphic explanation following.
Fig. 1 is the theory diagram based on the shortwave eight channel adaptive array signal processors of cpci bus of the embodiment of the invention.As shown in Figure 1, comprise based on the shortwave eight channel adaptive array signal processors of cpci bus: 8 A/D chips, 2 down-conversion chips, fpga chip, series arrangement element, cpci bus and dsp chips.
Wherein, 8 A/D chips are imported 8 short out ripple intermediate-freuqncy signals respectively, and above-mentioned 8 short out ripple intermediate-freuqncy signals are sampled, and obtain 8 way word signals; 2 down-conversion chips connect four in above-mentioned 8 A/D chips respectively, and every down-conversion chip carries out down-converted to 4 tunnel in the above-mentioned 8 way word signals; Fpga chip connects above-mentioned 2 down-conversion chips, and said fpga chip comprises internal logic control and Filtering Processing is carried out in the output of above-mentioned 2 down-conversion chips; The series arrangement element connects above-mentioned fpga chip, and is used to store the program of fpga chip; Dsp chip connects cpci bus and above-mentioned fpga chip, and from cpci bus input external control order, thereby self-adaptive processing is carried out in the output of said fpga chip, dsp chip returns state information to cpci bus simultaneously.
Further, in the present embodiment, we adopt TMS320C6455 to process the dsp chip in the device, and this chip fast operation, memory source enrich, have the encoding and decoding coprocessor, have the master/slave pattern interface of 32bit/33MHz PCI simultaneously.FPGA adopts the Cyclone II FPGA of altera corp, fast operation, and support the high-speed-differential data.A/D selects 8 AD9244 for use, selects 2 down-conversion chip HSP50216 for use, uses fpga chip to do logic control and handles, and dsp chip reads in the external control order through cpci bus, and dsp chip returns state information to cpci bus again simultaneously.
8 AD9244 sample to 8 short out ripple signals respectively; Give 2 HSP50216 chips respectively with the digital signal of sampling and do the Digital Down Convert processing; Give fpga chip then and make Filtering Processing; Fpga chip is realized the internal logic control of this processor simultaneously, gives dsp chip by the 8 way word signals of FPGA after with Filtering Processing at last, realizes self-adaptive processing by dsp chip.
Wherein, the FPGA procedure stores is in the EPCS16 chip, and the DSP program is through the cpci bus load operating, and the FPGA handling procedure uses Quartus II compiling to generate, and the DSP program is used the CCS translation and compiling environment, and the self-adaptive processing sketch map is as shown in Figure 2.Obtain 8 roadbed band digital signals after 8 tunnel intermediate-freuqncy signals process A/D conversion, utilize baseband digital signal treatment technology identification subscriber signal arrival direction.Simultaneously this 8 road signal is carried out weighted, linear combination obtains a signal value output, is shown below:
Wherein the signal of each passage A/D conversion output is one tunnel complex signal, weight coefficient (k=1 ..., 8) also be plural number, then the data that obtain after this value weighted are carried out demodulation process, and these data are delivered in the cpci bus.In order to guarantee that each baseband signal has and identical phase place of antenna input and amplitude relation, can replenish the channel correcting means.Through above processing, can guarantee to form the spatial orientation wave beam at user's direction of arrival.
Fig. 2 is the signal processing sketch map among the present invention, and DSP accomplishes the dotted portion among Fig. 2.
In sum; This processor can be realized the adaptive array processing of octuple short-wave signal; Improve the gain of whole short-wave reception signal; Adopt the cpci bus interface to carry out transfer of data and information exchange simultaneously, not only data transmission bauds is fast but also the slot standard, thereby digital signal is difficult for being disturbed having reduced the requirement to total beta radiation.
Though the present invention discloses as above with preferred embodiment, so it is not in order to limit the present invention.Have common knowledge the knowledgeable in the technical field under the present invention, do not breaking away from the spirit and scope of the present invention, when doing various changes and retouching.Therefore, protection scope of the present invention is as the criterion when looking claims person of defining.
Claims (2)
1. the shortwave eight channel adaptive array signal processors based on cpci bus is characterized in that, comprising:
8 A/D chips are imported 8 short out ripple intermediate-freuqncy signals respectively, and above-mentioned 8 short out ripple intermediate-freuqncy signals are sampled, and obtain 8 way word signals;
2 down-conversion chips connect four in above-mentioned 8 A/D chips respectively, and every down-conversion chip carries out down-converted to 4 tunnel in the above-mentioned 8 way word signals;
Fpga chip connects above-mentioned 2 down-conversion chips, and said fpga chip comprises internal logic control
And Filtering Processing is carried out in the output to above-mentioned 2 down-conversion chips;
The series arrangement element connects above-mentioned fpga chip, and is used to store the program of fpga chip;
Cpci bus; And dsp chip; Connect cpci bus and above-mentioned fpga chip; And from cpci bus input external control order, the external control order of cpci bus comprise change frequently, the mode of changing jobs orders, these orders are to be sent by the main control module on the cpci bus; Thereby self-adaptive processing is carried out in the output to said fpga chip, and dsp chip is with state information simultaneously; State information comprises in proper working order or fault message, these information is returned to main control module through cpci bus help understanding operating state and fault location and passback to cpci bus.
2. the shortwave eight channel adaptive array signal processors based on cpci bus according to claim 1; It is characterized in that; Wherein the model of dsp chip is TMS320C6455, and fpga chip adopts Cyclone II FPGA, and the model of A/D chip is AD9244; The model of down-conversion chip is HSP50216, and the model of series arrangement element is the EPCS16 chip.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103067058A (en) * | 2012-12-25 | 2013-04-24 | 熊猫电子集团有限公司 | Short wave receiving and sending integration digital signal processing module based on delayed diversity |
| CN103067059A (en) * | 2012-12-25 | 2013-04-24 | 熊猫电子集团有限公司 | Short wave receiving and sending communication channel process device based on delayed diversity and compact peripheral component interconnect (CPCI) bus |
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| CN102053240A (en) * | 2010-10-26 | 2011-05-11 | 北京理工大学 | Reconnaissance receiving processor for synthetic aperture radar signal |
| CN102420584A (en) * | 2011-12-28 | 2012-04-18 | 熊猫电子集团有限公司 | Shortwave adaptive array processor based on compact peripheral component interconnect (CPCI) bus |
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| CN101998110A (en) * | 2009-08-31 | 2011-03-30 | 北京维盛网域科技有限公司 | Opened-type display control and command equipment |
| CN102053240A (en) * | 2010-10-26 | 2011-05-11 | 北京理工大学 | Reconnaissance receiving processor for synthetic aperture radar signal |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103067058A (en) * | 2012-12-25 | 2013-04-24 | 熊猫电子集团有限公司 | Short wave receiving and sending integration digital signal processing module based on delayed diversity |
| CN103067059A (en) * | 2012-12-25 | 2013-04-24 | 熊猫电子集团有限公司 | Short wave receiving and sending communication channel process device based on delayed diversity and compact peripheral component interconnect (CPCI) bus |
| CN103067059B (en) * | 2012-12-25 | 2015-07-08 | 熊猫电子集团有限公司 | Short wave receiving and sending communication channel process device based on delayed diversity and compact peripheral component interconnect (CPCI) bus |
| CN103067058B (en) * | 2012-12-25 | 2015-09-09 | 熊猫电子集团有限公司 | Based on the shortwave transmitting-receiving integrated Digital Signal processing module of delay diversity |
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