CN103869317A - Synthetic aperture radar real-time signal processing device - Google Patents

Synthetic aperture radar real-time signal processing device Download PDF

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CN103869317A
CN103869317A CN201410132449.3A CN201410132449A CN103869317A CN 103869317 A CN103869317 A CN 103869317A CN 201410132449 A CN201410132449 A CN 201410132449A CN 103869317 A CN103869317 A CN 103869317A
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node
processing
module
control node
aperture radar
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CN103869317B (en
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陶青长
雷磊
梁志恒
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Tsinghua University
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S13/00—Systems using the reflection or reradiation of radio waves, e.g. radar systems; Analogous systems using reflection or reradiation of waves whose nature or wavelength is irrelevant or unspecified
    • G01S13/88—Radar or analogous systems specially adapted for specific applications
    • G01S13/89—Radar or analogous systems specially adapted for specific applications for mapping or imaging
    • G01S13/90—Radar or analogous systems specially adapted for specific applications for mapping or imaging using synthetic aperture techniques, e.g. synthetic aperture radar [SAR] techniques
    • G01S13/9004—SAR image acquisition techniques
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S13/00—Systems using the reflection or reradiation of radio waves, e.g. radar systems; Analogous systems using reflection or reradiation of waves whose nature or wavelength is irrelevant or unspecified
    • G01S13/88—Radar or analogous systems specially adapted for specific applications
    • G01S13/89—Radar or analogous systems specially adapted for specific applications for mapping or imaging
    • G01S13/90—Radar or analogous systems specially adapted for specific applications for mapping or imaging using synthetic aperture techniques, e.g. synthetic aperture radar [SAR] techniques
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
    • G01S7/02—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00

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  • Engineering & Computer Science (AREA)
  • Remote Sensing (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • General Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Logic Circuits (AREA)

Abstract

The invention provides a synthetic aperture radar real-time signal processing device which comprises a plurality of transposition cache nodes, at least one processing node, a control node, a clock module, a plurality of power modules, a reset module and a watchdog module. Each processing node is connected with two transposition cache nodes, and the processing nodes are used for processing radar signals. The control node is connected with the at least one processing node and used for achieving control and state monitor on the at least one processing node. The clock module is used for providing a multi-channel clock for the at least one processing node and the control node. The power modules are used for providing a plurality of power supplies for the synthetic aperture radar real-time signal processing device. The reset module is used for controlling the at least one processing node and the control node to be reset. The watchdog module is used for monitoring the work state of the control node and the work state of the at least one processing state. The device has the advantages of being large in cache quantity, high in real-time performance and high in computing capacity.

Description

Synthetic-aperture radar real time signal processing device
Technical field
The present invention relates to Radar Signal Processing Technology field, relate in particular to a kind of synthetic-aperture radar real time signal processing device.
Background technology
Synthetic Aperture Radar Technique, through development for many years, has been tending towards ripe.Because it has round-the-clock, round-the-clock, remote, broad observation band etc., make it to have a wide range of applications in the field such as Aeronautics and Astronautics, national defence.SAR signal processing algorithm complexity, computing are intensive, require Radar Signal Processing System to possess powerful processing power and data transmission capabilities at a high speed.Most radar signal processes that board buffer memory is little, real-time is poor, arithmetic capability is low in real time, is difficult to meet the real time signal processing requirement of synthetic-aperture radar.
Summary of the invention
The present invention is intended to solve at least to a certain extent one of technical matters in correlation technique.
For this reason, first object of the present invention is to propose the synthetic-aperture radar real time signal processing device that a kind of buffer memory ability is large, arithmetic capability is strong, real-time.
To achieve these goals, in embodiments of the invention, propose a kind of synthetic-aperture radar real time signal processing device, comprising: multiple transposition cache nodes; At least one processing node, each described processing node is connected with two described transposition cache nodes, for the treatment of real-time radar signal; Control node, described control node is connected with described at least one processing node, for realizing control and the condition monitoring to described at least one processing node; Clock module, is used to described at least one processing node and described control node that multipath clock is provided; Multiple power modules, are used to described synthetic-aperture radar real time signal processing device that multiple power sources is provided; Reseting module, resets for controlling described at least one processing node and described control node; And watchdog module, for monitoring the duty of described control node and described at least one processing node.
According to synthetic-aperture radar real time signal processing device of the present invention, be provided with multiple transposition cache nodes, improve the buffer memory of synthetic-aperture radar real time signal processing device, adopted control node, reseting module and watchdog module to improve the real-time of this device processing signals simultaneously.
In some instances, described control node has communication module, and described communication module is for interconnected with outside.
In some instances, described at least one processing node adopts FPGA to realize.
In some instances, described control node adopts FPGA to realize.
In some instances, described clock module is also selected for the multiple clock sources that outside inputed to described synthetic-aperture radar real time signal processing device.
The aspect that the present invention is additional and advantage in the following description part provide, and part will become obviously from the following description, or recognize by practice of the present invention.
Accompanying drawing explanation
Fig. 1 is the structured flowchart of synthetic-aperture radar real time signal processing device according to an embodiment of the invention;
Fig. 2 is the hardware structure diagram of the synthetic-aperture radar real time signal processing device of one embodiment of the invention;
Fig. 3 is the endocorpuscular topology diagram of single transposition cache node of one embodiment of the invention; With
Fig. 4 is DDR3SDRAM circuit impedance design drawing in one embodiment of the invention;
Fig. 5 is the clock module design diagram of one embodiment of the invention;
Fig. 6 is the reseting module circuit theory diagrams of one embodiment of the invention; With
Fig. 7 is the watchdog module circuit design block diagram of one embodiment of the invention.
Embodiment
Describe embodiments of the invention below in detail, the example of described embodiment is shown in the drawings, and wherein same or similar label represents same or similar element or has the element of identical or similar functions from start to finish.Be exemplary below by the embodiment being described with reference to the drawings, be intended to for explaining the present invention, and can not be interpreted as limitation of the present invention.
Fig. 1 is the structured flowchart of synthetic-aperture radar real time signal processing device according to an embodiment of the invention.In embodiments of the invention, propose a kind of synthetic-aperture radar real time signal processing device, having comprised: multiple transposition cache nodes 100, at least one processing node 200, control node 300, clock module 400, multiple power module 500, reseting module 600 and watchdog module 700.
Wherein, at least one processing node 200, each processing node is connected with two transposition cache nodes 100, for the treatment of radar signal.Control node 300, be connected with at least one processing node 200, for realizing control and the condition monitoring at least one processing node 200.Clock module 400, being used at least one processing node 200 and controlling node 300 provides multipath clock.Multiple power modules 500, are used to synthetic-aperture radar real time signal processing device that multiple power sources is provided.Reseting module 600, resets for controlling at least one processing node 200 and controlling node 300.Watchdog module 700, for monitoring the duty of controlling node 300 and at least one processing node 200.
Particularly, at least one processing node 200 and control node 300 all adopt FPGA to realize, and have improved the arithmetic capability of device of the present invention.Control node 300 and also possess communication module, this module, for interconnected with outside, has been improved the interconnected characteristic of this device.
Further, in a specific embodiment of the present invention, adopt four transposition cache nodes, two processing nodes, control node, clock module, power module, reseting module and a watchdog module to form synthetic-aperture radar real time signal processing device.The communication protocol of this device support comprises LINK, Aurora, gigabit Ethernet, PCIE, PCI etc., and structure type is CPCI standard 6U template.
In the hardware structure diagram of the synthetic-aperture radar real time signal processing device of one embodiment of the invention as shown in Figure 2, comprise:
(1) 4 transposition cache node, each transposition cache node capacity is 4GB, the DDR3SDRAM particle that comprises 16 2Gb capacity, model is MT41J256M8DA.The endocorpuscular topological structure of single transposition cache node as shown in Figure 3.In Fig. 3,16 memory grains are divided into 4 submodules, 4 particles of each submodule.4 submodules are shared a set of address bus and control bus, and every 2 submodules are shared 1 sets of data bus.Distinguish the access to different submodules by different chip selection signals, realize storage depth expansion.Data line, by the parallel data bit width that forms 32bit of 4 particles, is monopolized separately in each submodule inside, and shared address bus and control bus are realized storage width expansion.According to the relevant regulations in JEDEC standard, the single-ended trace width of DDR3SDRAM is 4mil, and characteristic impedance is 60ohm, tolerance limit 10%.According to above requirement, stack-design as shown in Figure 4.
(2) 2 processing nodes adopt Virtex6 high-performance FPGA to realize, and model is XC6VLX240T-1FF1759, and every FPGA comprises 768 DSP48E, 832 18Kb Block RAM, 37680 slices, 720 self-defined IO.On each processing node, connect 2 DDRII-SRAM, model is K7I643682M, and capacity is 72Mb, the highest support 330MHz clock rate, and every read-write speed can reach 2.4GB/s, and this chip is for data cache.In addition, also connect a slice SDR-SRAM on each processing node, model is IS61NVP25636A, capacity is 9Mb, the highest support 250MHz clock, every read-write speed can reach 1GB/s, and this chip is as code and the data-carrier store of the soft core of the inner MicroBlaze of processing node.Each processing node connects two transposition cache nodes, and each capacity is 4GB, and readwrite bandwidth is 3.2GB/s continuously, and discrete readwrite bandwidth is 1.6GB/s.Between two processing nodes, use full duplex LINK agreement to connect, high speed transmission data rate can reach 4.8GBps.Processing node and this device are connected with external device (ED) interconnected by LINK and 4x Aurora, wherein LINK transmission data rate can reach 4.8GBps, and Aurora data transmission rate can reach 20Gbps.
(3) controlling node is a slice Virtex5 Series FPGA, and model is XC5VLX110T-1FF1156, comprises 64 DSP48E, 296 18Kb Block RAM, 17280 slices, 680 self-defined IO.Control node and connect 2 NOR type flash, total volume is 128MB, can store 5 cover configuration files.Control contact and connect a slice DDR2SDRAM, model is MT47H256M8HG, and capacity is 2Gb, the highest support 333MHz clock rate, and this chip is for controlling code and the data-carrier store of the soft core of intra-node MicroBlaze.Control node and connect processing node by 1x Aurora, thereby realize control and condition monitoring to processing node.Control node and support the pci bus of 32bit/66MHz to be connected with outside, support Gen11x PCIE simultaneously.In addition, control node and also there is communication module, support that gigabit Ethernet is interconnected.
(4) clock module, this module provides reference data for controlling node and 2 processing nodes.For a processing node, connect 2 transposition cache nodes and need 2 local clocks, connect 2 DDRII-SRAM and need 2 local clocks, connect LINK and need 2 local clocks, amount to and need altogether 6 local clocks.Simultaneously in order to meet the system requirements of clock homology, clock system needs multiple clock sources that can input to this device to outside to select.Compatibility and the extendability of considering design, the input source of clock has 3, is respectively the independent crystal oscillator in two clocks and the plate of CPCI input.Clock System Design principle as shown in Figure 5.In an embodiment of the present invention, the clock chip of 1:5 is selected the MAX9387 of MAXIM company, and the clock chip of 1:8 is selected the LMK01010 of National Semiconductor.
(5) power module, need to provide the power supply of 0.9V, 1V, 1.2V, 1.8V, 2.5V, 3V, seven kinds of level of 3.3V altogether.In an embodiment of the present invention, 1V, 1.8V, 2.5V power supply are selected the LTM4616 power supply chip of LINEAR company.0.9V power supply is selected the TPS5110 power supply chip of TI company.3.3V, 1.2V power supply are selected the TPS74401 power supply chip of TI company.3.0V power supply is selected the LT1763cs8 power supply chip of LINEAR company.Power Management Design is as table 1 mistake! Do not find Reference source.Shown in.
The list of table 1 power module
Figure BDA0000486384110000041
(6) resetting system has designed altogether 7 reset source, as shown in table 2, and these reset source are by connecting together and be input in reset chip with door, and reset chip is realized the reset to controlling node and processing node, and reset chip adopts MAX6708.
Table 2 reset source design lists
Reset source Explanation
FPGA_Config_done The configuration settling signal of processing node
FPGA_RESET Control node reset signal able to programme
POWER_GOOD_1V8 VCC_1V8 voltage stabilization signal
POWER_GOOD_VCCINT1V2 VCCINT1P2 voltage stabilization signal
POWER_GOOD_VCCINT1V0 VCCINT1P0 voltage stabilization signal
Reset_J3 The reset signal of sending into from J3
Hand-reset Hand switch resets
According to the above-mentioned demand analysis to reseting module circuit, the reset signal of MAX708 output three FPGA that reset respectively, the design of reseting module circuit is as shown in Figure 6.
(7) whether watchdog module, normally work in order to monitor processing node, and can reload program in the time that work is undesired, also designed in an embodiment of the present invention watchdog circuit.Control the house dog of node as processing node, monitor two processing nodes and whether normally work.In the time that two processing nodes can not be exported lasting pulse to control node, control node reset or reload two processing nodes.Whether can by outside watchdog chip be detected normally worked, can not export lasting pulse to watchdog chip when controlling node if controlling node itself, watchdog chip triggers control node and reloads program.The design of watchdog module circuit as shown in Figure 7.
According to synthetic-aperture radar real time signal processing device of the present invention, be provided with multiple transposition cache nodes, improve the buffer memory of synthetic-aperture radar real time signal processing device.Communication module support gigabit Ethernet and the external unit of the control node of this device are interconnected, adopt reseting module and watchdog module to improve the real-time of this device processing signals simultaneously.In addition, multiple modules of this device adopt FPGA to realize, and have improved the arithmetic capability of synthetic-aperture radar real time signal processing device of the present invention.
In the description of this instructions, the description of reference term " embodiment ", " some embodiment ", " example ", " concrete example " or " some examples " etc. means to be contained at least one embodiment of the present invention or example in conjunction with specific features, structure, material or the feature of this embodiment or example description.In this manual, to the schematic statement of above-mentioned term not must for be identical embodiment or example.And, specific features, structure, material or the feature of description can one or more embodiment in office or example in suitable mode combination.In addition,, not conflicting in the situation that, those skilled in the art can carry out combination and combination by the feature of the different embodiment that describe in this instructions or example and different embodiment or example.
Although illustrated and described embodiments of the invention above, be understandable that, above-described embodiment is exemplary, can not be interpreted as limitation of the present invention, and those of ordinary skill in the art can change above-described embodiment within the scope of the invention, modification, replacement and modification.

Claims (5)

1. a synthetic-aperture radar real time signal processing device, is characterized in that, comprising:
Multiple transposition cache nodes;
At least one processing node, each described processing node is connected with two described transposition cache nodes, for the treatment of radar signal;
Control node, described control node is connected with described at least one processing node, for realizing control and the condition monitoring to described at least one processing node;
Clock module, is used to described at least one processing node and described control node that multipath clock is provided;
Multiple power modules, are used to described synthetic-aperture radar real time signal processing device that multiple power sources is provided;
Reseting module, resets for controlling described at least one processing node and described control node; And
Watchdog module, for monitoring the duty of described control node and described at least one processing node.
2. device according to claim 1, is characterized in that, described control node has communication module, and described communication module is for interconnected with outside.
3. device according to claim 1, is characterized in that, described at least one processing node adopts FPGA to realize.
4. device according to claim 1, is characterized in that, described control node adopts FPGA to realize.
5. device according to claim 1, is characterized in that, described clock module is also selected for the multiple clock sources that outside inputed to described synthetic-aperture radar real time signal processing device.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104459669A (en) * 2014-12-10 2015-03-25 珠海纳睿达科技有限公司 Radar reflection signal processing device and method

Citations (4)

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Publication number Priority date Publication date Assignee Title
CN1877360A (en) * 2005-06-10 2006-12-13 中国科学院电子学研究所 Real-time image processing transpose memory in synthetic aperture radar
CN102053240A (en) * 2010-10-26 2011-05-11 北京理工大学 Reconnaissance receiving processor for synthetic aperture radar signal
CN103048644A (en) * 2012-12-19 2013-04-17 电子科技大学 Matrix transposing method of SAR (synthetic aperture radar) imaging system and transposing device
CN203480022U (en) * 2013-05-16 2014-03-12 中国电子科技集团公司第二十七研究所 Super-high speed general radar signal processing board

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1877360A (en) * 2005-06-10 2006-12-13 中国科学院电子学研究所 Real-time image processing transpose memory in synthetic aperture radar
CN102053240A (en) * 2010-10-26 2011-05-11 北京理工大学 Reconnaissance receiving processor for synthetic aperture radar signal
CN103048644A (en) * 2012-12-19 2013-04-17 电子科技大学 Matrix transposing method of SAR (synthetic aperture radar) imaging system and transposing device
CN203480022U (en) * 2013-05-16 2014-03-12 中国电子科技集团公司第二十七研究所 Super-high speed general radar signal processing board

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104459669A (en) * 2014-12-10 2015-03-25 珠海纳睿达科技有限公司 Radar reflection signal processing device and method
CN104459669B (en) * 2014-12-10 2016-09-21 珠海纳睿达科技有限公司 Radar appearance processing means and processing method thereof

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