CN102005196B - Shift register with low power loss - Google Patents

Shift register with low power loss Download PDF

Info

Publication number
CN102005196B
CN102005196B CN201010528620.4A CN201010528620A CN102005196B CN 102005196 B CN102005196 B CN 102005196B CN 201010528620 A CN201010528620 A CN 201010528620A CN 102005196 B CN102005196 B CN 102005196B
Authority
CN
China
Prior art keywords
electrically coupled
grid
drain electrode
transistor
level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201010528620.4A
Other languages
Chinese (zh)
Other versions
CN102005196A (en
Inventor
杨欲忠
陈勇志
林致颖
徐国华
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AU Optronics Corp
Original Assignee
AU Optronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by AU Optronics Corp filed Critical AU Optronics Corp
Publication of CN102005196A publication Critical patent/CN102005196A/en
Application granted granted Critical
Publication of CN102005196B publication Critical patent/CN102005196B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Shift Register Type Memory (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Liquid Crystal (AREA)

Abstract

The invention relates to a shift register with low power loss, comprising many levels. In one embodiment, each level comprises a first output end, a second output end, a pull-up circuit electrically coupled between one node and the second output end, a pull-up control circuit electrically coupled with the node, a pull-down control circuit electrically coupled between the node and the first output end and a control circuit electrically coupled between the node and the first output end.

Description

The shift register of tool low-power consumption
Technical field
The present invention relates to a kind of shift register, particularly relevant a kind of multistage shift register with mutual serial connection.Every one-level is all used thin film transistor (TFT), and it is driven with a direct current (DC) voltage signal, and then reduces dynamic power dissipation and improve the fiduciary level of shift register in operation.
Background technology
One liquid crystal display (LCD) comprises a panel of LCD and pixel cell, and wherein panel of LCD is formed by liquid crystal cells, and each pixel cell has with its corresponding liquid crystal cells and is associated.Pixel cell sequentially is configured to form a matrix, and it has gate line on column direction, and has data line on line direction.The LCD panel is driven by one drive circuit, yet driving circuit comprises a gate drivers and a data driver.Gate drivers produces a plurality of signals (sweep signal), and sequentially puts on the gate line, and then a startup pixel cell that is listed as regularly.Data driver produces a plurality of source signal (data-signal), for example: continuous sampling signal of video signal, sequentially put on the data line, and together with the signal that puts on the gate line, come the liquid crystal cells on the calibrating crystal display pannel, controlling its light penetration rate, thereby show image is on LCD.
In this driving circuit, a shift register is used in the gate drivers, the driving grid line sequentially to produce a plurality of signals.Yet in order to reduce cost, its correlation technique research and development expand and invariably are devoted to, and shift register and gate drivers are integrated in the panel of LCD.For instance, a method wherein is with shift register and gate drivers, makes to be formed on the glass baseplate of panel of LCD, in other words, is grid array (gate on array; GOA) configuration, and use amorphous silicon (a-Si) thin film transistor (TFT) (TFTs).
In order effectively to drive the gate line on the panel of LCD, amorphous silicon film transistor (a-SiTFTs) usually design to have large scale (channel width), wherein be because of the carrier mobility of amorphous silicon material quite low.Yet when the size of amorphous silicon film transistor heals when large, the parasitic capacitance value utmost point of amorphous silicon film transistor is also higher, and this will cause the power attenuation of the data line on the panel of LCD to rise significantly.
Therefore, up to now, those skilled in the art invariably poor its strive to find solution, to improve above-mentioned problem crux.
Summary of the invention
An aspect of the present invention relates to a kind of shift register.In one embodiment, shift register comprises multistage, { S n, n=1,2 ..., N, N are a positive integer.Every one-level comprises one first output terminal, in order to export a signal, one second output terminal, carry signal (Stage Carry Signal), a pull-up circuit in order to export one-level, be electrically coupled between a node and the second output terminal, draw control circuit on one, be electrically coupled to node, a pull-down circuit, be electrically coupled between node and the first output terminal, a drop-down control circuit, be electrically coupled between node and the pull-down circuit and a control circuit, be electrically coupled between node and the first output terminal.Control circuit comprises a transistor, and it has a grid, is electrically coupled to node, one source pole, in order to receive a direct current voltage signal and a drain electrode, is electrically coupled to the first output terminal.S nDraw control circuit to be electrically coupled to especially node and S on the level N-1The second output terminal of level, and S wherein nThe pull-down circuit of level is electrically coupled to S especially N+1The second output terminal of level.
In one embodiment, pull-up circuit comprises a transistor, and it has a grid, is electrically coupled to node, one source pole, in order to receive a plurality of control signals one of them, { HCj}, j=1,2, ..., M, M are a positive integer and a drain electrode, are electrically coupled to the second output terminal.Pull-up circuit can more comprise an electric capacity, is electrically coupled between transistorized grid and the drain electrode.
In one embodiment, draw control circuit to comprise a first transistor and a transistor seconds on.The first transistor has a grid and is electrically coupled to S N-1The second output terminal of level carries signal in order to receiver stage therefrom, and drain electrode then is electrically coupled to the input node.Transistor seconds has a grid, is electrically coupled to S N-1Node, the one source pole of level, { HCj} one of them and a drain electrode are electrically coupled to the grid of the first transistor in order to receive a plurality of control signals.
In one embodiment, pull-down control circuit comprises one first pull-down control circuit and one second pull-down control circuit.Each first pull-down control circuit and the second pull-down control circuit all have a first transistor, a transistor seconds, one the 3rd transistor and one the 4th transistor.The first transistor has a grid, in order to receive one first clock signal or one second clock signal, one source pole, is electrically coupled to grid and a drain electrode.Transistor seconds has a grid, is electrically coupled to drain electrode and a drain electrode that node, one source pole are electrically coupled to the first transistor, in order to receive a supply voltage.The 3rd transistor has a grid, is electrically coupled to drain electrode, the one source pole of the first transistor, is electrically coupled to source electrode and a drain electrode of the first transistor, is electrically coupled to a node.The 4th transistor has a grid, is electrically coupled to node, one source pole, is electrically coupled to the 3rd transistorized drain electrode and a drain electrode, in order to receive a supply voltage.
In one embodiment, pull-down circuit comprises one first pull-down circuit and one second pull-down circuit.The first pull-down circuit comprises a first transistor and a transistor seconds.The first transistor has a grid, is electrically coupled to node, the one source pole of the first pull-down control circuit, is electrically coupled to node and a drain electrode, is electrically coupled to the first output terminal.Transistor seconds has a grid, is electrically coupled to node, the one source pole of the first pull-down control circuit, is electrically coupled to the first output terminal and a drain electrode, in order to receive supply voltage.The second pull-down circuit comprises a first transistor, a transistor seconds, one the 3rd transistor and one the 4th transistor.The first transistor has a grid, is electrically coupled to node, the one source pole of the second pull-down control circuit, is electrically coupled to node and a drain electrode, is electrically coupled to the first output terminal.Transistor seconds has a grid, is electrically coupled to node, the one source pole of the second pull-down control circuit, is electrically coupled to the first output terminal and a drain electrode, in order to receive supply voltage.The 3rd transistor has a grid, is electrically coupled to S N+1The second output terminal, the one source pole of level are electrically coupled to node and a drain electrode, in order to receive supply voltage.The 4th transistor has a grid, is electrically coupled to S N+1The second output terminal, the one source pole of level are electrically coupled to the first output terminal and a drain electrode, in order to receive supply voltage.
Another aspect of the present invention relates to a kind of liquid crystal display (LCD), and it comprises a liquid crystal panel, a plurality of sweep trace and a gate drivers.Liquid crystal panel has a plurality of pixels, sequentially is configured to form a matrix.Sweep trace then is sequentially to dispose along a column direction, and wherein per two adjacent sweep traces define a pixel column.One gate drivers drives pixel in order to produce a plurality of signals.Gate drivers comprises a shift register, and it has the multistage { S of mutual serial connection n, n=1,2 ..., N, N are a positive integer.
Every one-level comprises draws control circuit, a pull-down circuit and a control circuit on one first output terminal, the pull-up circuit.The corresponding gate line of the first output terminal electric property coupling, and then export a signal.The second output terminal carries signal in order to export one-level.Pull-up circuit is electrically coupled between a node and the second output terminal.On draw control circuit to be electrically coupled to node.Pull-down circuit is electrically coupled between node and the first output terminal.Pull-down control circuit is electrically coupled between node and the pull-down circuit.Control circuit is electrically coupled between node and the first output terminal.Control circuit comprises a transistor, and it has a grid, is electrically coupled to node, one source pole, in order to receive a dc voltage signal and a drain electrode, is electrically coupled to the first output terminal.S nDraw control circuit to be electrically coupled to especially node and S on the level N-1The second output terminal of level, and S wherein nThe pull-down circuit of level is electrically coupled to S especially N+1The second output terminal of level.
In one embodiment, pull-up circuit comprises a transistor, and it has a grid, is electrically coupled to node, one source pole, in order to receive a plurality of control signals one of them, { HCj}, j=1,2, ..., M, M are a positive integer and a drain electrode, are electrically coupled to the second output terminal.Pull-up circuit can more comprise an electric capacity, and it is electrically coupled to grid and drain electrode in the transistor.
In one embodiment, draw control circuit to comprise a first transistor and a transistor seconds on.The first transistor has a grid, one source pole, is electrically coupled to S N-1The second output terminal of level carries signal and a drain electrode with receiver stage, is electrically coupled to the input node.Transistor seconds has a grid, is electrically coupled to S N-1Node, the one source pole of level, { HCj} one of them and a drain electrode are electrically coupled to the grid of the first transistor in order to receive multi-control signal.
In one embodiment, pull-down control circuit comprises one first pull-down control circuit and one second pull-down control circuit.Each first pull-down control circuit and the second pull-down control circuit have a first transistor, a transistor seconds, one the 3rd transistor and one the 4th transistor.The first transistor has a grid, in order to receive one first clock signal or one second clock signal, one source pole, is electrically coupled to grid, a drain electrode.Transistor seconds has a grid, is electrically coupled to node, one source pole, is electrically coupled to drain electrode and a drain electrode of the first transistor, in order to receive a supply voltage.The 3rd transistor has a grid, is electrically coupled to drain electrode, the one source pole of the first transistor, is electrically coupled to source electrode and a drain electrode of the first transistor, is electrically coupled to a node.The 4th transistor has a grid, is electrically coupled to node, one source pole, is electrically coupled to the 3rd transistorized drain electrode and a drain electrode, in order to receive a supply voltage.
In one embodiment, pull-down circuit comprises one first pull-down circuit and one second pull-down circuit.
The first pull-down circuit comprises a first transistor and a transistor seconds.The first transistor has a grid, is electrically coupled to node, the one source pole of the first pull-down control circuit, is electrically coupled to node and a drain electrode, is electrically coupled to the first output terminal.Transistor seconds has a grid, is electrically coupled to node, the one source pole of the first pull-down control circuit, is electrically coupled to the first output terminal and a drain electrode, in order to receive supply voltage.
The second pull-down circuit comprises a first transistor, a transistor seconds, one the 3rd transistor and one the 4th transistor.The first transistor has a grid, is electrically coupled to node, the one source pole of the second pull-down control circuit, is electrically coupled to node and a drain electrode, is electrically coupled to the first output terminal.Transistor seconds has a grid, is electrically coupled to node, the one source pole of the second pull-down control circuit, is electrically coupled to the first output terminal and a drain electrode, in order to receive supply voltage.The 3rd transistor has a grid, is electrically coupled to S N+1The second output terminal, the one source pole of level are electrically coupled to node and a drain electrode, in order to receive supply voltage.The 4th transistor has a grid, is electrically coupled to S N+1The second output terminal, the one source pole of level are electrically coupled to the first output terminal and a drain electrode, in order to receive supply voltage.
In one embodiment, this liquid crystal panel of liquid crystal panel, sweep trace and gate drivers all is formed on the glass baseplate, causes these levels { S nBe disposed at least one side of liquid crystal panel.
Shift register disclosed by the invention and the LCD that uses it, because shift register has the multistage of mutual serial connection, every one-level is all used a thin film transistor (TFT), and it is driven by d. c. voltage signal, and then the reduction dynamic power dissipation, and promote its operation in fiduciary level.
Yet, as for each aspect and other aspects of the invention described above, will by following each embodiment accompanying drawing corresponding with it, be described in detail it.
Description of drawings
For above and other purpose of the present invention, feature, advantage and embodiment can be become apparent, appended the description of the drawings is as follows:
Fig. 1 is the calcspar of a kind of shift register of illustrating according to one embodiment of the invention;
Fig. 2 is for illustrating the S of shift register among Fig. 1 nOne circuit diagram of level;
Fig. 3 is the signal waveforms that illustrates shift register among Fig. 1;
Fig. 4 is the analog output signal that illustrates shift register among Fig. 1;
Fig. 5 is a RA test result that illustrates the output signal of shift register among Fig. 1.
Wherein, Reference numeral
100: 141: the first pull-down control circuits of shift register
142: the second pull-down control circuits of 111: the first output terminals
Output terminal 150 in 112: the second: pull-down control circuit
120: 151: the first pull-down circuits of pull-up circuit
130: on draw 152: the second pull-down circuits of control circuit
140: pull-down circuit
Embodiment
In order to make narration of the present invention more detailed and complete, to allow those skilled in the art with clear difference and the variation wherein of energy, can be with reference to the embodiment of the following stated.In the following passage, be described in detail for various embodiments of the present invention.In the appended accompanying drawing, identical number represents same or analogous element.In addition, in embodiment and claim, unless be particularly limited to some extent for article in the interior literary composition, " one " can make a general reference single one or more with " being somebody's turn to do ".And, in embodiment and claim, unless be particularly limited to some extent herein, otherwise mentioned " ... in " also comprise " and ... inner " with " and ... on " connotation.
In order to make narration of the present invention more detailed and complete, can be with reference to appended accompanying drawing and the various embodiment of the following stated, identical number represents same or analogous element in the accompanying drawing.On the other hand, well-known element and step are not described among the embodiment, with the restriction of avoiding causing the present invention unnecessary.
Generally being often referred to the error of numerical value or scope in 20 percent about " pact " used herein, " approximately " or " roughly about ", is preferably in ten Percent, more preferably then is in percentage five.Wen Zhongruo is without offering some clarification on, and its mentioned numerical value is all regarded as approximate value, namely such as " pact ", " approximately " or " roughly about " represented error or scope.
Yet, as for " comprising " used herein, " comprising ", " having " and similar vocabulary, all regard as open conjunction.For example, " comprise " and do not get rid of request item not element, composition or the step of record in the combination that represents element, composition or step.
Following will for embodiments of the present invention and corresponding Fig. 1-Fig. 5, the detailed description in detail.According to purpose of the present invention, more specifically and widely to set forth a kind of aspect of the present invention, be about a kind of shift register and a kind of liquid crystal display LCD that uses it.
Please refer to Fig. 1, it illustrates according to the calcspar of a kind of shift register 100 of one embodiment of the invention (or GOA topological design).Shift register 100 comprises the multistage { S of mutual serial connection n, n=1,2 ..., N, N are a positive integer.These multistage { S nDispose/be formed at a glass baseplate
On the (not shown).Among the embodiment as shown in Figure 1, only illustrate the level Four S in the shift register 100 n, S N+1, S N+2, and S N+3
Every one-level S nHave one first output terminal 111 in order to exporting a signal G (n), and one second output terminal 112 carries (stage carry) signal ST (n) in order to export one-level.Every one-level S nThe first output terminal be electrically coupled to a corresponding gate line of a panel of LCD (not shown), thereby so as to the output gate drive signal.Every one-level S nAlso have a plurality of input ends, in order to receive corresponding one or more control/clock signal, for example: LC1, LC2, HC1, HC2, HC3, HC4 and a supply voltage VSS.
In addition, every one-level S nHave and draw control circuit 130, a pull-up circuit 120, a drop-down control circuit 150, a pull-down circuit 140 and a control circuit on one, wherein control circuit comprises a transistor T 22, is formed on the glass baseplate adjacent one another are.Every one-level S nIn, pull-up circuit 120 is electrically coupled between a node Q (n) and the second output terminal 112.On draw control circuit 130 to be electrically coupled to pull-up circuit 120 through node Q (n).Pull-down circuit 140 is electrically coupled between node Q (n) and the first output terminal 111.Pull-down control circuit 150 is electrically coupled between node Q (n) and the pull-down circuit 140.Pull-up circuit 120 is to receive a corresponding control/clock signal HC1, HC2, HC3 or HC4.For instance, S nLevel, S N+1Level, S N+2Level and S N+3Pull-up circuit 120 in the level receives respectively control/clock signal HC1, HC2, HC3 and HC4, as shown in Figure 1.Pull-down control circuit 150 is also in order to receive control/clock signal LC1 and LC2.Transistor T 22 has a grid, is electrically coupled to node Q (n), one source pole, in order to receive a direct current voltage signal VGH and a drain electrode, is electrically coupled to the first output terminal 111.Moreover, S n Draw control circuit 130 also to be electrically coupled to prime S on the level N-1The node Q (n-1) of level and the second output terminal 112.S nThe pull-down circuit 140 of level is electrically coupled to next stage S N+1The second output terminal 112 of level.
Please refer to Fig. 2, it illustrates a kind of according to an embodiment of the invention S of shift register 100 nThe circuit diagram of level.Pull-up circuit 120 comprises a transistor T 21, and it has a grid, is electrically coupled to node Q (n), one source pole, in order to reception control signal HC2 and a drain electrode, is electrically coupled to the second output terminal 112.Pull-up circuit 120 more comprises a capacitor C, is electrically coupled between the grid and drain electrode of transistor T 21.
On draw control circuit 130 to comprise a first transistor T11 and a transistor seconds T12.The first transistor T11 has a grid, one source pole, is electrically coupled to S N-1The second output terminal 112 of level, thus signal ST (n-1) and a drain electrode carried in order to receiver stage, be electrically coupled to node Q (n).Transistor seconds T12 has a grid, is electrically coupled to S N-1Node Q (n-1), the one source pole of level in order to reception control signal HC1 and a drain electrode, are electrically coupled to the grid among the first transistor T11.
Pull-down control circuit 140 comprises one first pull-down control circuit 141 and one second pull-down control circuit 142.
The first pull-down control circuit 141 has a first transistor T51, a transistor seconds T52, one the 3rd transistor T 53 and one the 4th transistor T 54.The first transistor T51 has a grid, in order to receive the first clock signal LC1, one source pole, is electrically coupled to grid and a drain electrode.Transistor seconds T52 has a grid, is electrically coupled to this node Q (n), one source pole, is electrically coupled to drain electrode and the drain electrode of the first transistor T51, in order to receive supply voltage VSS.One the 3rd transistor T 53 has a grid, is electrically coupled to drain electrode, the one source pole of the first transistor T51, is electrically coupled to source electrode and the drain electrode of the first transistor T51, electric property coupling one node P (n).The 4th transistor T 54 has a grid, is electrically coupled to node Q (n), one source pole, is electrically coupled to drain electrode and a drain electrode of the 3rd transistor T 53, in order to receive a supply voltage VSS.
The second pull-down control circuit 142 has a first transistor T61, a transistor seconds T62, one the 3rd transistor T 63 and one the 4th transistor T 64.The first transistor T61 has a grid, in order to receive the second clock signal LC2, one source pole, is electrically coupled to grid and a drain electrode.Transistor seconds T62 has a grid, is electrically coupled to drain electrode and a drain electrode that node Q (n), one source pole are electrically coupled to the first transistor T61, in order to receive supply voltage VSS.The 3rd transistor T 63 has a grid, is electrically coupled to drain electrode, the one source pole of the first transistor T61, is electrically coupled to source electrode and the drain electrode of the first transistor T61, is electrically coupled to a node K (n).The 4th transistor T 64 has a grid, is electrically coupled to node Q (n), one source pole, is electrically coupled to drain electrode and a drain electrode of the 3rd transistor T 63, in order to receive supply voltage VSS.
Pull-down circuit 150 comprises one first pull-down circuit 151 and one second pull-down circuit 152.
The first pull-down circuit 151 comprises a first transistor T31 and a transistor seconds T32.The first transistor T31 has a grid, is electrically coupled to node P (n), the one source pole of the first pull-down control circuit, is electrically coupled to node Q (n) and a drain electrode, is electrically coupled to the first output terminal.Transistor seconds T32 has a grid, is electrically coupled to node P (n), the one source pole of the first pull-down control circuit, is electrically coupled to the first output terminal and a drain electrode, in order to receive supply voltage VSS.
The second pull-down circuit 152 comprises a first transistor T41, a transistor seconds T42, one the 3rd transistor T 43 and one the 4th transistor T 44.The first transistor T41 has a grid, is electrically coupled to node K (n), the one source pole of the second pull-down control circuit, is electrically coupled to node Q (n) and a drain electrode, is electrically coupled to the first output terminal.Transistor seconds T42 has a grid, is electrically coupled to node K (n), the one source pole of the second pull-down control circuit, is electrically coupled to the first output terminal and a drain electrode, in order to receive supply voltage VSS.The 3rd transistor T 43 has a grid, is electrically coupled to S N+1The second output terminal, the one source pole of level, electric property coupling node Q (n) and a drain electrode are in order to receive supply voltage VSS.The 4th transistor T 44 has a grid, is electrically coupled to S N+1The second output terminal, the one source pole of level, electric property coupling the first output terminal and a drain electrode are in order to receive supply voltage VSS.
Transistor T 22 has a grid, be electrically coupled to node Q (n), one source pole, be electrically coupled to a DC power supply, to receive a high voltage DC signal VGH and a drain electrode, be electrically coupled to the first output terminal 111, exporting a signal to a corresponding gate line, and then the driving pixel relevant with gate line.
Above-mentioned disclosed transistor comprises transistor T 22, be thin film transistor (TFT) (TFTs), yet better selection is to adopt amorphous silicon film transistor (a-Si TFTs).
In the configuration structure of Fig. 1 and the shown shift register of Fig. 2, draw the load current potential of adjacent level more than transistor T 21 usefulness of pull-up circuit 120.So the channel width of transistor T 21 can be designed to very narrow, so that its dynamic power dissipation may diminish to is very little.In addition, the input signal of transistor T 22 is a direct current voltage signal, thereby will can not produce dynamic power dissipation.Therefore, whole power attenuations of shift register are able to essence and effectively reduce.
Fig. 3 illustrates shift register among Fig. 1 and Fig. 2 in operation, its second level S 2The oscillogram of signal (n=2).
In period P1, first order S 1The voltage (current potential) of node Q (1) be positioned at a high voltage potential, and transistor T 12 corresponding unlatchings.So the grid of transistor T 11 is namely charged by the first clock signal HC1, thereby opens it.Thus, node Q (2) is then by prime S adjacent one another are 1Level carry a signal ST (1) and charged.When the voltage on the node Q (2) charging (drawing high) during to a noble potential, transistor T 21 is just opened with 22 grades of transistor Ts thereupon.Yet, in period P1, because the second clock signal HC2 is coupled to, be positioned at the drain electrode of the transistor T 21 of low voltage potential VGL, so there is not level to carry the output of signal ST (2).Flow to source electrode with regard to transistor T 22, one power supplys from the drain electrode of transistor T22, so that sweep trace G (2) is charged, wherein drain electrode is electrically connected to the high voltage potential of d. c. voltage signal VGH, and source electrode is electric property coupling the first output terminal then.
In period P2, when the first clock signal HC1 was positioned at low voltage potential, 11 of transistor Ts were closed and node Q (2) is positioned at a quick condition.Yet transistor T 21 is kept unlatching with transistor T 22.When the second clock signal HC2 was positioned at high voltage potential VGH, a level year signal ST (2) exported by transistor T 21.Level is carried signal ST (2) and is coupled in capacitor C, alternately node Q (2) is charged to a higher voltage potential.So the waveform on the node Q (2) has the rising of two steps.When the voltage on the node Q (2) is positioned at more high voltage potential, from transistor T22 flow out/electric current of output is namely greater than the electric current in period P1.Yet, higher at the output voltage of the first output terminal G (2).
In period P3, when the 3rd clock signal HC3 is positioned at high voltage potential VGH, the output of the level year signal ST (3) of next stage S3 is arranged then, wherein by transistor T 43, the voltage potential on the pull-down node Q (2) is to reference voltage VSS.Yet it is by transistor T 44 that level is carried signal ST (3), and the voltage potential on the drop-down sweep trace G (2) is to reference voltage VSS.Under this situation, node P (2)/K (2) is playing the part of the quite moving role who wants in the voltage potential of regulation and control node Q (2)/G (2).In general, the voltage potential of node Q (2)/G (2) is by transistor T 31/T32/T41/T42, to regulate and control to reference voltage VSS.Yet when the output terminal of this grade had the contribution of node Q (2), node P (2)/K (2) was pulled down to reference voltage VSS, makes and closes circuit for regulating and controlling.
More than disclosed running principle also be applicable in the shift register other the level.
Fig. 4 illustrates in the shift register of Fig. 1 and Fig. 2, and it is respectively by S nLevel, S N+1Level and S N+2Output signal G (n), the G (n+1) that level produces and the analog waveform figure of G (n+2).
Fig. 5 illustrates the shift register position and is about 100 ℃ in temperature and went through its S 72 hours nThe one RA test result of output signal of level, wherein G (n) and G ' (n) correspond respectively to primary output signal and a grade output signal after the RA test.According to the present invention, its shown level output signal G ' after the RA test (n), almost identical in the primary output signal G (n) after RA test, this expresses this shift register and shows quite reliable and stablely, and the power of its loss is quite low.
Another sample attitude of the present invention is relevant for a kind of LCD that uses above-mentioned disclosed shift register.In one embodiment, LCD comprises a liquid crystal panel, a plurality of sweep trace and a gate drivers.Liquid crystal panel has a plurality of pixels, and sequentially is configured to form a matrix.A plurality of sweep traces sequentially dispose along a column direction, and wherein per two adjacent sweep traces define a pixel column.Gate drivers in order to produce a plurality of signals, drives pixel.Gate drivers comprises shift register, and it has the multistage { S of mutual serial connection n.Every one-level S nOutput terminal be electrically coupled to corresponding gate line, and then to export a signal G (n).
In one embodiment, liquid crystal panel, sweep trace and gate drivers all are formed on the glass baseplate, so so that multistage { S nBe disposed at a side of liquid crystal panel, or be disposed at the dual-side on the liquid crystal panel.Therefore one, namely simplify the GOA design architecture and reduced the manufacturing cost of panel of LCD.Moreover, more can reduce its power attenuation and promote the fiduciary level of panel of LCD in operation.
Generally speaking, the present invention LCD of disclosing a kind of shift register and using it.Shift register has the multistage of mutual serial connection.Every one-level is all used a thin film transistor (TFT), and it is driven by d. c. voltage signal, and then reduces dynamic power dissipation, and promotes the fiduciary level in its operation.More than for the narration of the typical embodiment of the present invention only for accompanying drawing and character narrate the present invention, be not in order thoroughly to describe the present invention or the present invention to be limited to disclosed form fully.Content by above-mentioned institute teaching can inspire various corrections and improvement.
Embodiment selected and that describe is in order to explain the application of principle of the present invention and its reality, impel whereby other can utilize the present invention and its various embodiments those skilled in the art, and think deeply by various concrete embodiments and suitable specific use pattern.Keeping the present invention and do not having in the situation departing from its spirit and scope, those skilled in the art can find other embodiment.Based on this, scope of the present invention is defined by claim hereinafter, but not is defined by the narration of above-mentioned illustrative embodiment.
Certainly; the present invention also can have other various embodiments; in the situation that does not deviate from spirit of the present invention and essence thereof; those of ordinary skill in the art work as can make according to the present invention various corresponding changes and distortion, but these corresponding changes and distortion all should belong to the protection domain of the appended claim of the present invention.

Claims (11)

1. a shift register is characterized in that, comprise mutual serial connection multistage Sn}, n=1,2 ..., N, N are a positive integer, wherein every one-level Sn comprises:
One first output terminal is in order to export a signal G (n);
One second output terminal carries signal ST (n) in order to export one-level;
One pull-up circuit is electrically coupled between this second output terminal of a node Q (n) and Sn level;
Draw control circuit on one, be electrically coupled to this node Q (n);
One pull-down circuit is electrically coupled between this first output terminal of this node Q (n) and Sn level; And
One control circuit, be electrically coupled between this first output terminal of this node Q (n) and Sn level, wherein this control circuit comprises a transistor T 22, it has a grid, one source pole and a drain electrode, and wherein this grid is electrically coupled to this node Q (n), this source electrode is in order to receive a direct current (DC) voltage signal, and this drain electrode is electrically coupled to this first output terminal of Sn level;
Wherein said Sm level in multistage should on draw control circuit more to be electrically coupled to this second output terminal of this node Q (m-1) and this Sm-1 level, and wherein this pull-down circuit of this Sm level more is electrically coupled to this second output terminal of this Sm+1 level, m=2 ..., N-1; Wherein
Being somebody's turn to do of Sm level draws control circuit to comprise a transistor T 11 and a transistor T 12; This transistor T 11 has one source pole, is electrically coupled to this second output terminal of Sm-1 level, thereby carries signal ST (m-1), a drain electrode in order to receiver stage, is electrically coupled to node Q (m) and a grid; This transistor T 12 has a grid, is electrically coupled to node Q (m-1), the one source pole of Sm-1 level, in order to receive multi-control signal { HCj } one of them, j=1,2 ..., M, M is a positive integer, and a drain electrode, is electrically coupled to the grid of this transistor T 11.
2. shift register according to claim 1, it is characterized in that, the pull-up circuit of Sm level comprises a transistor T 21 and has a grid, one source pole and a drain electrode, wherein this grid is electrically coupled to this node Q (m), this source electrode in order to receive multi-control signal { HCj } one of them, this drain electrode is electrically coupled to this second output terminal of Sm level.
3. shift register according to claim 2 is characterized in that, this pull-up circuit of Sm level more comprises an electric capacity, is electrically coupled between this grid and this drain electrode in the transistor T 21 of this pull-up circuit of Sm level.
4. shift register according to claim 2 is characterized in that, this pull-down circuit of Sm level comprises a drop-down control circuit, and it has one first pull-down control circuit and one second pull-down control circuit, and wherein this first pull-down control circuit comprises:
One transistor T 51 has a grid, one source pole and a drain electrode, and wherein this grid is in order to receive one first clock signal (LC1), and this source electrode is electrically coupled to this grid;
One transistor T 52 has a grid, one source pole and a drain electrode, and wherein this grid is electrically coupled to this node Q (m), and this source electrode is electrically coupled to this drain electrode of this transistor T 51, and this drain electrode is in order to receive a supply voltage;
One transistor T 53 has a grid, one source pole and a drain electrode, and wherein this grid is electrically coupled to this drain electrode of this transistor T 51, and this source electrode is electrically coupled to this source electrode of this transistor T 51, and this drain electrode is electrically coupled to a node P (m); And
One transistor T 54 has a grid, one source pole and a drain electrode, and wherein this grid is electrically coupled to this node Q (m), this drain electrode of this this transistor T 53 of source electrode electric property coupling, and this drain electrode is in order to receive a supply voltage;
Wherein the second pull-down control circuit comprises:
One transistor T 61 has a grid, one source pole and a drain electrode, and wherein this grid is in order to receive one second clock signal (LC2), and this source electrode is electrically coupled to this grid;
One transistor T 62 has a grid, one source pole and a drain electrode, and wherein this grid is electrically coupled to this node Q (m), and this source electrode is electrically coupled to this drain electrode of this transistor T 61, and this drain electrode is in order to receive a supply voltage;
One transistor T 63 has a grid, one source pole and a drain electrode, and wherein this grid is electrically coupled to this drain electrode of this transistor T 61, and this source electrode is electrically coupled to this source electrode of this transistor T 61, and this drain electrode is electrically coupled to a node K (m); And
One transistor T 64 has a grid, one source pole and a drain electrode, and wherein this grid is electrically coupled to this node Q (m), this drain electrode of this this transistor T 63 of source electrode electric property coupling, and this drain electrode is in order to receive a supply voltage.
5. shift register according to claim 4 is characterized in that, this pull-down circuit of Sm level more comprises one first pull-down circuit and one second pull-down circuit, and wherein this first pull-down circuit comprises:
One transistor T 31 has a grid, one source pole and a drain electrode, wherein this grid is electrically coupled to this node P (m) of this first pull-down control circuit, this source electrode is electrically coupled to this node Q (m), and this drain electrode is electrically coupled to this first output terminal of Sm level; And
One transistor T 32 has a grid, one source pole and a drain electrode, and wherein this grid is electrically coupled to this node P (m) of this first pull-down control circuit, and this source electrode is electrically coupled to this first output terminal of Sm level, and this drain electrode is in order to receive this supply voltage; And
Wherein this second pull-down circuit comprises:
One transistor T 41 has a grid, one source pole and a drain electrode, wherein this grid is electrically coupled to this node K (m) of this second pull-down control circuit, this source electrode is electrically coupled to this node Q (m), this first output terminal of this drain electrode electric property coupling Sm level; And
One transistor T 42 has a grid, one source pole and a drain electrode, and wherein this grid is electrically coupled to this node K (m) of this second pull-down control circuit, and this source electrode is electrically coupled to this first output terminal of Sm level, and this drain electrode is in order to receive this supply voltage;
One transistor T 43 has a grid, one source pole and a drain electrode, and wherein this grid is electrically coupled to this second output terminal of this Sm+1 level, and this source electrode is electrically coupled to this node Q (m), and this drain electrode is in order to receive this supply voltage; And
One transistor T 44 has a grid, one source pole and a drain electrode, and wherein this grid is electrically coupled to this second output terminal of this Sm+1 level, and this source electrode is electrically coupled to this first output terminal of Sm level, and this drain electrode is in order to receive this supply voltage.
6. a liquid crystal display (LCD) is characterized in that, comprises:
One liquid crystal panel has a plurality of pixels, sequentially is configured to form a matrix;
A plurality of sweep traces sequentially dispose along a column direction, and wherein per two adjacent sweep traces define a pixel column; And
One gate drivers in order to produce a plurality of signals, drives these pixels, wherein this gate drivers comprises a shift register, multistage { Sn}, n=1,2 with mutual serial connection, N, N are a positive integer, and wherein every one-level Sn comprises: one first output terminal, electric property coupling one corresponding gate line is in order to export a signal G (n); One second output terminal carries signal ST (n) in order to export one-level; One pull-up circuit is electrically coupled between this second output terminal of a node Q (n) and Sn level; Draw control circuit on one, be electrically coupled to this node Q (n); One pull-down circuit is electrically coupled between this first output terminal of this node Q (n) and Sn level; An and control circuit, be electrically coupled between this first output terminal of this node Q (n) and Sn level, wherein this control circuit comprises a transistor T 22, have a grid, one source pole and a drain electrode, and wherein this grid is electrically coupled to this node Q (n), this source electrode is in order to receive a direct current (DC) voltage signal, and this drain electrode is electrically coupled to this first output terminal of Sn level;
Wherein said Sm level in multistage should on draw control circuit to be electrically coupled to especially this second output terminal of this node Q (m-1) and this Sm-1 level, and wherein this pull-down circuit of this Sm level is electrically coupled to this second output terminal of this Sm+1 level especially, m=2 ..., N-1; Wherein
Being somebody's turn to do of Sm level draws control circuit to comprise a transistor T 11 and a transistor T 12; This transistor T 11 has one source pole, is electrically coupled to this second output terminal of Sm-1 level, thereby carries signal ST (m-1), a drain electrode in order to receiver stage, is electrically coupled to node Q (m) and a grid; This transistor T 12 has a grid, is electrically coupled to node Q (m-1), the one source pole of Sm-1 level, in order to receive multi-control signal { HCj } one of them, j=1,2 ..., M, M is a positive integer, and a drain electrode, is electrically coupled to the grid of this transistor T 11.
7. liquid crystal display according to claim 6, it is characterized in that, this pull-up circuit of Sm level comprises a transistor T 21, have a grid, one source pole and a drain electrode, wherein this grid is electrically coupled to this node Q (m), this source electrode in order to receive multi-control signal { HCj } one of them, this drain electrode is electrically coupled to this second output terminal of Sm level.
8. liquid crystal display according to claim 7 is characterized in that, this pull-up circuit of Sm level more comprises an electric capacity, is electrically coupled between this grid and this drain electrode in the transistor T 21 of this pull-up circuit of Sm level.
9. liquid crystal display according to claim 7 is characterized in that, this pull-down circuit of Sm level comprises a drop-down control circuit, and it comprises one first pull-down control circuit and one second pull-down control circuit, and wherein this first pull-down control circuit comprises:
One transistor T 51 has a grid, one source pole and a drain electrode, and wherein this grid is in order to receive one first clock signal (LC1), and this source electrode is electrically coupled to this grid;
One transistor T 52 has a grid, one source pole and a drain electrode, and wherein this grid is electrically coupled to this node Q (m), and this source electrode is electrically coupled to this drain electrode of this transistor T 51, and this drain electrode is in order to receive a supply voltage;
One transistor T 53 has a grid, one source pole and a drain electrode, and wherein this grid is electrically coupled to this drain electrode of this transistor T 51, this source electrode of this this transistor T 51 of source electrode electric property coupling, and this drain electrode is electrically coupled to a node P (m); And
One transistor T 54 has a grid, one source pole and a drain electrode, and wherein this grid is electrically coupled to this node Q (m), and this source electrode is electrically coupled to this drain electrode of this transistor T 53, and this drain electrode is in order to receive a supply voltage;
This second pull-down control circuit comprises:
One transistor T 61 has a grid, one source pole and a drain electrode, and wherein this grid is in order to receive one second clock signal (LC2), and this source electrode is electrically coupled to this grid;
One transistor T 62 has a grid, one source pole and a drain electrode, and wherein this grid is electrically coupled to this node Q (m), and this source electrode is electrically coupled to this drain electrode of this transistor T 61, and this drain electrode is in order to receive a supply voltage;
One transistor T 63 has a grid, one source pole and a drain electrode, and wherein this grid is electrically coupled to this drain electrode of this transistor T 61, this source electrode of this this transistor T 61 of source electrode electric property coupling, and this drain electrode is electrically coupled to a node K (m); And
One transistor T 64 has a grid, one source pole and a drain electrode, and wherein this grid is electrically coupled to this node Q (m), and this source electrode is electrically coupled to this drain electrode of this transistor T 63, and this drain electrode is in order to receive a supply voltage.
10. liquid crystal display according to claim 9 is characterized in that, this pull-down circuit of Sm level more comprises one first pull-down circuit and one second pull-down circuit, and wherein this first pull-down circuit comprises:
One transistor T 31 has a grid, one source pole and a drain electrode, wherein this grid is electrically coupled to this node P (m) of this first pull-down control circuit, this source electrode is electrically coupled to this node Q (m), this first output terminal of this drain electrode electric property coupling Sm level; And
One transistor T 32 has a grid, one source pole and a drain electrode, and wherein this grid is electrically coupled to this node P (m) of this first pull-down control circuit, and this source electrode is electrically coupled to this first output terminal of Sm level, and this drain electrode is in order to receive this supply voltage; And
Wherein this second pull-down circuit comprises:
One transistor T 41 has a grid, one source pole and a drain electrode, this node K (m) of this this second pull-down control circuit of grid electric property coupling wherein, this source electrode is electrically coupled to this node Q (m), and this drain electrode is electrically coupled to this first output terminal of Sm level; And
One transistor T 42 has a grid, one source pole and a drain electrode, and wherein this grid is electrically coupled to this node K (m) of this second pull-down control circuit, and this source electrode is electrically coupled to this first output terminal of Sm level, and this drain electrode is in order to receive this supply voltage;
One transistor T 43 has a grid, one source pole and a drain electrode, and wherein this grid is electrically coupled to this second output terminal of this Sm+1 level, and this source electrode is electrically coupled to this node Q (m), and this drain electrode is in order to receive this supply voltage; And
One transistor T 44 has a grid, one source pole and a drain electrode, and wherein this grid is electrically coupled to this second output terminal of this Sm+1 level, and this source electrode is electrically coupled to this first output terminal of Sm level, and this drain electrode is in order to receive this supply voltage.
11. liquid crystal display according to claim 6 is characterized in that, liquid crystal panel, these sweep traces and this gate drivers all are formed on the glass baseplate so that these levels Sn} be positioned at this liquid crystal panel at least on one side.
CN201010528620.4A 2010-03-24 2010-10-26 Shift register with low power loss Active CN102005196B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/730,576 US8537094B2 (en) 2010-03-24 2010-03-24 Shift register with low power consumption and liquid crystal display having the same
US12/730,576 2010-03-24

Publications (2)

Publication Number Publication Date
CN102005196A CN102005196A (en) 2011-04-06
CN102005196B true CN102005196B (en) 2013-01-30

Family

ID=42829945

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201010528620.4A Active CN102005196B (en) 2010-03-24 2010-10-26 Shift register with low power loss

Country Status (5)

Country Link
US (1) US8537094B2 (en)
EP (1) EP2369594B1 (en)
JP (1) JP5258913B2 (en)
CN (1) CN102005196B (en)
TW (1) TWI422156B (en)

Families Citing this family (62)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102034553B (en) * 2009-09-25 2013-07-24 北京京东方光电科技有限公司 Shift register and gate line driving device thereof
TWI413972B (en) * 2010-09-01 2013-11-01 Au Optronics Corp Shift register circuit
TWI451383B (en) * 2011-12-05 2014-09-01 Au Optronics Corp Flat panel display, shift register and method of controlling the shift register
TWI455094B (en) * 2012-06-07 2014-10-01 Au Optronics Corp Gate driver of display device and operating method thereof
TWI460702B (en) * 2012-07-19 2014-11-11 Au Optronics Corp Display device and shift register thereof
TWI482136B (en) * 2012-08-21 2015-04-21 Innocom Tech Shenzhen Co Ltd Gate driver circuit structure and display thereof
TWI459368B (en) * 2012-09-14 2014-11-01 Au Optronics Corp Display apparatus and method for generating gate signal thereof
TWI511459B (en) * 2012-10-11 2015-12-01 Au Optronics Corp Gate driving circuit capable of preventing current leakage
TWI505245B (en) * 2012-10-12 2015-10-21 Au Optronics Corp Shift register
TWI571842B (en) * 2012-11-01 2017-02-21 友達光電股份有限公司 Gate scanner driving circuit and shift register thereof
TWI476774B (en) * 2012-11-02 2015-03-11 Au Optronics Corp Shift register
TWI473059B (en) * 2013-05-28 2015-02-11 Au Optronics Corp Shift register circuit
CN104123918B (en) * 2013-06-11 2016-06-29 深超光电（深圳）有限公司 Shift register and liquid crystal indicator
TWI533606B (en) * 2013-06-14 2016-05-11 友達光電股份有限公司 Shift register circuit
US9202590B2 (en) 2013-07-29 2015-12-01 Broadcom Corporation Low power shift register
TWI493522B (en) * 2013-08-16 2015-07-21 Au Optronics Corp Shift register circuit
CN103680388B (en) * 2013-12-26 2015-11-11 深圳市华星光电技术有限公司 For recoverable GOA circuit and the display device of flat pannel display
CN103745700B (en) * 2013-12-27 2015-10-07 深圳市华星光电技术有限公司 Self-repair type gate driver circuit
TWI522978B (en) * 2014-02-20 2016-02-21 友達光電股份有限公司 Inspection and repairing method of display panel
CN103985341B (en) * 2014-04-30 2016-04-20 京东方科技集团股份有限公司 A kind of shift register cell, gate driver circuit and display device
TWI486959B (en) * 2014-05-05 2015-06-01 Au Optronics Corp Shift register circuit
CN103985369B (en) * 2014-05-26 2017-02-15 深圳市华星光电技术有限公司 Array substrate row driving circuit and liquid crystal display device
CN104167191B (en) * 2014-07-04 2016-08-17 深圳市华星光电技术有限公司 Complementary type GOA circuit for flat pannel display
CN104064160B (en) * 2014-07-17 2016-06-15 深圳市华星光电技术有限公司 There is the gate driver circuit of self-compensating function
TWI541779B (en) * 2014-07-18 2016-07-11 友達光電股份有限公司 Shift register and method of driving shift register
TWI533272B (en) * 2014-09-26 2016-05-11 友達光電股份有限公司 Display device and driving method thereof
TWI523021B (en) * 2014-10-31 2016-02-21 友達光電股份有限公司 Shift register
CN104332144B (en) * 2014-11-05 2017-04-12 深圳市华星光电技术有限公司 Liquid crystal display panel and gate drive circuit thereof
KR20160055368A (en) 2014-11-07 2016-05-18 삼성디스플레이 주식회사 Display apparatus and method of driving the same
CN104376824A (en) * 2014-11-13 2015-02-25 深圳市华星光电技术有限公司 GOA circuit for liquid crystal display and liquid crystal display device
CN104376826B (en) * 2014-11-20 2017-02-01 深圳市华星光电技术有限公司 Shifting register unit, grid driving circuit and displaying device
CN104376825B (en) * 2014-11-20 2017-02-22 深圳市华星光电技术有限公司 Shifting register unit, grid driving circuit and displaying device
CN104505036B (en) * 2014-12-19 2017-04-12 深圳市华星光电技术有限公司 Gate driver circuit
TWI537916B (en) * 2014-12-24 2016-06-11 友達光電股份有限公司 Display device and repairing method thereof
CN104517577B (en) * 2014-12-30 2016-10-12 深圳市华星光电技术有限公司 Liquid crystal indicator and gate drivers thereof
CN104505048A (en) * 2014-12-31 2015-04-08 深圳市华星光电技术有限公司 Gate driver on array (GOA) circuit and liquid crystal display device
CN104575438B (en) * 2015-02-15 2017-05-03 合肥京东方光电科技有限公司 Shifting register unit, driving method of shifting register unit, grid driving circuit and display device
CN104766575B (en) * 2015-04-07 2017-10-17 深圳市华星光电技术有限公司 A kind of GOA circuits and liquid crystal display
CN104732945B (en) * 2015-04-09 2017-06-30 京东方科技集团股份有限公司 Shift register and driving method, array substrate gate drive device, display panel
US20160358566A1 (en) * 2015-06-08 2016-12-08 Boe Technology Group Co., Ltd. Shift register unit and driving method thereof, gate driving circuit and display device
CN105139825B (en) * 2015-10-20 2017-08-25 京东方科技集团股份有限公司 Shift register cell, gate drive apparatus, display device, control method
CN105528983B (en) * 2016-01-25 2018-07-17 武汉华星光电技术有限公司 Scan drive circuit and flat display apparatus with the circuit
CN105575329B (en) 2016-03-16 2017-12-01 京东方科技集团股份有限公司 Shift register and driving method, drive circuit, array base palte and display device
CN106157858B (en) * 2016-08-31 2020-02-07 深圳市华星光电技术有限公司 Test circuit of grid drive circuit of liquid crystal display panel and working method thereof
CN106409262A (en) * 2016-11-28 2017-02-15 深圳市华星光电技术有限公司 Goa driving circuit and liquid crystal display device
CN106486078B (en) * 2016-12-30 2019-05-03 深圳市华星光电技术有限公司 A kind of scan drive circuit, driving circuit and display device
WO2018163897A1 (en) * 2017-03-06 2018-09-13 シャープ株式会社 Scan signal line driving circuit and display device provided therewith
TWI616860B (en) * 2017-06-27 2018-03-01 友達光電股份有限公司 Gate driving circuit and operating method thereof
CN107146589A (en) * 2017-07-04 2017-09-08 深圳市华星光电技术有限公司 GOA circuits and liquid crystal display device
US10386663B2 (en) * 2017-08-14 2019-08-20 Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. GOA circuit and liquid crystal display device
JP2019074560A (en) * 2017-10-12 2019-05-16 シャープ株式会社 Display device
CN107633833A (en) * 2017-10-31 2018-01-26 京东方科技集团股份有限公司 Shift register cell and its driving method, gate driving circuit, display device
TWI643173B (en) * 2018-01-19 2018-12-01 友達光電股份有限公司 Gate driving apparatus
CN108053801B (en) * 2018-02-12 2021-01-29 京东方科技集团股份有限公司 Shifting register unit and driving method thereof, grid driving circuit and display device
TWI671747B (en) * 2018-11-12 2019-09-11 友達光電股份有限公司 Shift register
CN111223459B (en) 2018-11-27 2022-03-08 元太科技工业股份有限公司 Shift register and gate drive circuit
CN110335572B (en) * 2019-06-27 2021-10-01 重庆惠科金渝光电科技有限公司 Array substrate row driving circuit unit, driving circuit thereof and liquid crystal display panel
TWI706404B (en) * 2019-09-04 2020-10-01 友達光電股份有限公司 Gate driving circuit
CN111081196B (en) * 2019-12-24 2021-06-01 深圳市华星光电半导体显示技术有限公司 GOA circuit and display panel
CN111710274B (en) * 2020-06-12 2023-06-27 深圳市华星光电半导体显示技术有限公司 Clock signal judging circuit and display panel
TWI744096B (en) * 2020-11-18 2021-10-21 友達光電股份有限公司 Gate of array driving circuit
TWI749998B (en) * 2021-01-12 2021-12-11 友達光電股份有限公司 Shift register circuit and pixel driving device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200951968A (en) * 2008-06-06 2009-12-16 Au Optronics Corp Shift register
CN101661798A (en) * 2009-09-24 2010-03-03 友达光电股份有限公司 Shift register circuit and method for generating grid signals thereof

Family Cites Families (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU2003214699A1 (en) * 2002-04-08 2003-10-27 Samsung Electronics Co., Ltd. Liquid crystal display device
US6845140B2 (en) * 2002-06-15 2005-01-18 Samsung Electronics Co., Ltd. Method of driving a shift register, a shift register, a liquid crystal display device having the shift register
US7486269B2 (en) * 2003-07-09 2009-02-03 Samsung Electronics Co., Ltd. Shift register, scan driving circuit and display apparatus having the same
KR20050079718A (en) * 2004-02-06 2005-08-11 삼성전자주식회사 Shift register and display apparatus including the same
KR20070017600A (en) * 2005-08-08 2007-02-13 삼성전자주식회사 Shift Register And Display Device Having The Same
TWI316219B (en) * 2005-08-11 2009-10-21 Au Optronics Corp A three-level driving shift register
TWI320564B (en) * 2005-08-25 2010-02-11 Au Optronics Corp A shift register driving method
KR20070034800A (en) * 2005-09-26 2007-03-29 삼성전자주식회사 Shift register, scan driver for display device and display device including same
US7310402B2 (en) * 2005-10-18 2007-12-18 Au Optronics Corporation Gate line drivers for active matrix displays
TWI326445B (en) * 2006-01-16 2010-06-21 Au Optronics Corp Shift register turning on a feedback circuit according to a signal from a next stage shift register
TWI325132B (en) * 2006-02-10 2010-05-21 Au Optronics Corp Shift register capable of self feedback
KR101154338B1 (en) * 2006-02-15 2012-06-13 삼성전자주식회사 Shift register, and scan drive circuit and display device having the same
JP5128102B2 (en) * 2006-02-23 2013-01-23 三菱電機株式会社 Shift register circuit and image display apparatus including the same
TWI323869B (en) * 2006-03-14 2010-04-21 Au Optronics Corp Shift register circuit
KR100769970B1 (en) * 2006-05-30 2007-10-25 경희대학교 산학협력단 Shift register
US8174478B2 (en) * 2006-06-12 2012-05-08 Samsung Electronics Co., Ltd. Gate driving circuit and display apparatus having the same
KR101275248B1 (en) * 2006-06-12 2013-06-14 삼성디스플레이 주식회사 Gate driver circuit and display apparatus having the same
TWI322975B (en) 2006-06-23 2010-04-01 Au Optronics Corp Shift register circuit and display apparatus incorporating the same
TWI338275B (en) * 2006-08-24 2011-03-01 Au Optronics Corp Shift register with lower coupling effect and the related lcd
TWI336870B (en) * 2006-09-01 2011-02-01 Au Optronics Corp Signal-driving system and shift register unit thereof
TWI347577B (en) * 2006-09-01 2011-08-21 Au Optronics Corp Shift register with low stress
TWI345195B (en) * 2006-09-01 2011-07-11 Au Optronics Corp Control circuit for releasing residual charges
TWI349908B (en) * 2006-09-14 2011-10-01 Au Optronics Corp Shift register, shift register array circuit, and flat display apparatus
JP4990034B2 (en) * 2006-10-03 2012-08-01 三菱電機株式会社 Shift register circuit and image display apparatus including the same
KR101281498B1 (en) * 2006-10-31 2013-07-02 삼성디스플레이 주식회사 Gate driving circuit and display apparatus having the same
JP4912186B2 (en) * 2007-03-05 2012-04-11 三菱電機株式会社 Shift register circuit and image display apparatus including the same
CN101042937B (en) * 2007-04-24 2010-10-13 友达光电股份有限公司 Displacement register capable of reducing voltage bias effective voltage, control circuit and liquid crystal display
TWI337735B (en) * 2007-05-18 2011-02-21 Au Optronics Corp Liquid crystal display and shift register with individual driving node
KR101286539B1 (en) * 2008-04-15 2013-07-17 엘지디스플레이 주식회사 Shift register
TWI386904B (en) * 2008-05-12 2013-02-21 Chimei Innolux Corp Flat display
TWI398852B (en) * 2008-06-06 2013-06-11 Au Optronics Corp Shift register and shift register unit for diminishing clock coupling effect
CN101303895B (en) * 2008-06-17 2011-07-27 友达光电股份有限公司 Shift buffer
TWI379310B (en) * 2008-08-27 2012-12-11 Au Optronics Corp Shift register
KR101022092B1 (en) * 2009-01-12 2011-03-17 삼성모바일디스플레이주식회사 Shift Register and Organic Light Emitting Display Device Using the Same
US9281077B2 (en) * 2009-02-25 2016-03-08 Sharp Kabushiki Kaisha Shift register and display device
TWI400686B (en) * 2009-04-08 2013-07-01 Au Optronics Corp Shift register of lcd devices
EP2444974A4 (en) 2009-06-15 2013-04-10 Sharp Kk Shift register and display device
US20130069930A1 (en) * 2010-03-15 2013-03-21 Sharp Kabushiki Kaisha Shift register, scanning signal line drive circuit, and display device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200951968A (en) * 2008-06-06 2009-12-16 Au Optronics Corp Shift register
CN101661798A (en) * 2009-09-24 2010-03-03 友达光电股份有限公司 Shift register circuit and method for generating grid signals thereof

Also Published As

Publication number Publication date
TW201134097A (en) 2011-10-01
TWI422156B (en) 2014-01-01
CN102005196A (en) 2011-04-06
US8537094B2 (en) 2013-09-17
EP2369594A1 (en) 2011-09-28
JP2011204343A (en) 2011-10-13
US20110234577A1 (en) 2011-09-29
JP5258913B2 (en) 2013-08-07
EP2369594B1 (en) 2015-10-21

Similar Documents

Publication Publication Date Title
CN102005196B (en) Shift register with low power loss
US8754674B2 (en) Gate drive circuit and method of driving the same
US8243058B2 (en) Gate driving circuit and display device having the gate driving circuit
CN101833997B (en) Pull-down control circuit and shift register using the same
US7310402B2 (en) Gate line drivers for active matrix displays
US9666140B2 (en) Display device and method for driving same
TWI529682B (en) A scanning signal line driving circuit, a display device including the same, and a driving method of a scanning signal line
US8456409B2 (en) Gate drive circuit and display apparatus having the same
US9053677B2 (en) Gate driving circuit and display panel having the same
US20070237285A1 (en) Shift register with four phase clocks
JP6231692B2 (en) Gate drive circuit and drive method
CN101587700B (en) Liquid crystal display and method for driving same
CN107909971B (en) GOA circuit
CN106782282A (en) Shift register, gate driving circuit, display panel and driving method
CN103714792A (en) Shift register unit, gate drive circuit and display apparatus
JP2009015291A (en) Display device and driving method thereof
CN107689221B (en) GOA circuit
KR102023641B1 (en) Shift register and method for driving the same
CN102800289A (en) Shift register and drive method, gird drive device, and display device thereof
KR20100075141A (en) Gate driving circuit and display device having the gate driving circuit
US9786243B2 (en) Gate driving circuit and display apparatus including the same
US10553166B2 (en) Display apparatus and method of driving the display apparatus
US11600242B2 (en) Single-stage gate driving circuit with multiple outputs and gate driving device
KR101860732B1 (en) Gate driving circuit and display device having the same
US8547319B2 (en) Display apparatus including a gate driver that has a plurality of stages and method for driving the display apparatus

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant