CN101990282A - Method and device for improving performance of receiver - Google Patents
Method and device for improving performance of receiver Download PDFInfo
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- CN101990282A CN101990282A CN2009100560500A CN200910056050A CN101990282A CN 101990282 A CN101990282 A CN 101990282A CN 2009100560500 A CN2009100560500 A CN 2009100560500A CN 200910056050 A CN200910056050 A CN 200910056050A CN 101990282 A CN101990282 A CN 101990282A
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
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Abstract
The invention relates to the technical field of communication, and discloses a method and a device for improving performance of a receiver. The method comprises the following steps of: after a terminal sleep cycle ends, determining the receiving lead aiming at timing offset; determining the initial time for receiving data according to the receiving lead; and receiving downlink data after the initial time is up. By adopting the method and the device, the influence of the terminal clock system timing offset on the performance of the receiver can be improved, and the method and the device can be suitable for different application environments.
Description
Technical field
The present invention relates to the communication technology, be specifically related to a kind of method and device that improves receiver performance.
Background technology
Compare with traditional 2G/3G access technology, TD-LTE (Time Division-Long TermEvolution, time-division Long Term Evolution) technology has the raising of several number magnitude on data rate and bandwidth.30.72MHz basic sample frequency, other data rate of 100Mbps level, make the TD-LTE terminal must and eNodeB (evolution base station) maintenance high level of synchronization, this has just proposed more strict requirement to the timing accuracy of terminal this locality; The operating frequency of device and power consumption also significantly improve thereupon simultaneously.So the TD-LTE terminal must be supported DRX (Discontinuous Reception, discontinuous reception) sleep function in the cycle to be satisfying the power saving performance of terminal, and the DRX parameter has determined terminal to wake up when idle condition time interval of monitoring seek channel message.
As shown in Figure 1, be the clock system logic diagram of existing terminal:
The clock system of terminal is by work clock generation module 101, Clock management subsystem 102, physical layer subsystem 103, clock alignment circuit 104 and two clocks: 32KHz clock and 20MHz clock are formed, wherein, the 20MHz clock is a work clock, and the 32KHz clock is a low frequency and low power consumption clock.The operation principle of this clock system is as follows:
1. when the terminal decision enters sleep state, by the zero hour and the duration of physical layer subsystem 103 notice Clock management subsystems 102 sleeps;
2. Clock management subsystem 102 is closed the 20MHz work clock, opens the 32KHz clock simultaneously, and writes down the timing starting point deviation of these two clocks, and system enters low power consumpting state;
3. after sleep cycle finished, Clock management subsystem 102 was opened the 20MHz clock, starts clock alignment circuit 104 simultaneously;
4. clock alignment circuit 104 is calibrated work clock according to the timing offset of the sleep record zero hour, and the work clock after will calibrating is supplied with physics straton system 103;
5. physical layer subsystem 103 is provided with Tx/Rx (emission/reception) incident of radio-frequency module 101, and system enters normal operating conditions.
In the terminal sleep process, the work clock of chip is closed, and only safeguards the synchronizing signal of low-power consumption, low precision with the 32K clock.Because factors such as volume, cost, the clock devices type selecting of terminal is limited in scope, in sleep procedure, factor such as temperature, voltage can produce bigger timing offset when skew takes place, even pass through hardware calibration behind the sleep awakening, also can produce certain timing offset, synchronous error can be brought the deterioration of algorithm performance, and then influences the receiver performance of terminal.
For this reason, rule of thumb fixedly install the method that receives lead in the prior art usually.Because ofdm signal increases the data volume that receives in advance, the Cyclic Prefix (CP) of signal can be included, synchronized algorithm can identify the accurate position of signal when carrying out related calculation, and then reaches the purpose of correcting timing offset.
In realizing process of the present invention, the inventor finds that there is following problem at least in said method: fixedly install the method that receives lead and lack flexibility and adaptability, can not guarantee the performance of algorithm, because receiving being provided with usually of lead obtains according to emulation, simulation or actual measurement, therefore there is very big blindness, and can't adapts to different applied environments.
Summary of the invention
The embodiment of the invention provides a kind of method and device that improves receiver performance, improving terminal clock system timing offset to the receiver Effect on Performance, and can be applicable to different applied environments.
For this reason, the embodiment of the invention provides following technical scheme:
A kind of method that improves receiver performance comprises:
Behind the terminal sleep end cycle, determine this reception lead at timing offset;
Receive the zero-time that lead determines to receive data according to this;
Arrive the back receiving downlink data in described zero-time.
Preferably, described definite this reception lead at timing offset comprises:
After first sleep cycle finishes, according to the predetermined maximum lead T that receives
Max, this is set receives lead T
1=T
Max
After follow-up sleep cycle finishes, according to the preceding reception lead T that once determines
I-1, determine that this receives lead T
i, i represents the sleep cycle number of times.
Preferably, the described maximum lead T that receives
MaxBe to determine, specifically comprise according to the clock system performance of described terminal:
Determine the longest length of one's sleep of terminal according to maximum discontinuous receiving cycle;
Determine the maximum timing offset of described clock system hardware calibration according to the longest described length of one's sleep;
Determine the maximum lead T that receives according to described maximum timing offset
Max
Preferably, the reception lead T that once determines before the described basis
I-1, determine that this receives lead T
iComprise:
Calculate the timing offset average Δ t after descending reception link timing offset estimated value Δ t and described terminal arrive steady operation
0
Determine that according to following formula this receives lead T
i:
T
i=T
I-1-α * (T
I-1-T
0)/(1+ β * Δ t), wherein, α is a sensitive factor, 1≤α≤T
Max/ (T
Max-T
0); β is a stable factor, β=1/ Δ t
0T
0Be reception lead required under the ideal synchronisation state.
Preferably, according to the sensitiveness of terminal receiving algorithm, described T is set for timing offset
0With sensitive factor α.
Preferably, the operating state according to terminal is provided with described stable factor β.
A kind of device that improves receiver performance comprises:
The lead determining unit is used for behind the terminal sleep end cycle, determines this reception lead at timing offset;
The zero-time determining unit is used for receiving the zero-time that lead determines to receive data according to this;
The Data Receiving unit is used for arriving the back receiving downlink data in described zero-time.
Preferably, described lead determining unit comprises:
First determining unit is used for after first sleep cycle finishes, according to the predetermined maximum lead T that receives
Max, this is set receives lead T
1=T
Max
Second determining unit is used for after follow-up sleep cycle finishes, according to the preceding reception lead T that once determines
I-1, determine that this receives lead T
i, i represents the sleep cycle number of times.
Preferably, described device also comprises:
The maximum lead determining unit that receives is used for determining the maximum lead T that receives according to the clock system performance of described terminal
Max, the described maximum lead determining unit that receives comprises:
The longest length of one's sleep, determining unit was used for determining according to maximum discontinuous receiving cycle the longest length of one's sleep of terminal;
Maximum timing offset determining unit is used for determining according to the longest described length of one's sleep the maximum timing offset of described clock system hardware calibration;
The 3rd determining unit is used for determining the maximum lead T that receives according to described maximum timing offset
Max
Preferably, described second determining unit comprises:
First computation subunit is used to calculate descending reception link timing offset estimated value Δ t;
Second computation subunit is used to calculate the timing offset average Δ t after described terminal arrives steady operation
0
The 3rd computation subunit is used for determining that according to following formula this receives lead T
i:
T
i=T
I-1-α * (T
I-1-T
0)/(1+ β * Δ t), wherein, α is a sensitive factor, 1≤α≤T
Max/ (T
Max-T
0); β is a stable factor, β=1/ Δ t
0T
0Be reception lead required under the ideal synchronisation state.
Preferably, described device also comprises:
First is provided with the unit, is used for according to the sensitiveness of terminal receiving algorithm for timing offset described T being set
0With sensitive factor α.
Preferably, described device also comprises:
Second is provided with the unit, is used for according to the operating state of terminal described stable factor β being set.
The embodiment of the invention improves the method and the device of receiver performance, receive lead correction timing offset shortage flexibility and adaptive shortcoming at prior art by fixedly installing, after the each sleep cycle of terminal finishes, adjust this reception lead adaptively at timing offset, correct the timing offset that produces in the terminal sleep process, thereby improved terminal clock system timing offset effectively to the receiver Effect on Performance, had good flexibility and adaptability.
Further, adopt maximum reception lead in only receiving the first time after each sleep finishes, after follow-up sleep finishes, determine current reception lead in conjunction with the timing offset output in each receiving course, convergence fast then, computational complexity and reception lead descend thereupon fast, wake the stages such as initial stage, steady operation and optimum state up thereby can adapt to terminal sleep automatically neatly.Owing to determine adaptively to receive lead, thereby go for different applied environments, improve the terminal receiver performance.
Description of drawings
Fig. 1 is the clock system logic diagram of existing terminal;
Fig. 2 is the flow chart that the embodiment of the invention improves the method for receiver performance;
Fig. 3 determines the maximum flow chart that receives lead in the embodiment of the invention;
Fig. 4 is a kind of structural representation that the embodiment of the invention improves the device of receiver performance;
Fig. 5 is the another kind of structural representation that the embodiment of the invention improves the device of receiver performance.
Embodiment
In order to make those skilled in the art person understand the scheme of the embodiment of the invention better, the embodiment of the invention is described in further detail below in conjunction with drawings and embodiments.
The embodiment of the invention improves the method and the device of receiver performance, receive lead correction timing offset shortage flexibility and adaptive shortcoming at prior art by fixedly installing, after the each sleep cycle of terminal finishes, adjust this reception lead adaptively, correct the timing offset that produces in the terminal sleep process at timing offset.Particularly, after first sleep cycle finishes,, this is set receives lead according to the predetermined maximum lead that receives; After follow-up sleep cycle finishes,, determine that this receives lead according to the preceding reception lead of once determining.
As shown in Figure 2, be the flow chart that the embodiment of the invention improves the method for receiver performance, may further comprise the steps:
Step 201 behind the terminal sleep end cycle, is determined this reception lead at timing offset;
Step 202 receives the zero-time that lead determines to receive data according to this;
Step 203 arrives the back receiving downlink data in described zero-time.
Particularly, in above-mentioned steps 201, after first sleep cycle end, can be according to the predetermined maximum lead T that receives
Max, this is set receives lead T
1=T
Max, certainly, also can make T
1＜T
MaxAfter follow-up sleep cycle finishes, can be according to the preceding reception lead T that once determines
I-1, determine that this receives lead T
iThereby can utilize the adjustment result of down-going synchronous process, dynamically adjust the reception lead after each sleep finishes, the iterative process by limited number of time makes clock synchronization reach stable state fast.
As seen, the embodiment of the invention improves the method for receiver performance, receive lead correction timing offset shortage flexibility and adaptive shortcoming at prior art by fixedly installing, after the each sleep cycle of terminal finishes, adjust this reception lead adaptively at timing offset, correct the timing offset that produces in the terminal sleep process, thereby improved terminal clock system timing offset effectively, have good flexibility and adaptability the receiver Effect on Performance.
In embodiments of the present invention, the maximum lead T that receives
MaxDetermine and can determine by off-line analysis.As shown in Figure 3, be to determine the maximum a kind of flow chart that receives lead in the embodiment of the invention, may further comprise the steps:
Step 301 is determined the longest length of one's sleep of terminal according to maximum DRX cycle.
Described maximum DRX cycle can be determined according to the regulation of agreement, when determining the longest length of one's sleep of terminal, to consider on the one hand the report cycle demand measured, on the other hand also will be according to the characteristic of clock devices itself, should be less than or equal to maximum DRX the longest described length of one's sleep.
Step 302 is determined the maximum timing offset of described clock system hardware calibration according to the longest described length of one's sleep.
Factors such as device that the maximum timing offset of described clock system hardware calibration and the clock alignment circuit of clock system adopt and external environment condition are relevant, particularly, can determine the maximum timing offset of clock system hardware calibration according to factors such as device performance, calibration cycle, temperature deviation, voltage bias.
Such as, can determine by following test process:
Structure test environment: in the official hour section, hardware platform (being the clock system of terminal) is implemented maximum temperature deviation and maximum voltage deviation,, work clock is calibrated by the timing offset of clock alignment circuit according to the sleep record zero hour.With clock after the calibration and absolute clock contrast, obtain the maximum timing offset of clock system hardware calibration.
Step 303 is determined the maximum lead T that receives according to described maximum timing offset
Max
Particularly, can assess the receptivity deterioration degree that maximum timing offset brings according to the characteristic of terminal receiving algorithm, such as, a timing offset E artificially is set earlier
Max, in DRP data reception process, do not consider the influence of this timing offset, count this situation with respect to normal condition by receiving algorithm, the receptivity deterioration degree.Then, the reference performance deterioration degree is further extrapolated the maximum lead T that receives
Max
Certainly, the maximum lead T that receives in the embodiment of the invention
MaxDetermine to be not limited in above-mentioned flow process, can also adopt other modes to determine.
The front is mentioned, after follow-up sleep cycle finishes, and can be according to the preceding reception lead T that once determines
I-1, determine that this receives lead T
iThereby can utilize the adjustment result of down-going synchronous process, dynamically adjust the reception lead after each sleep finishes, the iterative process by limited number of time makes clock synchronization reach stable state fast.
Particularly, can determine reception lead T after follow-up sleep cycle finishes by following process
i:
(1) the timing offset average Δ t behind descending reception link timing offset estimated value Δ t of calculating and the described terminal arrival steady operation
0
Can utilize existing receiving algorithm to obtain descending reception link timing offset estimated value Δ t, and by measuring the timing offset average Δ t after described terminal arrives steady operation
0
(2) determine that according to following formula this receives lead T
i:
T
i=T
I-1-α * (T
I-1-T
0)/(1+ β * Δ t), wherein, α is a sensitive factor, 1≤α≤T
Max/ (T
Max-T
0); β is a stable factor, β=1/ Δ t
0T
0Be required reception lead under the ideal synchronisation state (being Δ t=0);
Particularly, can described T be set according to the sensitiveness of terminal receiving algorithm for timing offset
0With sensitive factor α, described stable factor β is set according to the operating state of terminal.
The embodiment of the invention improves the method for receiver performance, owing to after terminal is slept end for the first time, receive lead T based on the maximum of assessing out
MaxDetermine this reception lead, this moment, Δ t=∞ received lead T so this can be set
1=T
Max, that is to say that the method for the embodiment of the invention can be held maximum timing offset.In addition, receive the timing offset estimation because terminal can be done down link constantly, and do timing offset control on this basis, controlled target is to make Δ t=0.Receive timing offset amount T=T this moment
Max-α * (T
Max-T
0), under the situation of the limit (be α=1 o'clock), T=T
0, the target of control meets the demand of algorithm under desirable synchronous regime; Under general situation, the deviate Δ t that reception lead T estimates along with link progressively restrains.That is to say that the method for the embodiment of the invention can satisfy worst error condition, also meet the algorithm requirements of ideal synchronisation situation, and the progressively convergence along with dwindling of timing offset.Descend fast thereby make computational complexity and receive lead thereupon, adapt to the stages such as sleep awakening initial stage, steady operation and optimum state automatically neatly.According to different applied environments, can between processing complexity and convergence rate, realize optimum balance by parameter optimization.
Compare with the fixing existing method that receives lead, the method of the embodiment of the invention has the control range of clear and definite controlled target, safety and closely combines with controlling object (timing offset), control procedure is clear accurately, convergence rate is variable along with the setting of sensitive factor α, has very strong flexibility.
One of ordinary skill in the art will appreciate that all or part of step that realizes in the foregoing description method is to instruct relevant hardware to finish by program, described program can be stored in the computer read/write memory medium, described storage medium, as: ROM/RAM, magnetic disc, CD etc.
The embodiment of the invention also provides a kind of device that improves receiver performance, as shown in Figure 4, is a kind of structural representation of this device.
In this embodiment, described device comprises:
Lead determining unit 401 is used for behind the terminal sleep end cycle, determines this reception lead at timing offset;
Zero-time determining unit 402 is used for receiving the zero-time that lead determines to receive data according to this;
In the embodiment of the invention, a kind of preferred structure of described lead determining unit 401 comprises:
First determining unit 411 is used for after first sleep cycle finishes, according to the predetermined maximum lead T that receives
Max, this is set receives lead T
1=T
Max
Second determining unit 412 is used for after follow-up sleep cycle finishes, according to the preceding reception lead T that once determines
I-1, determine that this receives lead T
i, i represents the sleep cycle number of times.
The embodiment of the invention improves the device of receiver performance, receive lead correction timing offset shortage flexibility and adaptive shortcoming at prior art by fixedly installing, after the each sleep cycle of terminal finishes, adjust this reception lead adaptively at timing offset, correct the timing offset that produces in the terminal sleep process, thereby improved terminal clock system timing offset effectively to the receiver Effect on Performance, had good flexibility and adaptability.
As shown in Figure 5, be the another kind of structural representation that the embodiment of the invention improves the device of receiver performance.
With embodiment illustrated in fig. 4 different be that in this embodiment, described device also comprises: the maximum lead determining unit 404 that receives is used for determining the maximum lead T that receives according to the clock system performance of described terminal
Max
The described maximum a kind of preferred embodiment that receives lead determining unit 404 comprises:
The longest length of one's sleep, determining unit 441, were used for determining according to discontinuous receiving cycle the longest length of one's sleep of terminal;
Maximum timing offset determining unit 442 is used for determining according to the longest described length of one's sleep the maximum timing offset of described clock system hardware calibration;
The 3rd determining unit 443 is used for determining the maximum lead T that receives according to described maximum timing offset
Max
Certainly, in the embodiment of the invention, the described maximum lead determining unit 404 that receives is not limited in said structure, and other frame modes can also be arranged.
In embodiments of the present invention, a kind of preferred structure of described second determining unit 412 comprises: first computation subunit, second computation subunit and the 3rd computation subunit.Wherein:
Described first computation subunit is used to calculate descending reception link timing offset estimated value Δ t;
Described second computation subunit is used to calculate the timing offset average Δ t after described terminal arrives steady operation
0
Described the 3rd computation subunit is used for determining that according to following formula this receives lead T
i:
T
i=T
I-1-α * (T
I-1-T
0)/(1+ β * Δ t), wherein, α is a sensitive factor, 1≤α≤T
Max/ (T
Max-T
0); β is a stable factor, β=1/ Δ t
0T
0Be reception lead required under the ideal synchronisation state.
In the device of the raising receiver performance that the embodiment of the invention provides, can comprise further that also first is provided with the unit and second unit, wherein:
Described first is provided with the unit, is used for according to the sensitiveness of terminal receiving algorithm for timing offset described T being set
0With sensitive factor α.
Described second is provided with the unit, is used for according to the operating state of terminal described stable factor β being set.
The embodiment of the invention improves the device of receiver performance, owing to after terminal is slept end for the first time, receive lead T based on the maximum of assessing out
MaxDetermine this reception lead, this moment, Δ t=∞ received lead T so this can be set
1=T
Max, that is to say that the method for the embodiment of the invention can be held maximum timing offset.In addition, receive the timing offset estimation because terminal can be done down link constantly, and do timing offset control on this basis, controlled target is to make Δ t=0.Receive timing offset amount T=T this moment
Max-α * (T
Max-T
0), under the situation of the limit (be α=1 o'clock), T=T
0, the target of control meets the demand of algorithm under desirable synchronous regime; Under general situation, the deviate Δ t that reception lead T estimates along with link progressively restrains.That is to say that the method for the embodiment of the invention can satisfy worst error condition, also meet the algorithm requirements of ideal synchronisation situation, and the progressively convergence along with dwindling of timing offset.Descend fast thereby make computational complexity and receive lead thereupon, adapt to the stages such as sleep awakening initial stage, steady operation and optimum state automatically neatly.According to different applied environments, can between processing complexity and convergence rate, realize optimum balance by parameter optimization.
More than the embodiment of the invention is described in detail, used embodiment herein the present invention set forth, the explanation of above embodiment just is used for help understanding method and apparatus of the present invention; Simultaneously, for one of ordinary skill in the art, according to thought of the present invention, the part that all can change in specific embodiments and applications, in sum, this description should not be construed as limitation of the present invention.
Claims (12)
1. a method that improves receiver performance is characterized in that, comprising:
Behind the terminal sleep end cycle, determine this reception lead at timing offset;
Receive the zero-time that lead determines to receive data according to this;
Arrive the back receiving downlink data in described zero-time.
2. method according to claim 1 is characterized in that, described definite this reception lead at timing offset comprises:
After first sleep cycle finishes, according to the predetermined maximum lead T that receives
MaxThis is set receives lead T
1=T
Max
After follow-up sleep cycle finishes, according to the preceding reception lead T that once determines
I-1, determine that this receives lead T
i, i represents the sleep cycle number of times.
3. method according to claim 2 is characterized in that, the described maximum lead T that receives
MaxBe to determine, specifically comprise according to the clock system performance of described terminal:
Determine the longest length of one's sleep of terminal according to maximum discontinuous receiving cycle;
Determine the maximum timing offset of described clock system hardware calibration according to the longest described length of one's sleep;
Determine the maximum lead T that receives according to described maximum timing offset
Max
4. method according to claim 2 is characterized in that, the reception lead T that once determines before the described basis
I-1, determine that this receives lead T
iComprise:
Calculate the timing offset average Δ t after descending reception link timing offset estimated value Δ t and described terminal arrive steady operation
0
Determine that according to following formula this receives lead T
i:
T
i=T
I-1-α * (T
I-1-T
0)/(1+ β * Δ t), wherein, α is a sensitive factor, 1≤α≤T
Max/ (T
Max-T
0); β is a stable factor, β=1/ Δ t
0T
0Be reception lead required under the ideal synchronisation state.
5. method according to claim 4 is characterized in that, according to the sensitiveness of terminal receiving algorithm for timing offset, described T is set
0With sensitive factor α.
6. method according to claim 4 is characterized in that, according to the operating state of terminal described stable factor β is set.
7. a device that improves receiver performance is characterized in that, comprising:
The lead determining unit is used for behind the terminal sleep end cycle, determines this reception lead at timing offset;
The zero-time determining unit is used for receiving the zero-time that lead determines to receive data according to this;
The Data Receiving unit is used for arriving the back receiving downlink data in described zero-time.
8. device according to claim 7 is characterized in that, described lead determining unit comprises:
First determining unit is used for after first sleep cycle finishes, according to the predetermined maximum lead T that receives
Max, this is set receives lead T
1=T
Max
Second determining unit is used for after follow-up sleep cycle finishes, according to the preceding reception lead T that once determines
I-1, determine that this receives lead T
i, i represents the sleep cycle number of times.
9. device according to claim 8 is characterized in that, described device also comprises:
The maximum lead determining unit that receives is used for determining the maximum lead T that receives according to the clock system performance of described terminal
Max, the described maximum lead determining unit that receives comprises:
The longest length of one's sleep, determining unit was used for determining according to maximum discontinuous receiving cycle the longest length of one's sleep of terminal;
Maximum timing offset determining unit is used for determining according to the longest described length of one's sleep the maximum timing offset of described clock system hardware calibration;
The 3rd determining unit is used for determining the maximum lead T that receives according to described maximum timing offset
Max
10. device according to claim 9 is characterized in that, described second determining unit comprises:
First computation subunit is used to calculate descending reception link timing offset estimated value Δ t;
Second computation subunit is used to calculate the timing offset average Δ t after described terminal arrives steady operation
0
The 3rd computation subunit is used for determining that according to following formula this receives lead T
i:
T
i=T
I-1-α * (T
I-1-T
0)/(1+ β * Δ t), wherein, α is a sensitive factor, 1≤α≤T
Max/ (T
Max-T
0); β is a stable factor, β=1/ Δ t
0T
0Be reception lead required under the ideal synchronisation state.
11. device according to claim 10 is characterized in that, also comprises:
First is provided with the unit, is used for according to the sensitiveness of terminal receiving algorithm for timing offset described T being set
0With sensitive factor α.
12. device according to claim 10 is characterized in that, also comprises:
Second is provided with the unit, is used for according to the operating state of terminal described stable factor β being set.
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|---|---|---|---|
| CN200910056050.0A CN101990282B (en) | 2009-08-04 | 2009-08-04 | Method and device for improving performance of receiver |
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|---|---|---|---|
| CN200910056050.0A CN101990282B (en) | 2009-08-04 | 2009-08-04 | Method and device for improving performance of receiver |
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| CN101990282B CN101990282B (en) | 2014-02-05 |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103379600A (en) * | 2012-04-26 | 2013-10-30 | 马维尔国际有限公司 | Discontinuous reception control device, controller and user equipment for long term evolution system |
| CN106411444A (en) * | 2015-07-30 | 2017-02-15 | 联芯科技有限公司 | Timing compensation method and mobile terminal |
| CN106879002A (en) * | 2015-12-11 | 2017-06-20 | 北京展讯高科通信技术有限公司 | A kind of method and device of data processing |
| CN111836348A (en) * | 2020-07-23 | 2020-10-27 | 广东博智林机器人有限公司 | Data receiving method and device based on ultra-wideband positioning tag receiver |
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| CN1968049B (en) * | 2005-11-16 | 2010-05-05 | 联芯科技有限公司 | Synchronization method and device after terminal dormancy awaken of TD_SCDMA mobile phone |
| CN100508635C (en) * | 2006-03-24 | 2009-07-01 | 联芯科技有限公司 | Resynchronization method of mobile terminal under stand-by state woke up from sleep mode |
| CN101296024A (en) * | 2007-04-28 | 2008-10-29 | 中兴通讯股份有限公司 | Uplink Synchronization method for one-way service in mobile communication system |
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2009
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103379600A (en) * | 2012-04-26 | 2013-10-30 | 马维尔国际有限公司 | Discontinuous reception control device, controller and user equipment for long term evolution system |
| CN103379600B (en) * | 2012-04-26 | 2018-04-24 | 马维尔国际有限公司 | Discontinuous reception control device, controller and user equipment for long evolving system |
| CN106411444A (en) * | 2015-07-30 | 2017-02-15 | 联芯科技有限公司 | Timing compensation method and mobile terminal |
| CN106879002A (en) * | 2015-12-11 | 2017-06-20 | 北京展讯高科通信技术有限公司 | A kind of method and device of data processing |
| CN106879002B (en) * | 2015-12-11 | 2020-03-20 | 北京展讯高科通信技术有限公司 | Data processing method and device |
| CN111836348A (en) * | 2020-07-23 | 2020-10-27 | 广东博智林机器人有限公司 | Data receiving method and device based on ultra-wideband positioning tag receiver |
| CN111836348B (en) * | 2020-07-23 | 2023-06-27 | 广东博智林机器人有限公司 | Data receiving method and device based on ultra-wideband positioning tag receiver |
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