CN101990282B - Method and device for improving performance of receiver - Google Patents
Method and device for improving performance of receiver Download PDFInfo
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- CN101990282B CN101990282B CN200910056050.0A CN200910056050A CN101990282B CN 101990282 B CN101990282 B CN 101990282B CN 200910056050 A CN200910056050 A CN 200910056050A CN 101990282 B CN101990282 B CN 101990282B
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
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Abstract
The invention relates to the technical field of communication, and discloses a method and a device for improving performance of a receiver. The method comprises the following steps of: after a terminal sleep cycle ends, determining the receiving lead aiming at timing offset; determining the initial time for receiving data according to the receiving lead; and receiving downlink data after the initial time is up. By adopting the method and the device, the influence of the terminal clock system timing offset on the performance of the receiver can be improved, and the method and the device can be suitable for different application environments.
Description
Technical field
The present invention relates to the communication technology, be specifically related to a kind of method and device that improves receiver performance.
Background technology
Compare with traditional 2G/3G access technology, TD-LTE (Time Division-Long TermEvolution, time-division Long Term Evolution) technology has the raising of several orders of magnitude in data rate and bandwidth.The basic sample frequency of 30.72MHz, other data rate of 100Mbps level, make TD-LTE terminal must and eNodeB (evolution base station) maintenance high level of synchronization, this has just proposed more strict requirement to the timing accuracy of terminal this locality; The operating frequency of device and power consumption also significantly improve thereupon simultaneously.So TD-LTE terminal must be supported DRX (Discontinuous Reception, discontinuous reception) sleep function in the cycle to be to meet the power saving performance of terminal, and DRX parameter has determined that terminal wakes up time interval of monitoring seek channel message when idle condition.
As shown in Figure 1, be the clock system logic diagram of existing terminal:
The clock system of terminal is by work clock generation module 101, Clock management subsystem 102, physical layer subsystem 103, clock alignment circuit 104 and two clocks: 32KHz clock and 20MHz clock form, wherein, 20MHz clock is work clock, and 32KHz clock is a low frequency and low power consumption clock.The operation principle of this clock system is as follows:
1. when terminal determines to enter sleep state, by the zero hour and the duration of physical layer subsystem 103 notice Clock management subsystem 102 sleeps;
2. Clock management subsystem 102 is closed 20MHz work clock, opens 32KHz clock simultaneously, and records the timing starting point deviation of these two clocks, and system enters low power consumpting state;
3. after sleep cycle finishes, Clock management subsystem 102 is opened 20MHz clock, starts clock alignment circuit 104 simultaneously;
4. clock alignment circuit 104, according to the timing offset of the sleep record zero hour, is calibrated work clock, and the work clock after calibration is supplied with to physics straton system 103;
5. physical layer subsystem 103 arranges Tx/Rx (transmitting/receiving) event of radio-frequency module 101, and system enters normal operating conditions.
In terminal sleep process, the work clock of chip is closed, and only with 32K clock, safeguards the synchronizing signal of low-power consumption, low precision.Due to factors such as volume, costs, the clock devices type selecting of terminal is limited in scope, in sleep procedure, the factor such as temperature, voltage can produce larger timing offset while there is skew, even if pass through hardware calibration after sleep awakening, also can produce certain timing offset, synchronous error can be brought the deterioration of algorithm performance, and then affects the receiver performance of terminal.
For this reason, in prior art, be conventionally rule of thumb fixedly installed the method that receives lead.Due to ofdm signal, increase the data volume receiving in advance, the Cyclic Prefix of signal (CP) can be included, synchronized algorithm can identify the accurate location of signal when carrying out related calculation, and then reaches the object of correcting timing offset.
In realizing process of the present invention, inventor finds that said method at least exists following problem: be fixedly installed the method shortage flexibility and the adaptability that receive lead, can not guarantee the performance of algorithm, owing to receiving arranging conventionally of lead, according to emulation, simulation or actual measurement, obtain, therefore there is very large blindness, and cannot adapt to different applied environments.
Summary of the invention
The embodiment of the present invention provides a kind of method and device that improves receiver performance, to improve the impact of terminal clock timing deviation on receiver performance, and can be applicable to different applied environments.
For this reason, the embodiment of the present invention provides following technical scheme:
A method that improves receiver performance, comprising:
After terminal sleep end cycle, determine this reception lead for timing offset;
According to this, receive lead and determine the initial time that receives data;
Receiving downlink data after described initial time arrives.
Preferably, described definite this reception lead for timing offset comprises:
After first sleep cycle finishes, according to the predetermined maximum lead T that receives
max, this is set and receives lead T
1=T
max;
After follow-up sleep cycle finishes, according to front once definite reception lead T
i-1, determine that this receives lead T
i, i represents sleep cycle number of times.
Preferably, the described maximum lead T that receives
maxbe to determine according to the clock system performance of described terminal, specifically comprise:
According to maximum discontinuous receiving cycle, determine the longest length of one's sleep of terminal;
According to the longest described length of one's sleep, determine the maximum timing offset of described clock system hardware calibration;
According to described maximum timing offset, determine the maximum lead T that receives
max.
Preferably, described according to front once definite reception lead T
i-1, determine that this receives lead T
icomprise:
Calculate descending receiver timing offset estimated value Δ t and described terminal and arrive the timing offset average Δ t after steady operation
0;
According to following formula, determine that this receives lead T
i:
T
i=T
i-1-α * (T
i-1-T
0)/(1+ β * Δ t), wherein, α is sensitive factor, 1≤α≤T
max/ (T
max-T
0); β is stable factor, β=1/ Δ t
0; T
0for reception lead required under ideal synchronisation state.
Preferably, the sensitiveness according to terminal receiving algorithm for timing offset, arranges described T
0with sensitive factor α.
Preferably, according to the operating state of terminal, described stable factor β is set.
A device that improves receiver performance, comprising:
Lead determining unit, for after terminal sleep end cycle, determines this reception lead for timing offset;
Initial time determining unit, determines for receiving lead according to this initial time that receives data;
Data receiver unit, for receiving downlink data after arriving in described initial time.
Preferably, described lead determining unit comprises:
The first determining unit, after finishing at first sleep cycle, according to the predetermined maximum lead T that receives
max, this is set and receives lead T
1=T
max;
The second determining unit, after finishing at follow-up sleep cycle, according to front once definite reception lead T
i-1, determine that this receives lead T
i, i represents sleep cycle number of times.
Preferably, described device also comprises:
The maximum lead determining unit that receives, for determining the maximum lead T that receives according to the clock system performance of described terminal
max, the described maximum lead determining unit that receives comprises:
The longest length of one's sleep determining unit, for determine the longest length of one's sleep of terminal according to maximum discontinuous receiving cycle;
Maximum timing offset determining unit, for determining the maximum timing offset of described clock system hardware calibration according to the longest described length of one's sleep;
The 3rd determining unit, for determining the maximum lead T that receives according to described maximum timing offset
max.
Preferably, described the second determining unit comprises:
The first computation subunit, for calculating descending receiver timing offset estimated value Δ t;
The second computation subunit, arrives the timing offset average Δ t after steady operation for calculating described terminal
0;
The 3rd computation subunit, for determining that according to following formula this receives lead T
i:
T
i=T
i-1-α * (T
i-1-T
0)/(1+ β * Δ t), wherein, α is sensitive factor, 1≤α≤T
max/ (T
max-T
0); β is stable factor, β=1/ Δ t
0; T
0for reception lead required under ideal synchronisation state.
Preferably, described device also comprises:
The first setting unit, for the sensitiveness for timing offset according to terminal receiving algorithm, arranges described T
0with sensitive factor α.
Preferably, described device also comprises:
The second setting unit, for arranging described stable factor β according to the operating state of terminal.
The embodiment of the present invention improves method and the device of receiver performance, for prior art, by being fixedly installed, receive lead correction timing offset shortage flexibility and adaptive shortcoming, after the each sleep cycle of terminal finishes, adjust adaptively this reception lead for timing offset, correct the timing offset producing in terminal sleep process, thereby effectively improved the impact of terminal clock timing deviation on receiver performance, there is good flexibility and adaptability.
Further, only in receiving for the first time after each sleep finishes, adopt maximum reception lead, after follow-up sleep finishes, in conjunction with the timing offset output in each receiving course, determine current reception lead, then Fast Convergent, computational complexity and reception lead be fast-descending thereupon, thereby can automatically adapt to neatly terminal sleep, wakes the stages such as initial stage, steady operation and optimum state up.Owing to determining and receiving lead adaptively, thereby go for different applied environments, improve terminal receiver performance.
Accompanying drawing explanation
Fig. 1 is the clock system logic diagram of existing terminal;
Fig. 2 is the flow chart that the embodiment of the present invention improves the method for receiver performance;
Fig. 3 determines the maximum flow chart that receives lead in the embodiment of the present invention;
Fig. 4 is a kind of structural representation that the embodiment of the present invention improves the device of receiver performance;
Fig. 5 is the another kind of structural representation that the embodiment of the present invention improves the device of receiver performance.
Embodiment
In order to make those skilled in the art person understand better the scheme of the embodiment of the present invention, below in conjunction with drawings and embodiments, the embodiment of the present invention is described in further detail.
The embodiment of the present invention improves method and the device of receiver performance, for prior art, by being fixedly installed, receive lead correction timing offset shortage flexibility and adaptive shortcoming, after the each sleep cycle of terminal finishes, adjust adaptively this reception lead for timing offset, correct the timing offset producing in terminal sleep process.Particularly, after first sleep cycle finishes, according to the predetermined maximum lead that receives, this is set and receives lead; After follow-up sleep cycle finishes, according to front once definite reception lead, determine that this receives lead.
As shown in Figure 2, be the flow chart that the embodiment of the present invention improves the method for receiver performance, comprise the following steps:
Particularly, in above-mentioned steps 201, after finishing for first sleep cycle, can be according to the predetermined maximum lead T that receives
max, this is set and receives lead T
1=T
max, certainly, also can make T
1< T
max; After follow-up sleep cycle finishes, can be according to front once definite reception lead T
i-1, determine that this receives lead T
i.Thereby can utilize the adjustment result of down-going synchronous process, dynamically adjust the reception lead after each sleep finishes, the iterative process by limited number of time makes clock synchronous reach fast stable state.
Visible, the embodiment of the present invention improves the method for receiver performance, for prior art, by being fixedly installed, receive lead correction timing offset shortage flexibility and adaptive shortcoming, after the each sleep cycle of terminal finishes, adjust adaptively this reception lead for timing offset, correct the timing offset producing in terminal sleep process, thereby effectively improved the impact of terminal clock timing deviation on receiver performance, there is good flexibility and adaptability.
In embodiments of the present invention, the maximum lead T that receives
maxdetermine and can determine by off-line analysis.As shown in Figure 3, be in the embodiment of the present invention, to determine the maximum a kind of flow chart that receives lead, comprise the following steps:
Described maximum DRX cycle can be determined according to the regulation of agreement, when determining the longest length of one's sleep of terminal, to consider on the one hand the report cycle demand of measuring, on the other hand also will be according to the characteristic of clock devices itself, should be less than or equal to maximum DRX the longest described length of one's sleep.
The factors such as the device that the maximum timing offset of described clock system hardware calibration adopts with the clock alignment circuit of clock system and external environment condition are relevant, particularly, can be according to device performance, calibration cycle, temperature deviation, voltage bias etc. because usually determining the maximum timing offset of clock system hardware calibration.
Such as, can determine by following test process:
Structure test environment: in official hour section, hardware platform (being the clock system of terminal) is implemented to maximum temperature deviation and maximum voltage deviation, by clock alignment circuit, according to the timing offset of the sleep record zero hour, work clock is calibrated.By the clock after calibration and absolute clock contrast, obtain the maximum timing offset of clock system hardware calibration.
Particularly, can assess the receptivity deterioration degree that maximum timing offset brings according to the characteristic of terminal receiving algorithm, such as, a timing offset E is first artificially set
max, in DRP data reception process, do not consider the impact of this timing offset, by receiving algorithm, count this situation with respect to normal condition, receptivity deterioration degree.Then, reference performance deterioration degree is further extrapolated the maximum lead T that receives
max.
Certainly, the maximum lead T that receives in the embodiment of the present invention
maxbe definitely not limited in above-mentioned flow process, can also adopt other modes to determine.
Before mention, after follow-up sleep cycle finishes, can be according to front once definite reception lead T
i-1, determine that this receives lead T
i.Thereby can utilize the adjustment result of down-going synchronous process, dynamically adjust the reception lead after each sleep finishes, the iterative process by limited number of time makes clock synchronous reach fast stable state.
Particularly, can determine the reception lead T after follow-up sleep cycle finishes by following process
i:
(1) calculate descending receiver timing offset estimated value Δ t and described terminal and arrive the timing offset average Δ t after steady operation
0;
Can utilize existing receiving algorithm to obtain descending receiver timing offset estimated value Δ t, and arrive the timing offset average Δ t after steady operation by measuring described terminal
0;
(2) according to following formula, determine that this receives lead T
i:
T
i=T
i-1-α * (T
i-1-T
0)/(1+ β * Δ t), wherein, α is sensitive factor, 1≤α≤T
max/ (T
max-T
0); β is stable factor, β=1/ Δ t
0; T
0for the lower required reception lead of ideal synchronisation state (being Δ t=0);
Particularly, can be according to terminal receiving algorithm the sensitiveness for timing offset, described T is set
0with sensitive factor α, according to the operating state of terminal, described stable factor β is set.
The embodiment of the present invention improves the method for receiver performance, and after finishing owing to sleeping for the first time in terminal, the maximum based on evaluating receives lead T
maxdetermine this reception lead, now Δ t=∞, receives lead T so this can be set
1=T
max, that is to say, the method for the embodiment of the present invention can be held maximum timing offset.In addition, because terminal can be done the estimation of down link reception timing offset constantly, and do on this basis timing offset and control, controlling target is to make Δ t=0.Now receive timing offset amount T=T
max-α * (T
max-T
0), in the situation (being α=1 o'clock) of the limit, T=T
0, the target of control meets the demand of algorithm under desirable synchronous regime; General in the situation that, the deviate Δ t that reception lead T estimates along with link progressively restrains.That is to say, the method for the embodiment of the present invention can meet worst error condition, also meets the algorithm requirements of ideal synchronisation situation, and the progressively convergence along with dwindling of timing offset.Thereby make computational complexity and receive lead fast-descending thereupon, automatically adapt to neatly the stages such as sleep awakening initial stage, steady operation and optimum state.According to different applied environments, by parameter optimization, can between processing complexity and convergence rate, realize optimum balance.
Compare with the existing method of fixed reception lead, the method of the embodiment of the present invention has the control range of clear and definite control target, safety and is closely combined with control object (timing offset), control procedure is clear accurately, convergence rate is variable along with the setting of sensitive factor α, has very strong flexibility.
One of ordinary skill in the art will appreciate that all or part of step realizing in above-described embodiment method is to come the hardware that instruction is relevant to complete by program, described program can be stored in a computer read/write memory medium, described storage medium, as: ROM/RAM, magnetic disc, CD etc.
The embodiment of the present invention also provides a kind of device that improves receiver performance, as shown in Figure 4, is a kind of structural representation of this device.
In this embodiment, described device comprises:
Lead determining unit 401, for after terminal sleep end cycle, determines this reception lead for timing offset;
Initial time determining unit 402, determines for receiving lead according to this initial time that receives data;
In the embodiment of the present invention, a kind of preferred structure of described lead determining unit 401 comprises:
The first determining unit 411, after finishing at first sleep cycle, according to the predetermined maximum lead T that receives
max, this is set and receives lead T
1=T
max;
The second determining unit 412, after finishing at follow-up sleep cycle, according to front once definite reception lead T
i-1, determine that this receives lead T
i, i represents sleep cycle number of times.
The embodiment of the present invention improves the device of receiver performance, for prior art, by being fixedly installed, receive lead correction timing offset shortage flexibility and adaptive shortcoming, after the each sleep cycle of terminal finishes, adjust adaptively this reception lead for timing offset, correct the timing offset producing in terminal sleep process, thereby effectively improved the impact of terminal clock timing deviation on receiver performance, there is good flexibility and adaptability.
As shown in Figure 5, be the another kind of structural representation that the embodiment of the present invention improves the device of receiver performance.
From embodiment illustrated in fig. 4 different, in this embodiment, described device also comprises: the maximum lead determining unit 404 that receives, and for determine the maximum lead T that receives according to the clock system performance of described terminal
max.
The described maximum a kind of preferred embodiment that receives lead determining unit 404 comprises:
The longest length of one's sleep, determining unit 441, for determine the longest length of one's sleep of terminal according to discontinuous receiving cycle;
Maximum timing offset determining unit 442, for determining the maximum timing offset of described clock system hardware calibration according to the longest described length of one's sleep;
The 3rd determining unit 443, for determining the maximum lead T that receives according to described maximum timing offset
max.
Certainly, in the embodiment of the present invention, the described maximum lead determining unit 404 that receives is not limited in said structure, can also have other frame modes.
In embodiments of the present invention, a kind of preferred structure of described the second determining unit 412 comprises: the first computation subunit, the second computation subunit and the 3rd computation subunit.Wherein:
Described the first computation subunit, for calculating descending receiver timing offset estimated value Δ t;
Described the second computation subunit, arrives the timing offset average Δ t after steady operation for calculating described terminal
0;
Described the 3rd computation subunit, for determining that according to following formula this receives lead T
i:
T
i=T
i-1-α * (T
i-1-T
0)/(1+ β * Δ t), wherein, α is sensitive factor, 1≤α≤T
max/ (T
max-T
0); β is stable factor, β=1/ Δ t
0; T
0for reception lead required under ideal synchronisation state.
In the device of the raising receiver performance providing in the embodiment of the present invention, also can further comprise the first setting unit and the second unit, wherein:
Described the first setting unit, for the sensitiveness for timing offset according to terminal receiving algorithm, arranges described T
0with sensitive factor α.
Described the second setting unit, for arranging described stable factor β according to the operating state of terminal.
The embodiment of the present invention improves the device of receiver performance, and after finishing owing to sleeping for the first time in terminal, the maximum based on evaluating receives lead T
maxdetermine this reception lead, now Δ t=∞, receives lead T so this can be set
1=T
max, that is to say, the method for the embodiment of the present invention can be held maximum timing offset.In addition, because terminal can be done the estimation of down link reception timing offset constantly, and do on this basis timing offset and control, controlling target is to make Δ t=0.Now receive timing offset amount T=T
max-α * (T
max-T
0), in the situation (being α=1 o'clock) of the limit, T=T
0, the target of control meets the demand of algorithm under desirable synchronous regime; General in the situation that, the deviate Δ t that reception lead T estimates along with link progressively restrains.That is to say, the method for the embodiment of the present invention can meet worst error condition, also meets the algorithm requirements of ideal synchronisation situation, and the progressively convergence along with dwindling of timing offset.Thereby make computational complexity and receive lead fast-descending thereupon, automatically adapt to neatly the stages such as sleep awakening initial stage, steady operation and optimum state.According to different applied environments, by parameter optimization, can between processing complexity and convergence rate, realize optimum balance.
Above the embodiment of the present invention is described in detail, has applied embodiment herein the present invention is set forth, the explanation of above embodiment is just for helping to understand method and apparatus of the present invention; , for one of ordinary skill in the art, according to thought of the present invention, all will change in specific embodiments and applications, in sum, this description should not be construed as limitation of the present invention meanwhile.
Claims (8)
1. a method that improves receiver performance, is characterized in that, comprising:
After terminal sleep end cycle, determine this reception lead for timing offset;
According to this, receive lead and determine the initial time that receives data;
Receiving downlink data after described initial time arrives;
Wherein, described definite this reception lead for timing offset comprises:
After first sleep cycle finishes, according to the predetermined maximum lead T that receives
max, this is set and receives lead T
1=T
max;
After follow-up sleep cycle finishes, according to front once definite reception lead T
i-1, determine that this receives lead T
i, i represents sleep cycle number of times;
Wherein, described according to front once definite reception lead T
i-1, determine that this receives lead T
icomprise:
Calculate descending receiver timing offset estimated value Δ t and described terminal and arrive the timing offset average Δ t after steady operation
0;
According to following formula, determine that this receives lead T
i:
T
i=T
i-1-α * (T
i-1-T
0)/(1+ β * Δ t), wherein, α is sensitive factor, 1≤α≤T
max/ (T
max-T
0); β is stable factor, β=1/ Δ t
0; T
0for reception lead required under ideal synchronisation state.
2. method according to claim 1, is characterized in that, the described maximum lead T that receives
maxbe to determine according to the clock system performance of described terminal, specifically comprise:
According to maximum discontinuous receiving cycle, determine the longest length of one's sleep of terminal;
According to the longest described length of one's sleep, determine the maximum timing offset of described clock system hardware calibration;
According to described maximum timing offset, determine the maximum lead T that receives
max.
3. method according to claim 1, is characterized in that, the sensitiveness according to terminal receiving algorithm for timing offset arranges described T
0with sensitive factor α.
4. method according to claim 1, is characterized in that, according to the operating state of terminal, described stable factor β is set.
5. a device that improves receiver performance, is characterized in that, comprising:
Lead determining unit, for after terminal sleep end cycle, determines this reception lead for timing offset;
Initial time determining unit, determines for receiving lead according to this initial time that receives data;
Data receiver unit, for receiving downlink data after arriving in described initial time;
Wherein, described lead determining unit comprises:
The first determining unit, after finishing at first sleep cycle, according to the predetermined maximum lead T that receives
max, this is set and receives lead T
1=T
max;
The second determining unit, after finishing at follow-up sleep cycle, according to front once definite reception lead T
i-1, determine that this receives lead T
i, i represents sleep cycle number of times;
Wherein, described the second determining unit comprises:
The first computation subunit, for calculating descending receiver timing offset estimated value Δ t;
The second computation subunit, arrives the timing offset average Δ t after steady operation for calculating described terminal
0;
The 3rd computation subunit, for determining that according to following formula this receives lead T
i:
T
i=T
i-1-α * (T
i-1-T
0)/(1+ β * Δ t), wherein, α is sensitive factor, 1≤α≤T
max/ (T
max-T
0); β is stable factor, β=1/ Δ t
0; T
0for reception lead required under ideal synchronisation state.
6. device according to claim 5, is characterized in that, described device also comprises:
The maximum lead determining unit that receives, for determining the maximum lead T that receives according to the clock system performance of described terminal
max, the described maximum lead determining unit that receives comprises:
The longest length of one's sleep determining unit, for determine the longest length of one's sleep of terminal according to maximum discontinuous receiving cycle;
Maximum timing offset determining unit, for determining the maximum timing offset of described clock system hardware calibration according to the longest described length of one's sleep;
The 3rd determining unit, for determining the maximum lead T that receives according to described maximum timing offset
max.
7. device according to claim 5, is characterized in that, also comprises:
The first setting unit, for the sensitiveness for timing offset according to terminal receiving algorithm, arranges described T0 and sensitive factor α.
8. device according to claim 5, is characterized in that, also comprises:
The second setting unit, for arranging described stable factor β according to the operating state of terminal.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910056050.0A CN101990282B (en) | 2009-08-04 | 2009-08-04 | Method and device for improving performance of receiver |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910056050.0A CN101990282B (en) | 2009-08-04 | 2009-08-04 | Method and device for improving performance of receiver |
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| Publication Number | Publication Date |
|---|---|
| CN101990282A CN101990282A (en) | 2011-03-23 |
| CN101990282B true CN101990282B (en) | 2014-02-05 |
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ID=43746527
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|---|---|---|---|
| CN200910056050.0A Active CN101990282B (en) | 2009-08-04 | 2009-08-04 | Method and device for improving performance of receiver |
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Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103379600B (en) * | 2012-04-26 | 2018-04-24 | 马维尔国际有限公司 | Discontinuous reception control device, controller and user equipment for long evolving system |
| CN106411444A (en) * | 2015-07-30 | 2017-02-15 | 联芯科技有限公司 | Timing compensation method and mobile terminal |
| CN106879002B (en) * | 2015-12-11 | 2020-03-20 | 北京展讯高科通信技术有限公司 | Data processing method and device |
| CN111836348B (en) * | 2020-07-23 | 2023-06-27 | 广东博智林机器人有限公司 | Data receiving method and device based on ultra-wideband positioning tag receiver |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1968049A (en) * | 2005-11-16 | 2007-05-23 | 大唐移动通信设备有限公司 | Synchronization method and device after terminal dormancy awaken of TD_SCDMA mobile phone |
| CN101043670A (en) * | 2006-03-24 | 2007-09-26 | 大唐移动通信设备有限公司 | Resynchronization method of mobile terminal under stand-by state woke up from sleep mode |
| CN101296024A (en) * | 2007-04-28 | 2008-10-29 | 中兴通讯股份有限公司 | Uplink Synchronization method for one-way service in mobile communication system |
-
2009
- 2009-08-04 CN CN200910056050.0A patent/CN101990282B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1968049A (en) * | 2005-11-16 | 2007-05-23 | 大唐移动通信设备有限公司 | Synchronization method and device after terminal dormancy awaken of TD_SCDMA mobile phone |
| CN101043670A (en) * | 2006-03-24 | 2007-09-26 | 大唐移动通信设备有限公司 | Resynchronization method of mobile terminal under stand-by state woke up from sleep mode |
| CN101296024A (en) * | 2007-04-28 | 2008-10-29 | 中兴通讯股份有限公司 | Uplink Synchronization method for one-way service in mobile communication system |
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