CN101090547A - Method and device for calibrating sleep clock of TD-SCDMA terminal - Google Patents

Abstract

This invention provides a method and a device for calibrating TD-SCDMA terminal sleep clock including: in each DRX period, a synchronous error between timing of terminals and timing of base stations is obtained to judge if said error is greater than the length of a TD-SCDMA systematic synchronous window, if so, the calibration is done, otherwise, the calibration is not done, which can prolong the actual sleep time of terminals under the stand-by mode so as to prolong the stand-by time of terminal.

Description

A kind of method and apparatus of TD-SCDMA terminal sleep clock alignment

Technical field

The present invention relates to the calibrating sleep clock technology of wireless terminal, particularly relate to a kind of method and apparatus of TD-SCDMA terminal sleep clock alignment.

Background technology

TD SDMA (TD-SCDMA) system is a synchronous communication system, terminal must and the base station carry out correct time synchronously to guarantee the proper communication between the two.Under mode of operation, terminal is produced the sequential and the timing of various needs by high frequency clock, for the operation of control of baseband chip, radio frequency and system provides the precise time reference, this high frequency clock is time precision (be 97.66ns, be converted into clock frequency and then be 10.24Mhz) with 1/8th spreading rates of TD-SCDMA system.

Under standby mode, terminal is carried out the sleep awakening process according to discontinuous reception (DRX) cycle that network side disposed, all high frequency clocks are stopped to reduce power consumption during sleep, and this moment, terminal replaced the higher high frequency clock of precision to produce the sequential and the timing of various needs by the 32KHz clock (being sleep clock again) of low frequency.Because the 32KHz clock frequency is very low, the precision of crystal itself has than mistake, and its frequency varies with temperature and changes, thereby the frequency drift of this low-frequency clock will have a strong impact on the synchronization timing between terminal and the base station, must compensate its drift by the calibration (calibration) of high frequency clock and low-frequency clock, time reference after making terminal according to calibration is readjusted the timing of self, and is accurately synchronous to guarantee with the base station.

Calibration process is in the alignment time of regulation, calculates the mean number of 10.24Mhz clock cycle in each 32KHz clock cycle, and desired result is 312.5 (10.24MHz/32768Hz=312.5).If the 32KHz clock frequency has skew under standby mode, then this value also can depart from 312.5, and the result of calibration is exactly actual concussion frequency and the relation of the actual ratio between the 10.24Mhz clock that obtains current 32KHz clock.Certainly, the alignment time is long more, and the calibration result of its acquisition is just accurate more.

Because calibration process needs high-speed clock signal, and require baseband chip in running order, so terminal just can enter sleep pattern after calibration is finished, also be that calibration process has shortened the actual length of one's sleep under the standby mode, thereby shortened the stand-by time of terminal.Prior art is all carried out primary calibration in each DRX cycle, and the duration of each calibration be long fixed value, this makes terminal shorter the actual length of one's sleep, further its stand-by time is caused adverse effect.

Summary of the invention

Technical problem to be solved by this invention provides a kind of method and apparatus of TD-SCDMA terminal sleep clock alignment, prolonging the actual length of one's sleep of terminal under standby mode, thereby prolongs the stand-by time of terminal.

For solving the problems of the technologies described above, it is as follows to the invention provides technical scheme:

A kind of method of TD-SCDMA terminal sleep clock alignment comprises:

In each DRX cycle, obtain the synchronous error between terminal timing and the base station timing;

Whether judge described synchronous error greater than TD-SCDMA system synchronization window length, if, then carry out calibrating sleep clock, otherwise, in current DRX cycle, do not carry out calibrating sleep clock.

Preferably, described obtain terminal regularly and the synchronous error of base station between regularly comprise: descending pilot frequency time slot (DwPTS) correlation peak of computing terminal expection constantly and the DwPTS correlation peak of actual measurement difference constantly, and with described difference as synchronous error.

Preferably, the described calibrating sleep clock that carries out comprises:

Obtain the length of one's sleep and the sleep clock crystalline environment temperature change value of terminal in the current DRX cycle, according to the length of one's sleep of obtaining and variation of ambient temperature value calculating the calibration duration;

Calculating in the described calibration duration, the mean number in the high frequency clock cycle in each sleep clock cycle, and export this mean value to baseband processor as the clock alignment result.

Preferably, calculate calibration duration t according to following formula _Cal:

$t_{\mathrm{cal}}=k_2/(\frac{T_{\mathrm{SYNC}}-\mathrm{\Δ}{t}_{\mathrm{OSC}}}{t_{\mathrm{sleep}}}-k_3\·V_{\mathrm{UE}}-\frac{k_1}{\mathrm{\ΔC}}),$ Wherein, k ₁, k ₂, k ₃Be constant, T _SYNCBe TD-SCDMA system synchronization window length, Δ t _OscBe the shake of sleep clock, V _UEBe the maximum rate of terminal, t _SleepBe the length of one's sleep of terminal in the current DRX cycle, Δ C is a sleep clock crystalline environment temperature change value.

Preferably, comprise the described length of one's sleep of obtaining terminal in the current DRX cycle: obtain the current DRX cycle value of TD-SCDMA grid side, and with the length of one's sleep of this DRX cycle value as terminal.

A kind of device of TD-SCDMA terminal sleep clock alignment comprises:

The calibration judge module, be used at each DRX cycle, obtain the synchronous error between terminal timing and the base station timing, judge that whether described synchronous error is greater than TD-SCDMA system synchronization window length, and during greater than TD-SCDMA system synchronization window length, enable alignment time computing module and calibration Executive Module in definite described synchronous error;

The alignment time computing module is used for calculating the calibration duration;

The calibration Executive Module was used for calculating in the described calibration duration, the mean number in the high frequency clock cycle that each sleep clock cycle is interior, and export this mean value to baseband processor as the clock alignment result.

Preferably, described calibration judge module, the DwPTS correlation peak that is further used for computing terminal expection constantly and the DwPTS correlation peak of actual measurement difference constantly, and with described difference as synchronous error.

Preferably, described alignment time computing module is further used for obtaining the length of one's sleep and the sleep clock crystalline environment temperature change value of terminal in the current DRX cycle, according to the length of one's sleep of obtaining and variation of ambient temperature value calculating the calibration duration.

Preferably, described alignment time computing module calculates calibration duration t according to following formula _Cal:

$t_{\mathrm{cal}}=k_2/(\frac{T_{\mathrm{SYNC}}-\mathrm{\Δ}{t}_{\mathrm{OSC}}}{t_{\mathrm{sleep}}}-k_3\·V_{\mathrm{UE}}-\frac{k_1}{\mathrm{\ΔC}}),$ Wherein, k ₁, K ₂, k ₃Be constant, T _SYNCBe TD-SCDMA system synchronization window length, Δ t _OscBe the shake of sleep clock, V _UEBe the maximum rate of terminal, t _SleepBe the length of one's sleep of terminal in the current DRX cycle, Δ C is a sleep clock crystalline environment temperature change value.

Preferably, described alignment time computing module is further used for obtaining the current DRX cycle value of TD-SCDMA grid side, and with the length of one's sleep of this DRX cycle value as terminal.

Compared with prior art, the invention has the beneficial effects as follows:

The present invention utilizes the technical characterstic of TD-SCDMA system, in each DRX cycle, all judge whether to carry out the calibration of sleep clock, only regularly and the synchronous error of base station between regularly during greater than the synchronous window length of system in terminal, just calibrate, reduced the number of times of clock alignment, the prolongation of equivalence the actual length of one's sleep of terminal under standby mode, thereby prolonged the stand-by time of terminal;

The present invention also utilizes the technical characterstic of TD-SCDMA system, has effectively reduced the average duration of clock alignment, has further prolonged the actual length of one's sleep of terminal under standby mode.

Description of drawings

Fig. 1 is the flow chart of the TD-SCDMA terminal sleep clock correcting method of preferred embodiment of the present invention;

Fig. 2 is the structural representation of the TD-SCDMA terminal sleep clock calibrating device of preferred embodiment of the present invention.

Embodiment

For making the purpose, technical solutions and advantages of the present invention clearer, describe the present invention below in conjunction with the accompanying drawings and the specific embodiments.

Key of the present invention is: since standby mode under the TD-SCDMA terminal in each DRX cycle, all need to wake up once, and it is synchronous with the DwPTS of base station, if the synchronous error between terminal timing and the base station timing is not more than the synchronous window length of system, then do not need to carry out calibrating sleep clock; Further, under the prerequisite that satisfies the clock alignment precision, utilize the parameter of network side in the TD-SCDMA system and the environmental parameter of terminal itself, dynamically adjust the duration of calibration.

The synchronous window length of supposing the TD-SCDMA system is T _SYNC(the synchronous window length of different algorithm correspondences may be different, can be provided with flexibly according to the concrete technology implementation method of different terminals), if the synchronous error between terminal timing and the base station timing is greater than this synchronous window, then terminal can't with base station synchronization, therefore require the synchronous error Δ t after each sleep finishes _SleepMust be less than T _SYNC:

Δt _sleep≤T _SYNC (1)

That is to say, only at Δ t _Sleep＞T _SYNCThe time just need carry out the calibration of sleep clock.Wherein, the synchronous error Δ t that terminal is introduced owing to sleep under the standby mode _SleepDepend primarily on following factor:

1, under the standby mode, the t length of one's sleep of terminal in each DRX cycle _Sleep, the length of one's sleep and DRX cycle value approximately equal, obviously, single is long more the length of one's sleep, influenced by extraneous factor and the synchronous error introduced is big more;

2, the precision 1/f of calibration process _CalT _Cal, wherein, f _CalBe the reference clock frequency (being high frequency clock 10.24MHz) of calibration process, t _CalBe the calibration duration, its value is very big to the synchronous error influence, can be provided with according to the requirement of calibration accuracy;

3, the frequency accuracy of sleep clock crystal (32KHz) comprises that the absolute frequency precision of crystal and frequency vary with temperature and the precision that changes (is used temperature coefficient a ₀Weigh), the variation of ambient temperature value Δ C of crystal and the temperature coefficient of crystal are very big to the synchronous error influence;

4, clock jitter Δ t is supposed in the shake of sleep clock _OscLess than 100ns (≈ 1/6chip), because the average result of clock jitter is almost 0, so it is very little to synchronous drift influence;

5, the fast moving of terminal, the terminal of fast moving can be introduced Doppler effect, thereby causes synchronous error, and the maximum rate of supposing terminal is V _UE(the TD-SCDMA standard code is 120km/h), then synchronous error is t _SleepV _UE/ V ₀, V wherein ₀Be the light velocity, as seen, the synchronous error of being introduced by Doppler effect is very little.

By above analysis as can be known, synchronous error Δ t _SleepCan determine by following formula:

Δt _sleep＝t _sleep(k ₁/ΔC+k ₂/t _cal+k ₃·V _UE)+Δt _osc (2)

From (1) (2) two formulas, can solve calibration duration t _Cal:

$t_{\mathrm{cal}}=k_2/(\frac{T_{\mathrm{SYNC}}-\mathrm{\Δ}{t}_{\mathrm{OSC}}}{t_{\mathrm{sleep}}}-k_3\·V_{\mathrm{UE}}-\frac{k_1}{\mathrm{\ΔC}})---\left(3\right)$

Wherein, k ₁, k ₂, k ₃, T _SYNC, Δ t _Osc, V _UEAll be approximately and be constant, then calibrate duration t _CalDepend primarily on the t length of one's sleep of terminal _SleepWith crystalline environment temperature change value Δ C.

Based on above analysis, please refer to Fig. 1, the calibrating sleep clock method of preferred embodiment of the present invention comprises the steps:

Step 101, in each DRX cycle, obtain terminal regularly and the synchronous error of base station between regularly;

Wherein, can be used as synchronous error with the DwPTS correlation peak of surveying difference constantly constantly by the DwPTS correlation peak of computing terminal expection.

Step 102～103, whether judge described synchronous error greater than TD-SCDMA system synchronization window length, if, then carry out calibrating sleep clock, otherwise, in current DRX cycle, do not carry out calibrating sleep clock.

In the present embodiment, the process of carrying out calibrating sleep clock is: obtain the length of one's sleep and the sleep clock crystalline environment temperature change value of terminal in the current DRX cycle, according to the length of one's sleep of obtaining and variation of ambient temperature value calculating the calibration duration; Calculating in the described calibration duration, the mean number in the high frequency clock cycle (10.24Mhz) in each sleep clock cycle (32KHz), and export this mean value to baseband processor as the clock alignment result.Wherein, can calculate calibration duration t according to formula (3) _Cal, because the length of one's sleep and DRX cycle value approximately equal,, replace t in the formula (3) with this periodic quantity so in the described method of preferred embodiment of the present invention, also further obtain the current DRX cycle value of TD-SCDMA grid side _Sleep

Please refer to Fig. 2, the calibrating sleep clock device of preferred embodiment of the present invention comprises calibration judge module 21, alignment time computing module 22 and calibration Executive Module 23.

Calibration judge module 21 is used at each DRX cycle, obtain the synchronous error between terminal timing and the base station timing, judge that whether described synchronous error is greater than TD-SCDMA system synchronization window length, during greater than TD-SCDMA system synchronization window length, enable alignment time computing module 22 and calibration Executive Module 23 in definite described synchronous error.

The concrete operations that calibration judge module 21 is carried out are:

Obtain the DwPTS correlation peak moment T of terminal expection ₀DwPTS correlation peak moment T with actual measurement ₁

By calculating the synchronous error Δ T=|T between terminal timing and the base station timing ₀-T ₁|;

With the synchronous error Δ T that obtains and the synchronous window T of TD-SCDMA system _SYNCCompare, if Δ T＞T _SYNC, then carry out calibrating sleep clock with calibration Executive Module 23, otherwise do not need to carry out calibrating sleep clock by enabling alignment time computing module 22.

Alignment time computing module 22 is used for calculating the calibration duration.

The concrete operations that alignment time computing module 22 is carried out are:

Reading of network side parameter: read the current network side parameter of TD-SCDMA system---DRX cycle value, with the t length of one's sleep of this DRX cycle value as terminal _Sleep

The calculating of sleep clock crystalline environment temperature change value: the absolute value delta C that changes between the ambient temperature when calculating the ambient temperature of crystal in the current DRX cycle and a preceding clock alignment; Obtaining on hardware circuit of this value can perhaps utilize the high accuracy integrated temperature sensor to obtain by the mode of thermistor and voltage/temperature look-up table;

Obtaining the t length of one's sleep _SleepBehind temperature change value Δ C, alignment time computing module 22 calculates the required duration t of this time calibration according to formula (3) _Cal

Calibration Executive Module 23 was used for calculating in the described calibration duration, the mean number in the high frequency clock cycle that each sleep clock cycle is interior, and export this mean value to baseband processor as the clock alignment result.

Specifically, be exactly at t _CalIn time, calculate the mean number of 10.24Mhz clock cycle in each 32KHz clock cycle, and export this mean value to baseband processor as the clock alignment result.

Should be noted that at last, above embodiment is only unrestricted in order to technical scheme of the present invention to be described, those of ordinary skill in the art is to be understood that, can make amendment or be equal to replacement technical scheme of the present invention, and not breaking away from the spiritual scope of technical solution of the present invention, it all should be encompassed in the middle of the claim scope of the present invention.

Claims (10)

1. the method for a TD-SCDMA terminal sleep clock alignment is characterized in that, comprising:

In each discontinuous reception DRX period, obtain the synchronous error between terminal timing and the base station timing;

Whether judge described synchronous error greater than TD-SCDMA system synchronization window length, if, then carry out calibrating sleep clock, otherwise, in current DRX cycle, do not carry out calibrating sleep clock.

2. the method for claim 1 is characterized in that, the described synchronous error of obtaining between terminal timing and the base station timing comprises:

The descending pilot frequency time slot DwPTS correlation peak of computing terminal expection constantly and the DwPTS correlation peak of actual measurement difference constantly, and with described difference as synchronous error.

3. the method for claim 1 is characterized in that, the described calibrating sleep clock that carries out comprises:

Obtain the length of one's sleep and the sleep clock crystalline environment temperature change value of terminal in the current DRX cycle, according to the length of one's sleep of obtaining and variation of ambient temperature value calculating the calibration duration;

Calculating in the described calibration duration, the mean number in the high frequency clock cycle in each sleep clock cycle, and export this mean value to baseband processor as the clock alignment result.

4. method as claimed in claim 3 is characterized in that, calculates calibration duration t according to following formula _Cal:

$t_{\mathrm{cal}}=k_2/(\frac{T_{\mathrm{SYNC}}-\mathrm{\Δ}{t}_{\mathrm{OSC}}}{t_{\mathrm{sleep}}}-k_3\·V_{\mathrm{UE}}-\frac{K_1}{\mathrm{\ΔC}}),$ Wherein, k ₁, k ₂, k ₃Be constant, T _SYNCBe TD-SCDMA system synchronization window length, Δ t _OscBe the shake of sleep clock, V _UEBe the maximum rate of terminal, t _SleepBe the length of one's sleep of terminal in the current DRX cycle, Δ C is a sleep clock crystalline environment temperature change value.

5. method as claimed in claim 3 is characterized in that, comprises the described length of one's sleep of obtaining terminal in the current DRX cycle:

Obtain the current DRX cycle value of TD-SCDMA grid side, and with the length of one's sleep of this DRX cycle value as terminal.

6. the device of a TD-SCDMA terminal sleep clock alignment is characterized in that, comprising:

The calibration judge module, be used at each DRX cycle, obtain the synchronous error between terminal timing and the base station timing, judge that whether described synchronous error is greater than TD-SCDMA system synchronization window length, and during greater than TD-SCDMA system synchronization window length, enable alignment time computing module and calibration Executive Module in definite described synchronous error;

The alignment time computing module is used for calculating the calibration duration;

The calibration Executive Module was used for calculating in the described calibration duration, the mean number in the high frequency clock cycle that each sleep clock cycle is interior, and export this mean value to baseband processor as the clock alignment result.

7. device as claimed in claim 6 is characterized in that:

Described calibration judge module, the DwPTS correlation peak that is further used for computing terminal expection constantly and the DwPTS correlation peak of actual measurement difference constantly, and with described difference as synchronous error.

8. device as claimed in claim 6 is characterized in that:

Described alignment time computing module is further used for obtaining the length of one's sleep and the sleep clock crystalline environment temperature change value of terminal in the current DRX cycle, according to the length of one's sleep of obtaining and variation of ambient temperature value calculating the calibration duration.

9. device as claimed in claim 8 is characterized in that, described alignment time computing module calculates calibration duration t according to following formula _Cal:

$t_{\mathrm{cal}}=k_2/(\frac{T_{\mathrm{SYNC}}-\mathrm{\Δ}{t}_{\mathrm{OSC}}}{t_{\mathrm{sleep}}}-k_3\·V_{\mathrm{UE}}-\frac{k_1}{\mathrm{\ΔC}}),$ Wherein, k ₁, k ₂, k ₃Be constant, T _SYNCBe TD-SCDMA system synchronization window length, Δ t _OscBe the shake of sleep clock, V _UEBe the maximum rate of terminal, t _SleepBe the length of one's sleep of terminal in the current DRX cycle, Δ C is a sleep clock crystalline environment temperature change value.

10. device as claimed in claim 8 is characterized in that:

Described alignment time computing module is further used for obtaining the current DRX cycle value of TD-SCDMA grid side, and with the length of one's sleep of this DRX cycle value as terminal.

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