CN101981699B - Semiconductor-based large-area flexible electronic devices - Google Patents

Semiconductor-based large-area flexible electronic devices Download PDF

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CN101981699B
CN101981699B CN2008801281895A CN200880128189A CN101981699B CN 101981699 B CN101981699 B CN 101981699B CN 2008801281895 A CN2008801281895 A CN 2008801281895A CN 200880128189 A CN200880128189 A CN 200880128189A CN 101981699 B CN101981699 B CN 101981699B
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electronic device
layer
texture
semiconductor
resilient coating
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CN101981699A (en
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阿米特·戈亚尔
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Abstract

Novel articles and methods to fabricate the same resulting in flexible, {100}<100> or 45 DEG -rotated {100}<100> oriented, semiconductor-based, electronic devices are disclosed. Potential applications of resulting articles are in areas of photovoltaic devices, flat-panel displays, thermophotovoltaic devices, ferroelectric devices, light emitting diode devices,, computer hard disc drive devices, magnetoresistance based devices, photoluminescence based devices, non-volatile memory devices, dielectric devices, thermoelectric devices and quantum dot laser devices.

Description

The large area flexible electronic device of based semiconductor
About the research of federal funding or the statement of exploitation
The present invention makes under the government according to the contract of being rewarded by USDOE DE-AC05-000R22725 number supports.Government enjoys some right among the present invention.
Invention field
The present invention relates to comprise the manufacturing of various types of semi-conductive high-performance electronic devices and the goods that obtain thus.
Background of invention
This world application is the PCT application corresponding to No. the 12/011st, 450, the U.S. Patent application of submitting on January 28th, 2008.U.S. Patent application is for the 12/011st, No. 450 the part continuation application of No. the 11/715th, 047, the U.S. Patent application submitted on March 8th, 2007.International Application Serial No. PCT/US2008/002944 and U.S. Patent application are correlated with for the 11/715th, No. 047.The part continuation application that No. the 11/498th, 120, No. the 12/011st, 450, U.S. Patent application or undocumented U.S. Patent application.
The electronic device of based semiconductor, for example diode, transistor and integrated circuit can be seen everywhere.Many in using for these if the cost of device is reduced significantly, it is contemplated that more application so.Particularly for photovoltaic application or Application of Solar Energy, for all transducers, and for other applications, for example ferro-electric device, be used for light-emitting diode that solid-state illumination uses, such as the storage of computer hard disc driver use, based on the device of magnetic resistance, based on the device of luminescence generated by light, nonvolatile memory application, dielectric devices, thermoelectric device, really so.
The use of regenerative resource will be necessary for the future in this world that we live just therein.Solar energy has unlimited potentiality satisfying global energy requirement.Yet in the past twenty years, the rosy prospect of solar energy fails to realize all the time.This mainly be since the solar cell of producing now can't gratifying cost performance.Further technological innovation has and realizes for reducing price so that solar energy is more cheap or equate necessary economically and the potentiality coml breakthrough with fossil fuel on cost than fossil fuel.
Film photovoltaic cell (PV) has significant advantage with respect to traditional crystal Si battery based on wafer.The major advantage of film is to compare lower material and manufacturing cost and higher productivity ratio with single crystal technology.Film uses 1/20 to 1/100 of the needed material of crystal Si PV, and looks the lower production of cost that is suitable for more automation.At present, three kinds of membrane technologies are obtaining the very big concern from extensive PV industry: amorphous Si, CuInSe 2And CdTe.In most of the cases, module efficiency and battery efficiency are closely related, have because the loss (～10%) of some loss of effective area and the trace that some ohmic loss causes.For further raise the efficiency and for can be renewable the place of production make the high efficiency battery of based thin film, need the micro-structural feature of control limiting performance.Although the fully understanding for the micro-structural feature of limiting performance remains unclear, reasonably quite clearly be the defect and impurity place again in conjunction with being crucial in crystal boundary, crystal grain.In order to minimize the effect of crystal boundary, have large crystal grain or only the film of the GB of low energy be an object.
Because single crystalline substrate is with high costs to unavailable, so most of thin-film solar cells is based on the device layer of polycrystalline.Because described device layer is polycrystalline, so they do not have clear and definite crystalline orientation (crystallographic orientation) (the outer and face of face interior the two).Crystalline orientation can have two important effects.The firstth, the orientation effect of aufwuchsplate when combining dopant, intrinsic defect and other impurity.The above-mentioned research to multiple dopant shows, based on crystalline orientation, the variation of 1 to 2 order of magnitude can occur.The extreme effect that anisotropy is mixed is the doping of Si in the GaAs film.The doping of Si in the GaAs film causes the N-shaped conduction on (111) Type B GaAs, but at (111) A type GaAs p-type electric-conducting arranged.Second effect of crystalline orientation is the variation of the growth rate of the film that is being deposited.Test and simulate the two and show that all under certain conditions, growth rate can change with 1 to 2 order of magnitude as the function of crystalline orientation.There is the uncontrolled crystalline orientation in the PV material of large grain size can therefore cause the reproducibility problem, and therefore during producing in enormous quantities, reduces productive rate.Certainly, the crystal boundary of the infall of the crystal grain in polycrystal film is as disadvantageous recombination center.
The most of micro-structural features that are considered at present to have limited the thin-film solar cells performance of polycrystalline can be avoided by growing epitaxial film on the single crystalline substrate of Lattice Matching.Yet single crystalline substrate expensive stoped their uses in real world applications.If grain size is large (having the granularity of minimum impact to depend on inter alia doped level on character) enough, the effect of crystal boundary can be inhibited in the polycrystalline photovoltaic film.Yet in film, grain growth is normally constrained to the twice of the thickness that only is film.Therefore, the crystal boundary in the polycrystalline film has the conclusive impact on efficient.The impact of crystal boundary on Photovoltaic Properties reported in a lot of researchs.
Although the major part of above discussion has concentrated on the solar cell application, but also have many application, in these are used, when effective size of needed monocrystalline when diameter is about 100 μ m or hundreds of micron, need to be for the manufacture of the semiconductor film (single crystal-likesemiconductor film) of near single in fact can expand large-scale method cheaply.In addition, use for some, semiconductor surface/film/wafer need to be flexible, thus make wherein crooked semiconductor may be expectation application become possibility.For example, for solar cell application, the profile that makes the PV module meet the top when it is placed may be expected.Thin-film transistor is for the manufacture of display.In this is used, people also can easily recognize flexibility with large area display on purposes.
For electronic device, the oldered array of three-dimensional manometer point and nanometer rods provides the hope that device physics is extended to two-dimentional or three-dimensional completely restriction (quantum wire and quantum dot).Transportation and the optical property that significantly change is compared with block or planar heterojunction structure foretold in multidimensional restriction in these low dimension structures for a long time.In recent years, charge quantization has stimulated the impact of the transportation of little semiconductor-quantum-point manyly is enough to the research of the single-electron device of control device to the transmission of Single Electron wherein.Promotion is the semiconductor band gap process capability of the rapid expansion that provided by modern epitaxial growth to the most important factor of the active research of quantum effect.Possible application comprises spin transistor and single-electronic transistor.Other possible application of three-dimensional order nano dot and nanometer rods are included in the potential application on optoelectronics and the transducer.For example, the array of the luminous ordered nano point in the residuite can be used for using the device of luminescence generated by light effect.Other application are included in the application in high efficiency photovoltaic, the solid-state illumination device etc.
Summary of the invention
The present invention relates to manufacturing large-area, flexible, based semiconductor, that have high performance electronic device.The present invention obtains having on the crystallography (crystallographically texture) semiconductor device of texture.The present invention obtains the manufacturing of the semiconductor device layer of " single shaft " texture, " twin shaft " texture and " three axles " texture.Device is " flexibility " still.
As used herein, " three axle texture " refer to all relative to each other arrangements of three crystallographic axis of all crystal grains in the material.The structure cell of all material can be take three reference axis a, b and c as feature.The orientation of the single crystal grain in the polycrystalline specimen can be by its a, b and c crystallographic axis and the definition of reference coupon coordinate system angulation." single shaft texture " refers to consist of any one arrangement in these axles in the crystal grain of polycrystalline specimens at all." single shaft texture degree (degree of uniaxial texture) " can measure with Electron Back-Scattered Diffraction or by X-ray diffraction.Usually, it is found that crystal grain has the normal distribution that the feature bell curve is arranged or the Gaussian Profile of orientation.The half width of this Gaussian Profile (FWHM) or peak are " single shaft texture degree ", and definition " sharpness of texture (sharpness of thetexture) ".The sharpness of texture also is called as " inlaying (mosaic) ".Biaxial texture refers to two situations of arranging with certain degree or sharpness in three crystallographic axis of all crystal grains wherein.Three axle texture refer to the situation that whole three crystallographic axis of all crystal grains are wherein arranged with certain degree or sharpness.For example, three axle texture take 10 ° FWHM as the feature meaning is three crystallographic axis of all crystal grains of constituent material, i.e. a, b and c, the independent distribution of orientation can be described to half width be 10 ° distribution.
As used herein, " flexible " refers to device is not caused around 12 inches bent spindle the ability of the weakening of device electronic property.
In order to realize above-mentioned goods with other, and according to as in this article implementation and widely the description purpose of the present invention, the invention provides the electronic device goods, it comprises: (a) flexible, large crystal grain, crystalline metal or alloy substrate, it has macroscopic view, [100] or the single shaft texture of [110], have take less than the half widths (FWHM) of 10 degree as the sharpness of feature, (b) at least one resilient coating on described substrate, described at least one resilient coating is selected from and comprises metal, alloy, nitride, boride, oxide, fluoride, carbide, silicide, with the intermetallic alloy of germanium or the group of its combination, and the top resilient coating has the single shaft texture of [100] or [110] of macroscopic view, have take less than the half widths (FWHM) of 10 degree as the sharpness of feature, and (c) at least one epitaxial loayer of the electronic material on described resilient coating, at least one epitaxial loayer of described electronic material is selected from the group that includes but not limited to based on following: indirect gap semiconductor, for example Si, Ge, GaP; Direct gap semiconductor, for example CdTe, CuInGaSe 2(CIGS), GaAs, AlGaAs, GaInP and AlInP; Multiband semiconductor is for example as Zn 1-yMn yO xTe 1-xThe II-O-VI material, and III-N-V multiband semiconductor, for example GaN xAs 1-x-yP y, with and the combination.At least one epitaxial loayer of described electronic material comprises that being used in the semiconductor layer obtains trace doped dose of other materials of needed N-shaped or p-type semiconductor property.
In preferred embodiment of the present invention, described semiconductor layer in the goods is the compound semiconductor that mainly is comprised of two or more elements not of the same clan from the periodic table of elements, comprise for compd A lN, AlP, AlAs, GaN, GaP, GaAs, InP, InAs, InSb, AlInGaP, AlGaAs, III-th family (the B of InGaN etc., Al, Ga, In) and (N of V family, P, As, Sb, Bi) compound, and (the Zn of II family, Cd, Hg) and (O of VI family, S, Se, Te) compound, for example ZnS, ZnSe, ZnTe, CdTe, HgTe, CdHgTe etc.Except above binary compound, also comprise ternary compound (three kinds of elements, for example InGaAs) and quaternary compound (four kinds of elements, for example InGaAsP).
In preferred embodiment of the present invention, described semiconductor layer in the goods comprises elemental semiconductor or the alloy of the element in the identical family, for example SiC and SiGe, or comprise the compound semiconductor of element of IB family, group III A and the VIA family of the periodic table of elements, for example alloy of copper, indium, gallium, aluminium, selenium and sulphur.
In preferred embodiment of the present invention, there is the substrate (textured substrate) of texture to have the grain size greater than 100 microns.
The semiconductor device according to the invention goods also can be included at least one resilient coating on the described substrate, and this at least one resilient coating is selected from the group that comprises metal, alloy, nitride, boride, oxide, fluoride, carbide, silicide or its combination.
In preferred embodiment of the present invention, described resilient coating has the rock salt crystal structure (rock-salt crystal structure) that is selected from the crystal structure that comprises following group: formula AN or AO, and wherein A is that metal and N and O are corresponding to nitrogen and oxygen; Formula ABO 3Perovskite crystal structure, wherein A and B are that metal and O are oxygen; Formula A 2B 2O 7The pyrochlore crystal structure, wherein A and B are that metal and O are oxygen; And formula A 2O 3The bixbyite crystal structure, wherein A is that metal and O are oxygen.
In preferred embodiment of the present invention, described resilient coating has and is selected from the chemical formula that comprises following group: have formula A xB 1-xO and A xB 1-xThe rock salt crystal structure of the mixing of N, wherein A is different metals with B; The oxynitride that mixes, for example A xB 1-xN yO 1-y, wherein A is different metals with B; The bixbyite structure of mixing, for example (A xB 1-x) 2O 3, wherein A is different metals with B; The perovskite that mixes, for example (A xA ' 1-x) BO 3, (A xA ' 1-x) (B yB ' 1-y) O 3, wherein A, A ', B and B ' are different metals; And the pyrochlore that mixes, for example (A xA ' 1-x) 2B 2O 7, (A xA ' 1-x) 2(B yB ' 1-y) 2O 7, wherein A, A ', B and B ' are different metals.
In another preferred embodiment of the present invention, resilient coating can be to be selected from the oxide buffer layer that comprises following group: γ-Al 2O 3(Al 2O 3Cube form); Perovskite is such as but not limited to SrTiO 3, (Sr, Nb) TiO 3, BaTiO 3, (Ba, Ca) TiO 3, LaMnO 3, LaAlO 3, adulterated with Ca and Ti ore, for example (La, Sr) MnO 3, (La, Ca) MnO 3Layering perovskite, for example Bi 4Ti 3O 12Pyrochlore is such as but not limited to La 2Zr 2O 7, Ca 2Zr 2O 7, Gd 2Zr 2O 7Fluorite (flourite), for example Y 2O 3, YSZ; Rock salt oxide (rock-salt oxide) is such as but not limited to MgO; Spinelle is such as but not limited to MgAl 2O 4
In another preferred embodiment, the buffer stack of formation electronic device is selected from from comprising multilayer, the Y of a cube nitride layer, MgO/ cube nitride 2O 3The multilayer of/YSZ/ cube of nitride, Y 2O 3Multilayer, the Y of the multilayer of/YSZ/MgO/ cube of nitride, cubic oxide thing layer, MgO/ cubic oxide thing 2O 3Multilayer and the Y of/YSZ/ cubic oxide thing 2O 3The resilient coating structure of the group selection of the multilayer of/YSZ/MgO/ cubic oxide thing.
In another preferred embodiment, the buffer stack of formation electronic device is selected from from the multilayer, the Y that comprise TiN layer, MgO/TiN 2O 3The multilayer of/YSZ/TiN, Y 2O 3The multilayer of/YSZ/MgO/TiN, cubic oxide thing layer, MgO/ γ-Al 2O 3Multilayer, Y 2O 3/ YSZ/ γ-Al 2O 3Multilayer and Y 2O 3/ YSZ/MgO/ γ-Al 2O 3The resilient coating structure of group selection of multilayer.
Resilient coating can be the silicide resilient coating or with the intermetallic alloy of germanium, described silicide resilient coating or with the intermetallic alloy of germanium corresponding to chemical formula MSi or MSi are arranged 2, MSi 3, MGe or MGe 2, MGe 3Layer, wherein M is metal, such as but not limited to Ni, Cu, Fe, Ir and Co.
Resilient coating also can be the carbide lamella corresponding to cube form of SiC.
In preferred embodiments, the top resilient coating conducts electricity at least.
In still another preferred embodiment, resilient coating can be " graduate resilient coating ", includes the multi-buffer layer of different lattice parameters, so that good Lattice Matching to be provided to semiconductor layer.
In preferred embodiments, electronic device also is included in the semiconductor module flaggy between resilient coating and the semiconductor device layer, so that good Lattice Matching to be provided to semiconductor device layer.
The semiconductor module flaggy can be " graduate semiconductor die " layer with multilayer of different lattice parameters, so that good Lattice Matching to be provided to semiconductor device layer.
In preferred embodiments, the substrate that consists of electronic device have so that two crystallographic axis of other of all crystal grains in the face of substrate also to have less than the texture of the FWHM of the 10 degree crystallography texture as feature.
In preferred embodiments, at least one resilient coating that consists of electronic device have so that two crystallographic axis of other of all crystal grains in the face of substrate also to have less than the texture of the FWHM of the 10 degree crystallography texture as feature.
In preferred embodiments, the described electronic device layer that consists of electronic device have so that two crystallographic axis of other of all crystal grains in the face of substrate to have less than the texture of the FWHM of the 10 degree crystallography texture as feature.
In preferred embodiments, substrate is selected from the group that comprises Cu, Ni, Al, Mo, Nb and Fe and alloy thereof.
In preferred embodiments, substrate is the Ni base alloy that the W content in the scope of 3-9at%W (atomic percentage W) is arranged.
In preferred embodiments, substrate is the MULTILAYER COMPOSITE substrate, and only top layer has the crystallography arrangement in the MULTILAYER COMPOSITE substrate, and the crystallographic axis of all crystal grains in this layer is relative to each other arranged in 10 degree in all directions.
In preferred embodiments, substrate is the MULTILAYER COMPOSITE substrate, and only top layer and bottom have crystallography and arrange in the MULTILAYER COMPOSITE substrate, and the crystallographic axis of all crystal grains in these layers is in the relative to each other arrangement in 10 degree of all directions.
In preferred embodiments, electronic device is the photovoltaic device that comprises that at least one pn that is parallel to substrate surface ties.
In still another preferred embodiment, electronic device is the photovoltaic device that includes the multijunction cell of at least two and preferred three pn knots that are parallel to substrate surface.
In preferred embodiments, the photovoltaic conversion efficiency of described device layer is greater than 13% and be preferably greater than 15%.
In preferred embodiments, the nano dot of the arrangement that is comprised of another different from device layer on diameter crystallizations of described electronic device layer forms.
In still another preferred embodiment, 80% of nano dot with the arrangement in 60 degree of the normal of device layer.
Can be used for being selected from according to electronic device of the present invention comprise photovoltaic device, flat-panel monitor, thermo-photovoltaic device, ferro-electric device, LED device, computer hard disc driver device, based on the device of magnetic resistance, the application of group of device, nonvolatile memory device, dielectric devices, thermoelectric device and quantum dot laser spare based on luminescence generated by light.
In preferred embodiments, electronic device has the area greater than 50 square inches.Again further in the preferred embodiment, electronic device has the area greater than 113 square inches.
In preferred embodiments, can comprise at least a device that comprises following group that is selected from according to electronic device of the present invention: Double-end device, for example diode; Three termination devices, for example transistor, thyristor or rectifier; And multiterminal head device, for example microprocessor, random access memory, read-only memory or charge coupled device (charge-coupled device).
The accompanying drawing summary
By the repeatedly reading to following detailed description and accompanying drawing, with realize to the present invention with and the understanding more completely of feature and benefit, in the accompanying drawings:
Fig. 1 shows the Utopian schematic diagram with cross-sectional form according to the various embodiments of sandwich construction of the present invention.Fig. 1 shows the most basic structure, namely all directions have have less than 10 ° half width (FWHM) or inlay 100}＜100〉and primary recrystallization texture or the metal or alloy substrate of the flexibility of secondary recrystallization texture; Single or multi-buffer layer, wherein at least the top resilient coating have 100}＜100〉or 45 ° of rotations 100}＜100〉texture; Selectable epitaxial semiconductor template layer or graduate semiconductor module flaggy are to provide improved Lattice Matching to the device layer above resilient coating; And at last, epitaxial semiconductor device layers, it is simple layer or multilayer, and is selected from the group that includes but not limited to based on the layer of indirect gap semiconductor, direct gap semiconductor and multi-band gap semiconductor (multibandgap semiconductor).
Fig. 2 shows the Utopian schematic diagram with cross-sectional form according to the electronic device of the pn knot that texture is arranged that contains extension according to the present invention, and wherein the pn knot is parallel to substrate surface.Fig. 2 shows and comprises following device: the metal or alloy substrate that texture is arranged on the flexibility similar to substrate shown in Figure 1, crystalline, the crystallography; Also on the crystallography similar to resilient coating shown in Figure 1 the single of texture or multi-buffer layer are arranged; The semiconductor module flaggy of selectable extension or graduate semiconductor module flaggy are to provide improved Lattice Matching to the device layer above resilient coating; P-type and the N-shaped semiconductor layer of the extension that texture is arranged on top resilient coating or selectable semiconductor module flaggy; Transparent conductor layer and the antireflection coating that metal grid lines is arranged.A purposes of such device as shown in Figure 2 is for solar power generation.
Fig. 3 A shows simple active-matrix Organic Light Emitting Diode (active-matrix organic light emitting diode) idealized schematic diagram (AMOLED).Fig. 3 B shows the Utopian schematic diagram that contains the multijunction cell of three batteries according to of the present invention.In typical multijunction cell, there is each battery of different band gap to be stacked on each other top.Each battery is so that the mode that daylight at first is radiated on the material with maximum band gap is stacking.Absorbed photon is not transferred to second battery in first battery, and then the higher part of the energy of the solar radiation of second battery adsorbing residual keeps seeing through to the lower photon of energy simultaneously.These selectivity absorption processes continue, until arrive the final battery with minimum band gap.Substantially, multijunction device is the stacking of order that successively decrease with band gap (Eg) of each single junction cell.Top battery is caught high-energy photon, and remaining photon transfer is gone down to be absorbed by the lower battery of band gap.
Fig. 4 shows the cross section of some multijunction cell of having reported in the literature.Whole conversion efficiencies near 40% expection that schematic diagram has illustrated the part of being caught by multijunction cell in the spectrum of the sun and these batteries.Fig. 4 A shows three junction batteries of GaInP (1.8eV)/GaAs (1.4eV)/Ge (0.7eV); Fig. 4 B shows three junction batteries of GaInP (1.8eV)/GaInAs (1.25eV)/Ge (0.7eV); And Fig. 4 C shows four junction batteries of GaInP (1.8eV)/GaAs (1.4eV)/GaInAs (1.25eV)/Ge (0.7eV).
Fig. 5 shows the Utopian schematic diagram with cross-sectional form according to many knots electronic device of the pn knot that contains two extensions that texture arranged of the present invention, and wherein the pn knot is parallel to substrate surface.Fig. 5 shows and comprises following device: the metal or alloy substrate that texture is arranged on similar flexibility, crystalline, the crystallography of the substrate of describing to Fig. 1 and 2; The single of texture or multi-buffer layer are arranged on the crystallography; The semiconductor layer of selectable extension or on forming graduate (compositionally graded) template layer; The bottom battery that comprises the extension that texture is arranged of pn knot; Tunnel junction; The top battery that comprises the pn knot; Transparent conductor layer; Antireflection coating and metal grid lines.A purposes of device shown in Figure 5 is for solar power generation.
Fig. 6 shows the Utopian schematic diagram with cross-sectional form that contains many knots electronic device of three pn knots that texture arranged according to of the present invention, and wherein the pn knot is parallel to substrate surface.Fig. 6 shows and comprises following device: the metal or alloy substrate that texture is arranged on similar flexibility, crystalline, the crystallography of the substrate of describing to Fig. 1 and 2; The single of texture or multi-buffer layer are arranged on the crystallography; The semiconductor layer of selectable extension or on forming graduate template layer; The bottom battery that comprises the extension that texture is arranged of pn knot; Tunnel junction; The middle cell that comprises the pn knot; Tunnel junction; The top battery that comprises the pn knot; Transparent conductor layer; Antireflection coating and metal grid lines.A purposes of device shown in Figure 6 is for solar power generation.
Fig. 7 shows the Utopian schematic diagram with cross-sectional form such as the electronic device of describing among Fig. 1-6, and wherein resilient coating is stacking comprises a lot of thin resilient coatings, to provide good Lattice Matching to the semiconductor layer of growing in top buffering template." graduate buffering approach on forming " for the defect concentration that provides good Lattice Matching to minimize semiconductor layer to semiconductor is provided for this.
Fig. 8 shows the Utopian schematic diagram with cross-sectional form such as the electronic device of describing among Fig. 1-7, wherein the semiconductor module flaggy comprises a lot of thin layers, with to semiconductor device layer or comprise pn knot and the first battery of growth above the semiconductor module flaggy provides good Lattice Matching." graduate semiconductor approach " for the defect concentration that provides good Lattice Matching further to minimize semiconductor device layer to semiconductor device layer is provided for this.
Fig. 9 shows the Utopian schematic diagram with cross-sectional form such as the electronic device of describing among Fig. 1-8, and wherein resilient coating is stacking comprises a lot of thin resilient coatings, to provide good Lattice Matching to the semiconductor module flaggy of growing in top buffering template.In addition, the semiconductor module flaggy comprises a lot of thin layers, with to semiconductor device layer or comprise pn knot and the first battery of growth above the semiconductor module flaggy provides good Lattice Matching.Combination for " the graduate buffering approach " and " graduate semiconductor approach " of the defect concentration that provides good Lattice Matching to minimize this layer to semiconductor device layer is provided for this.
Figure 10 show 100}＜100〉and texture flexibility the NiW alloy, at the Si semiconductor layer that texture is arranged above the alloy with between the Utopian schematic diagram with cross-sectional form of the resilient coating of the extension that texture is arranged of the TiN between them.
Figure 11 show 100}＜100〉(111) X ray utmost point figure of the sample of epitaxially grown TiN on the Ni-3at%W substrate of texture.Only seen the peak of equivalence on four crystallography, this show by force 100}＜100〉be orientated.Use
Figure BPA00001232177800111
The half width (FWHM) of texture and use X-ray diffraction also represent at figure by the half width (FWHM) of the outer texture of face of (200) ω scanning survey in the face of scanning survey.
Figure 12 shows the low multiplication factor TEM cross section of the sample of Ni-3at%W/TiN/Si.In microphoto, can clearly distinguish whole three layers.
Figure 13 shows from obtaining with 0.6 micron spacing on hexagonal mesh and the orientation image microphoto of the electron backscattered Kikuchi diffraction pattern generation of index (indexing).The tonal gradation shade that provides among Figure 13 A (grey scale shading) expression has the district that is connected to each other less than the misorientation of 2 degree.The tonal gradation shadow representation that provides among Figure 13 B has the district that is connected to each other less than the misorientation of 3 degree.Be clear that the large single crystal that the silicon layer representative has some to inlay.The particle of the crowned of seeing in the image the reason there is, film is to use the pulse laser ablation technology growth, knownly can form so granular feature in this technology.Make deposited by electron beam evaporation or chemical vapour deposition (CVD) come growing film will obtain the very high film of smoothness.
Figure 14 shows the epitaxially grown high-definition picture of showing of Si/TiN interface.
Figure 15 shows along＜100〉the high-resolution transmission electron microscope photo on plane of silicon layer of extension.Insertion illustrates fast Fourier transform (FFT) pattern of photo.
Figure 16 show from the plane graph of the transmission electron microscopy sample of Si/TiN/NiW＜100〉crystal zone axis selected area electron diffraction pattern, show the arrangement of the extension of Si{220}, TiN{200} and Ni{200} diffraction spot.
Figure 17 also show from the plane graph of the transmission electron microscopy sample of Si/TiN/NiW＜100〉crystal zone axis selected area electron diffraction pattern, show the arrangement of the extension of Si{220}, TiN{200} and Ni{200} diffraction spot.In this case, can obtain the Qu Gengda of diffraction pattern.
Figure 18 shows the Utopian schematic diagram with cross-sectional form according to the various embodiments of sandwich construction of the present invention.That Figure 18 A shows is flexible, crystalline 100}＜100〉the metal or alloy substrate of texture; Crystallography above substrate has the TiN resilient coating of the extension of texture, and the Si of extension or other semiconductor device or template layer.That Figure 18 B shows is flexible, crystalline 100}＜100〉the metal or alloy substrate of texture; Crystallography above substrate has the MgO resilient coating of the extension of texture; Crystallography above the MgO layer has the TiN resilient coating of the extension of texture; And the Si of extension or other semiconductor device or template layer.That Figure 18 C shows is flexible, crystalline 100}＜100〉the metal or alloy substrate of texture; Crystallography above substrate has the Y of the extension of texture 2O 3Resilient coating; At Y 2O 3The YSZ resilient coating that the extension of texture is arranged on the crystallography of layer top; Crystallography above the YSZ layer has the TiN resilient coating of the extension of texture; And the Si of extension or other semiconductor device or template layer.That Figure 18 D shows is flexible, crystalline 100}＜100〉the metal or alloy substrate of texture; Crystallography above substrate has the Y of the extension of texture 2O 3Resilient coating; At Y 2O 3The YSZ resilient coating that the extension of texture is arranged on the crystallography of layer top; Crystallography above the YSZ layer has the MgO resilient coating of the extension of texture; Crystallography above the MgO layer has the TiN resilient coating of the extension of texture; And the Si of extension or other semiconductor device or template layer.
Figure 19 shows the Utopian schematic diagram with cross-sectional form according to the various embodiments of sandwich construction of the present invention.That Figure 19 A shows is flexible, crystalline 100}＜100〉the metal or alloy substrate of texture; At least one extension above substrate and graduate cube of nitride resilient coating selectively, and the Si of extension or other semiconductor device or template layer.That Figure 19 B shows is flexible, crystalline 100}＜100〉the metal or alloy substrate of texture; The MgO resilient coating of the extension above substrate; At least one extension above the MgO layer and graduate cube of nitride resilient coating selectively; And the Si of extension or other semiconductor device or template layer.That Figure 19 C shows is flexible, crystalline 100}＜100〉the metal or alloy substrate of texture; The Y of the extension above substrate 2O 3Resilient coating; At Y 2O 3The YSZ resilient coating of the extension of layer top; At least one extension above the YSZ layer and graduate cube of nitride resilient coating selectively; And the Si of extension or other semiconductor device or template layer.That Figure 19 D shows is flexible, crystalline 100}＜100〉the metal or alloy substrate of texture; The Y of the extension above substrate 2O 3Resilient coating; At Y 2O 3The YSZ resilient coating of the extension of layer top; The MgO resilient coating of the extension above the YSZ layer; At least one extension above the MgO layer and graduate cube of nitride resilient coating selectively; And the Si of extension or other semiconductor device or template layer.
Figure 20 shows the Utopian schematic diagram with cross-sectional form according to the various embodiments of sandwich construction of the present invention.That Figure 20 A shows is flexible, crystalline 100}＜100〉the metal or alloy substrate of texture; γ-the Al of the extension above substrate 2O 3Resilient coating, and the Si of extension or other semiconductor device or template layer.That Figure 20 B shows is flexible, crystalline 100}＜100〉the metal or alloy substrate of texture; The MgO resilient coating of the extension above substrate; γ-the Al of the extension above the MgO layer 2O 3Resilient coating; And the Si of extension or other semiconductor device or template layer.That Figure 20 C shows is flexible, crystalline 100}＜100〉the metal or alloy substrate of texture; The Y of the extension above substrate 2O 3Resilient coating; At Y 2O 3The YSZ resilient coating of the extension of layer top; γ-the Al of the extension above the YSZ layer 2O 3Resilient coating; And the Si of extension or other semiconductor device or template layer.That Figure 20 D shows is flexible, crystalline 100}＜100〉the metal or alloy substrate of texture; The Y of the extension above substrate 2O 3Resilient coating; At Y 2O 3The YSZ resilient coating of the extension of layer top; The MgO resilient coating of the extension above the YSZ layer; γ-the Al of the extension above the MgO layer 2O 3Resilient coating; And the Si of extension or other semiconductor device or template layer.
Figure 21 shows the Utopian schematic diagram with cross-sectional form according to the various embodiments of sandwich construction of the present invention.That Figure 21 A shows is flexible, crystalline 100}＜100〉the metal or alloy substrate of texture; At least one extension above substrate and graduate cubic oxide thing resilient coating selectively, and the Si of extension or other semiconductor device or template layer.That Figure 21 B shows is flexible, crystalline 100}＜100〉the metal or alloy substrate of texture; The MgO resilient coating of the extension above substrate; At least one extension above the MgO layer and graduate cubic oxide thing resilient coating selectively; And the Si of extension or other semiconductor device or template layer.That Figure 21 C shows is flexible, crystalline 100}＜100〉the metal or alloy substrate of texture; The Y of the extension above substrate 2O 3Resilient coating; At Y 2O 3The YSZ resilient coating of the extension of layer top; At least one extension above the YSZ layer and graduate cubic oxide thing resilient coating selectively; And the Si of extension or other semiconductor device or template layer.That Figure 21 D shows is flexible, crystalline 100}＜100〉the metal or alloy substrate of texture; The Y of the extension above substrate 2O 3Resilient coating; At Y 2O 3The YSZ resilient coating of the extension of layer top; The MgO resilient coating of the extension above the YSZ layer; At least one extension above the MgO layer and graduate cubic oxide thing resilient coating selectively; And the Si of extension or other semiconductor device or template layer.
Figure 22 shows the Utopian schematic diagram with cross-sectional form that contains the electronic device of the semiconductor device that texture is arranged on the crystallography according to of the present invention.That device comprises is flexible 100〉＜100〉texture metal/alloy Cu, Mo, Nb, Al, Fe or Ni base alloy substrate; The resilient coating that texture is arranged on the crystallography; The semiconductor module flaggy that texture is arranged on the selectable crystallography; The epitaxial loayer that texture is arranged on the crystallography of silicon and/or germanium; The GaAs layer that the extension of texture is arranged on the crystallography; The InGaP layer that the extension of texture is arranged on the crystallography; Transparent conductor layer, and selectable antireflection coating and metal grid lines.This representative form forms the general basis of device.People it is contemplated that with the other semiconductor layer of this multiple-level stack or knot and/or resilient coating.A purposes of such device is for solar power generation.
Figure 23 A shows the Utopian schematic diagram with cross-sectional form of compound substrate, described compound substrate contains and has or not bottom crystallography texture or that do not arrange, and have 100}＜100 top surface texture or that arrange, so that all crystal grains in this layer is arranged in 10 degree in all directions.Figure 23 B shows the Utopian schematic diagram with cross-sectional form of compound substrate, described compound substrate contains and has or not center crystallography texture or that do not arrange, and have 100}＜100 top surface and basal surface texture or that arrange, so that all crystal grains in this layer is arranged in 10 degree in all directions.
Figure 24 shows the thick YBa of 0.2 μ m of the self-assembled nanometer point of epitaxially grown BZO on the substrate of the biaxial texture of the buffering that extension is arranged 2Cu 3O x(YBCO) cross-sectional transmission electron microscope (TEM) image of layer.In the YBCO layer, can see BaZrO 3The post of self-assembled nanometer point (BZO).The ab face that post represents perpendicular to the parallel lattice fringe by in the YBCO layer of YBCO, and be parallel to the c-axis of YBCO.Black arrow among the figure shows some the position in the post of self-assembled nanometer point of BZO.
Figure 25 shows the Utopian schematic diagram with cross-sectional form of the nano dot self assembly in the epitaxially grown device layer or orderly on substrate.In this case, the ordered arrangement of nano dot occurs, so that form the vertical column of nano dot.
Figure 26 shows the Utopian schematic diagram with cross-sectional form of the nano dot self assembly in the epitaxially grown device layer or orderly on substrate.In this case, the ordered arrangement of nano dot can occur in some way, thereby form the post of the inclination of nano dot.
Figure 27 shows the Utopian schematic diagram of the nano dot self assembly in the epitaxially grown device layer or orderly on substrate.In this case, the ordered arrangement of nano dot is vertical, yet nano dot has as directed bending to self.
The detailed description of preferred embodiment
The present invention relates to have on large-area, flexible, the crystallography manufacturing of electronic device texture, that have high performance based semiconductor.The present invention makes also that the use reel-to-reel deposition (reel-to-reel deposition) of such device carries out creates possibility continuously.
Fig. 1 shows the Utopian schematic diagram with cross-sectional form according to the various embodiments of sandwich construction of the present invention.Fig. 1 shows the most basic structure, and the metal or alloy substrate that has less than the flexibility of the outer texture of macroscopical face of [100] or [110] of 10 ° half width (FWHM) is namely arranged; Having above this metal or alloy substrate has the single or multi-buffer layer less than texture outside the face of [100] or [110] of 10 ° FWHM; Selectable, epitaxial semiconductor template layer or graduate semiconductor module flaggy are to provide improved Lattice Matching to the device layer above resilient coating; And at last, epitaxial semiconductor device layers, it is simple layer or multilayer, and is selected from the group that includes but not limited to based on the group of indirect gap semiconductor, direct gap semiconductor and multi-band gap semiconductor.Fig. 1 comprises: device architecture, and it includes metal or alloy substrate flexibility, crystalline that has less than the outer texture of face of 10 ° FWHM [100] or [110], and wherein other two vertical crystallographic axis of all crystal grains are arranged with 10 ° half width; Single or multi-buffer layer above substrate, it has the outer texture of face that has less than [100] or [110] of 10 ° FWHM, and wherein other two vertical crystallographic axis of all crystal grains with 10 ° with interior arrangement; Selectable epitaxial semiconductor template layer above resilient coating or graduate semiconductor module flaggy are to provide improved Lattice Matching to device layer; And epitaxial semiconductor device layers, it is simple layer or multilayer, and is selected from the group that includes but not limited to based on the group of indirect gap semiconductor, direct gap semiconductor and multi-band gap semiconductor.
[100] or the semiconductor of [110] texture for realizing that high device performance is useful.The metal or alloy template of single shaft texture can be passed through heat engine tool process technology, and for example rolling and annealing, compacting or punching press and annealing, forging and annealing, drawing and annealing and crowded the forging and annealing are made.These distortion and the combination of annealing steps also can be used for having sharpness and the clear and definite outer single shaft texture of face and the large metal or alloy substrate of mean grain size with routine experiment manufacturing.For all heat engine tool processing approach, the crystallography texture that we point out in the present invention or present patent application be annealing recrystallization texture and Be notDeformation texture." deformation texture " is the crystallography texture that develops in metal and alloy when mechanical deformation, and the process of distortion obtains the crystal grain of plastic deformation.Deformation texture also can have very large sharpness and can be twin shaft, and has some the specific orientation in the cubic material.Details about the typical deformation texture that can be produced by mechanical deformation in metal and the alloy can find in following textbook: " Structure of Metals (structure of metal) ", author Charles Barrett and T.B.Massalski, the third edition, Pergamon publishing house, 1980, the 541-566 pages or leaves; " Recrystallisation and related annealing phenomena (recrystallization and relevant annealing phenomenon) ", author FJ Humphreys, M Hatherly are published by Elsevier, and 2004, the 43-54 page or leaf.Recrystallization is a kind of strained crystal grain by one group of new nucleation and growth until the process that the undeformed crystal grain that initial crystal grain all has been consumed replaces.The detailed definition of recrystallization can obtain from the document of this area, or from the network address of online free encyclopaedical Wikipedia Http:// en.wikipedia.orq/wiki/Recrystallization (metallurgy)Obtain.The crystallography texture of the process of process recrystallization is called as recrystallization texture.About how can find in following book by the details of heat engine tool processing generation annealing or recrystallization texture: exercise question is " Recrystallisation and related annealing phenomena (recrystallization and relevant annealing phenomenon) ", author FJ Humphreys, M Hatherly, published by Elsevier, 2004, the 327-415 page or leaf; " Structure of Metals (structure of metal) ", author Charles Barrett and T.B.Massalski, the third edition, Pergamon publishing house, 1980, the 568-582 pages or leaves; All lists of references of pointing out in the book are also incorporated into as relevant references.Details about the mode that forms single shaft texture, biaxial texture and three axle recrystallization textures can find in above-mentioned book.Especially, about cube, the details that forms the mode of [100] or [110] recrystallization texture in the metal of the center of area and body-centered and the alloy at length discusses in book.In the present invention, have on the crystallography texture and metal and the alloy of recrystallization are concerned about especially fully.This is because the surface of metal that be rolled and that texture is arranged and alloy is not easy to be used to the epitaxial growth of other materials.In addition, common deformation texture does not have the crystalline orientation for the expectation of being combined with semiconductor by suitable resilient coating.Resilient coating is for the stay in place form that provides chemical barrier layer and semiconductor layer to grow thereon.Need chemical barrier layer to prevent the diffusion of element from metal/alloy or ceramic substrate to semiconductor layer.Resilient coating can be selected from the group that comprises metal, alloy, nitride, boride, oxide, fluoride, carbide, silicide or its combination.Resilient coating can be the nitride resilient coating corresponding to the composition of MN, and wherein N is that nitrogen and M are selected from the group that comprises Ti, Ce, Y, Zr, Hf, V, Nb, Nd, La and Al and combination thereof.Resilient coating can be to be selected from the oxide buffer layer that comprises following group: γ-Al 2O 3(Al 2O 3Cube form); Perovskite is such as but not limited to SrTiO 3, (Sr, Nb) TiO 3, BaTiO 3, (Ba, Ca) TiO 3, LaMnO 3, LaAlO 3, the perovskite that mixes, for example (La, Sr) MnO 3, (La, Ca) MnO 3Layering perovskite, for example Bi 4Ti 3O 12Pyrochlore is such as but not limited to La 2Zr 2O 7, Ca 2Zr 2O 7, Gd 2Zr 2O 7Fluorite, for example Y 2O 3, YSZ; The rock salt oxide is such as but not limited to MgO; Spinelle is such as but not limited to MgAl 2O 4Resilient coating also can include chemical formula MN xO yNitride and the hopcalite of (1＜x, y＞0), wherein N is that nitrogen and O are oxygen, and M is selected from the group that comprises Ti, Ce, Y, Zr, Hf, V, Nb, Nd, La and Al and combination thereof.The stay in place form that need to comprise resilient coating obtaining the good Lattice Matching with the semiconductor layer of growing, thereby minimizes the defect concentration in the semiconductor layer.
In some cases, before semiconductor device layer, use other semiconductor module flaggy.This semiconductor module flaggy also is used for providing better Lattice Matching to semiconductor device layer.Another function of top resilient coating provides stable, level and smooth and fine and close surface, so that semiconductor layer is grown on this surface.Buffer-layer surface can be regulated with chemical means or hot means.In Chemical Regulation, use the surface with one or more chemical substance modification resilient coatings of gaseous state or solution form.In thermal conditioning, resilient coating is heated to the high temperature that surface reconstruction occurs.Surface modulation also can Application standard and full-fledged technology, be that plasma etching and reactive ion etching are finished and (seen, for example, Siliconprocessing for the VSLI Era (silicon in very lagre scale integrated circuit (VLSIC) epoch is processed), the 1st volume, S.Wolf and R.N.Tanber edit, the 539-574 page or leaf, Lattice publishing house, Sunset Park, CA, 1986).
The semiconductor device layer of [100] described in Fig. 1 or [110] texture can be selected from the group that includes but not limited to based on those following semiconductor device layer: indirect gap semiconductor, for example Si, Ge, GaP; Direct gap semiconductor, for example CdTe, CuInGaSe 2(CIGS), GaAs, AlGaAs, GaInP and AlInP; Multiband semiconductor is for example as Zn 1-yMn yO xTe 1-xThe II-O-VI material, and III-N-V multiband semiconductor, for example GaN xAs 1-x-yP y, with and the combination.This comprises in the semiconductor layer trace doped dose of the other materials that is used for obtaining needed N-shaped or p-type semiconductive character." directly ", " indirectly " and " multiband " semi-conductive definition can obtain from the document of this area, or from online free encyclopaedical Wikipedia ( Http:// en.wikipedia.org/wiki/Main Page) obtain.For example, as stating among the Wikipedia, the definition of direct gap semiconductor and indirect gap semiconductor is, " in semiconductor physics, direct band gap means in the momentum space minimum value of conduction band and is located immediately at above valence band peaked.In direct gap semiconductor, can directly with in the hole at valence band maximum place be combined at the electronics at conduction band minimum place, keep simultaneously momentum.The compound energy of crossing over band gap will be with the form emission of the photon of light.Radiation recombination that Here it is is also referred to as spontaneous emission.In the indirect gap semiconductor such as crystalline silicon, conduction band minimum is not identical with the peaked momentum of valence band, so the direct transition of leap band gap does not keep momentum and is forbidden.Compoundly occur in the third party who allows the conservation of momentum, for example phonon or crystal defect are during as medium.These compound will often releases as phonon but not the band-gap energy of photon, thereby and utilizing emitted light not.Therefore, launch very poor efficiency and faint from the light of indirect semiconductor.Has the photoemissive new technology of improving from indirect semiconductor.Referring to indirect band gap, to obtain explanation.The main example of direct gap semiconductor is GaAs, a kind of material that usually uses in laser diode.”
In preferred embodiment of the present invention, described semiconductor layer in the goods is the compound semiconductor that mainly is comprised of two or more elements not of the same clan from the periodic table of elements, comprise: III-th family (B, Al, Ga, In) and (N of V family, P, As, Sb, Bi) compound, compd A lN for example, AlP, AlAs, GaN, GaP, GaAs, InP, InAs, InSb, AlInGaP, AlGaAs, InGaN etc., and (the Zn of II family, Cd, Hg) and (O of VI family, S, Se, Te) compound, for example ZnS, ZnSe, ZnTe, CdTe, HgTe, CdHgTe etc.Except above binary compound, also comprise ternary compound (three kinds of elements, for example InGaAs) and quaternary compound (four kinds of elements, for example InGaAsP).
Semiconductor layer in the goods also can comprise elemental semiconductor or the alloy of the element in the identical family, for example SiC and SiGe, or comprise the compound semiconductor of element of IB family, group III A and the VIA family of the periodic table of elements, for example alloy of copper, indium, gallium, aluminium, selenium and sulphur.
Fig. 2 shows the Utopian schematic diagram with cross-sectional form that contains the electronic device of pn knot extension, that texture is arranged according to of the present invention, and wherein the pn knot is parallel to substrate surface.Fig. 2 shows and comprises following device: the metal or alloy substrate that texture is arranged on the flexibility similar to substrate shown in Figure 1, crystalline, the crystallography; Also on the crystallography similar to resilient coating shown in Figure 1 the single of texture or multi-buffer layer are arranged; The semiconductor module flaggy of selectable extension or graduate semiconductor module flaggy are to provide improved Lattice Matching to the device layer above resilient coating; On top resilient coating or selectable semiconductor module flaggy, p-type texture, extension and N-shaped semiconductor layer arranged; Transparent conductor layer; With the antireflection coating that metal grid lines is arranged.The p-type semiconductor obtains by implementing the doping process, and in the doping process, the atom of some type is incorporated in the semiconductor, to improve the freely quantity of (in this case, positive) charge carrier.When dopant material was added into, dopant material was taken away (weakly-bound) outer-shell electron that (acceptance) weak beam is tied up from semiconductor atom.Such dopant is also referred to as acceptor material (acceptor material), and the semiconductor atom that has lost electronics is called as the hole.The purpose that p-type is mixed is to produce abundant hole.For the situation of silicon, replace entering in the lattice with triad (usually from the group III A of the periodic table of elements, for example boron or aluminium).The result is that from normal four covalent bonds for silicon crystal lattice loses an electronics.Thereby dopant atom can be accepted electronics so that the 4th key is complete from the covalent bond of the atom that adjoins.Such dopant is called as acceptor.Dopant atom is accepted electronics, causes from the loss of half of a key of the atom that adjoins, and causes the formation in " hole ".Each hole is associated with near the dopant ion of negative electrical charge, and semiconductor keeps electric neutrality as a whole.Yet in case each hole forms in dot matrix, a proton in the atom of the position in described hole will be " exposure " so, and or else can be neutralized by electronics.Therefore, a certain amount of positive charge is played in the hole.When having added the acceptor atom of enough large quantity, the quantity in hole surpasses greatly by the quantity of the electronics of thermal excitation.Therefore, the hole is the carrier that occupies the majority, and electronics is the carrier that occupies the minority in the p-type material.The N-shaped semiconductor obtains by implementing the doping process, namely by add the impurity of pentad (valence-five element) to tetravalence semiconductor (valence-four semiconductor), to increase freely the quantity of (bearing in this case) charge carrier.When dopant material was added into, dopant material was abandoned the outer-shell electron that (providing) weak beam is tied up to semiconductor atom.Such dopant is also referred to as donor material (donor material), because it has abandoned in its electronics some.The purpose that N-shaped mixes be in material, produce abundant movably or " carrier " electronics.In order to help to understand the mode that realizes that N-shaped mixes, consider the situation of silicon (Si).The Si atom has four valence electrons, and wherein in each and four the Si atoms that adjoin forms covalent bond.If the atom of five valence electrons is arranged, for example phosphorus (P), arsenic (As) or antimony (Sb) are incorporated into lattice and replace the Si atom, and then this atom will have four covalent bonds and a free electronics.This extra electronics only faintly is combined with atom, and can easily be excited in the conduction band.At normal temperature, all such electronics all are excited in the conduction band basically.Since these electronics excite the formation that does not cause the hole, so the quantity of electronics far exceeds the quantity in hole in such material.In this case, electronics is the carrier that occupies the majority, and the hole is the carrier that occupies the minority.Because having extra electronics, five electronic atoms can " provide ", so they are known as donor atom.Therefore, can make p-type semiconductor and N-shaped semiconductor by the suitable doping of element.Device among Fig. 2 relates to p-n junction, and wherein knot is parallel to substrate surface.The combination of p-type layer and N-shaped layer is called as monocell.This device shown in Figure 2 only is the simple example of the possible device architecture that can make based on the present invention.The possible purposes of such device is as the solar cell or the photovoltaic cell that daylight are converted into electric energy.Can change layer, i.e. p-type or N-shaped, order.In addition, in some cases, comprise that the very large p+ layer of wherein excessive removable hole concentration may expect.Similarly, can deposit the n+ layer.Layer so also can be for the manufacture of the electric contact in the device.
Basic structure illustrated in figures 1 and 2 can be for the manufacture of large-scale electronic device, for example photovoltaic device, flat-panel monitor, thermo-photovoltaic device, ferro-electric device, LED device, computer hard disc driver device, based on the device of magnetic resistance, device, nonvolatile memory device, dielectric devices, thermoelectric device and quantum dot laser spare based on luminescence generated by light.The electronic device that can easily imagine is Double-end device, for example diode; Three termination devices, for example transistor, thyristor or rectifier; And multiterminal head device, for example microprocessor, random access memory, read-only memory or charge coupled device.
In the most exciting application some is in photovoltaic cell or solar cell and is used for display, for example thin-film transistor.In these two fields, the trend of using film in metal substrate has been arranged.Yet for these situations, semiconductor is unbodied or polycrystalline, and therefore the low performance of performance that obtains than from identical semi-conductive single crystal device is arranged.Flexible electronic instrument has physics and does not allow to use the rigid substrate part to realize the potentiality of novel application with restriction mechanics on the mechanics.In addition, use flexible substrate, it is contemplated that the rolling type manufacturing (roll-to-rollmanufacturing) similar to the printing machine that the treating capacity that is higher than significantly normal discrete semiconductor device manufacturing is arranged.In in application mentioned above some, there is the relatively loose requirement on devices of comparing other semiconductor device.The combination on metal, alloy and the ceramic substrate of large-area flexibility of the semiconductor layer of the near single of three axle texture and device can greatly change these application in these fields.Single crystal device on the substrate of flexibility will obtain high efficiency photovoltaic cell and the thin-film transistor (TFT) of higher electron mobility will be arranged.
Make the TFT circuit at the metal or alloy paper tinsel of flexibility and caused very big concern.See, for example, Thesis S.D. and Wagner S., " Amorphous silicon thin-film transistors on steel foilsubstrates (amorphous silicon film transistor on the steel foil substrate); " IEEE Electron Device Lett., vol.17, no.12, pp.578-580, Dec.1996; Serikawa T. and Omata F., " High-mobility poly-Si TFT ' s fabricated on flexible stainless steel substrates (the high mobility multi-crystal TFT of making at flexible stainless steel substrate); " IEEE ElectronDevice Lett., vol.20, no.11, pp.574-576, Nov.1999; Afentakis T. and Hatalis M., " High performance polysilicon circuits on thin metal foils (the high-performance polycrystal silicon circuit on the thin metal foil), " Proc.SPIE, vol.5004, pp.122-126,2003; Howell R.S., Stewart M., Karnik S.V., Saha S.K. and Hatalis M.K., IEEE Electron DeviceLett., vol.21, no.2, pp.70-72, Feb.2000.In these four pieces of papers, the result is Si layer polycrystalline or amorphous that orientation is arranged at all.Using polycrystalline Si in most cases, polycrystalline Si is the laser crystallization layer of Si.The amorphous layer of Si at first is deposited on the substrate, then is crystallisation step.Also can finish this crystallization with the infrared lamp that the high rate of heat addition is provided.Can use similar process to make the epitaxial silicon on substrate disclosed by the invention.The process that then precursor film of this at first deposited amorphous Si carries out follow-up crystallisation step is called as " ex situ (ex-situ) " process.Crystalline silicon also can be at high temperature directly epitaxial deposition on the substrate of near single.The single crystal device of three axle texture on metal, alloy and the ceramic substrate of flexibility will obtain the thin-film transistor (TFT) of the electron mobility higher than the electron mobility of the thin-film transistor of the silicon manufacturing that can use non-orientation, and therefore have veritably the potentiality of this application of very big change.Advanced flat-panel monitor, comprise active matrix liquid crystal display (LCD) (active matrix liquid crystal display), mainly used heavy sheet glass as substrate, heavy sheet glass provides the advantage of transparency and stable aspect, but it is weak and heavy to be highly brittle.Substrate in this paper will be firm and lightweight, and since device layer be three axle texture or near single, this substrate will have presumable those excellent performances on the specific rigidity glass substrate many performances.The wide range of flat panel display applications, and comprise computer monitor, TV, electronic billboard, mobile phone, calculator and the display screen on the consumer electronics of the whole series.For portable display, active matrix liquid crystal display (AMLCD) and active-matrix Organic Light Emitting Diode (AMOLED), use in the polycrystalline Si of K cryogenic treatment on glass and considered widely to be used for large-scale application.Active Matrix OLED (AMOLED) display is comprised of Organic Light Emitting Diode (OLED) pixel, wherein organic light-emitting diode pixel has been deposited or has been attached on thin-film transistor (TFT) array, luminous picture element matrix when being excited by electricity to be formed on.Opposite with passive-matrix OLED screens, if electricity distributes line by line, active-matrix TFT rear board flows through the array of switch of amount of the electric current of each OLED pixel as control so.Tft array is controlled the electric current that flows to pixel continuously, with the luminous brightness of each pixel of signal controlling.Usually, this continuous electric current is by at least two TFT controls in each pixel, a charging that begins and stop holding capacitor, and second voltage source that the needed level of generation constant current is provided to pixel.Therefore, AMOLED moves (that is, be used for whole frame scan) all the time, has avoided the needs to the needed very high electric current of passive-matrix operation.Polysilicon rear board technology for the manufacture of tft array is the current one preferred technique (technology-of-choice) that is used for OLED, because it provides the rational mobility that satisfies the requirement of OLED current drives (to see, for example, Afentakis T., Hatalis M., Voutsas T. and Hartzell J., " Poly-silicon TFT AM-OLED on thin flexible metalsubstrates (the multi-crystal TFT AM-OLED on the thin flexible metal substrate); " Proc.SPIE, vol.5004, pp.187-191,2003).The polysilicon technology also allows the directly combination on substrate of drive circuit.Yet, the challenge of the key that many needs overcome is arranged: reduce the threshold voltage inhomogeneities of polysilicon, and the productivity ratio of proof viable commercial.This problem can be expected to use device of the present invention to solve, in device of the present invention, three character axle texture or near single of semiconductor device layer will reduce inhomogeneities and boost productivity, and improve significantly mobility and will remain lightweight, because do not use glass.Fig. 3 A illustrates the schematic diagram of simple AMOLED device.Fig. 3 A when uniting with Fig. 1 and 2, shows the mode that can make based on AMOLED of the present invention, wherein uses the present invention to make the TFT/ substrate array.
An important application of device disclosed by the invention is in the photovoltaic field.Device schematically illustrated among Fig. 2 can be used as photovoltaic cell or solar cell.These devices will be large-area and flexible, and can be placed on the roof.Flexible solar cell is also used useful to space, because the large array of photovoltaic module or spool can be wrapped and then launch in space.
A kind of mode of making the higher solar cell of efficient be find with from the larger part of the spectrum of daylight-from infrared ray to visible light to ultraviolet ray-catch the material of energy.When photovoltaic material absorbed the light wave of the energy that contains the amount identical with its band gap, energy was from photon transfer to photovoltaic material.Band gap is that electronics is pushed to the needed energy of conduction band (Eg) that electronics freely flows therein from the valence band of material.Fig. 3 B shows the schematic diagram of the device that contains three photovoltaic cells that different band gap arranged.This structure is also referred to as cascade battery (cascade cell) or laminated cell (tandem cell), and this structure can realize higher total conversion efficiency by the larger part of catching solar spectrum.In this typical multijunction cell, each battery with different band gap is stacked on each other top.Each battery so that the mode that daylight at first is radiated on the material with maximum band gap be stacked.Absorbed photon is not transferred to second battery in first battery, and the part that then energy of the solar radiation of second battery adsorbing residual is higher also keeps seeing through to the lower photon of energy.These selectivity absorption processes continue, until arrive the final battery with minimum band gap.Such multijunction cell can obtain very high efficient.The principle of multijunction cell can obtain (MartinA.Green from prior art, Keith Emery, Klaus B ü cher, David L.King, Sanekazu Igari, " Solarcell efficiency tables (version 11) (solar battery efficiency table (the 11st edition); " Progressin Photovoltaics:Research and Applications, the 6th volume, the 1st phase, the 35-42 page or leaf, on May 4th, 1999; Karam, N.H.; King, R.R.; Cavicchi, B.T.; Krut, D.D.; Ermer, J.H.; Haddad, M.; Li Cai; Joslin, D.E.; Takahashi, M.; Eldredge, J.W.; Nishikawa, W.T.; Lillington, D.R.; Keyes, B.M.; Ahrenkiel, R.K., " Development and characterization of high-efficiency Ga0.5ln0.5P/GaAs/Gedual-and triple-junction solar cells (exploitation of high efficiency Ga0.5ln0.5P/GaAs/Ge binode and three-joint solar cell and sign); " Electron Devices, IEEE Transactions on, Vol.46, No.10, pp.2116-2125, Oct.1999; H.Hou, K.Reinhardt, S.Kurtz, J.Gee, A.Allerman, B.Hammons, P.Chang, E.Jones, Novel InGaAsN pn junction forhigh-efficiency multiple-junction solar cells (the novel I nGaAsN pn knot that is used for the multiple joint solar cell of high efficiency), The Second World Conference on PV EnergyConversion (meeting of Second Committee world PV power conversion), 1998, pp.3600-3603; D.Friedman, J.Geisz, S.Kurtz, J.Olson, 1-eV GaInNAs solar cells for ultra highefficiency multijunction devices (the 1-eV GaInNAs solar cell that is used for the Ultra-High Efficiency multijunction device), the meeting of the international PV power conversion of Second Committee, 1998, pp.3-7; T.V.Torchynska and G.Polupan, " High efficiency solar cells for space applications (being used for the high efficiency solar cell that use in the space); " Superficies y Vacio 17 (3), 21-25, in September, 2004; R.McConnell and M.Symko-Davies, " DOE High Performance Concentrator PVProject (DOE high-performance optically focused device PV engineering); " International Conference on SolarConcentrators for the Generation of Electricity or Hydrogen (about the international conference of the solar condenser that is used for generating or hydrogen manufacturing), 1-5 May 2005, Scottsdale, Arizona, NREL/CD-520-38172).
Fig. 4 shows the cross section of some multijunction cell of having reported in the literature.Whole conversion efficiencies near 40% expection that schematic diagram has illustrated the part of being caught by multijunction cell in the spectrum of the sun and these batteries.Fig. 4 A shows three junction batteries of GaInP (1.8eV)/GaAs (1.4eV)/Ge (0.7eV); Fig. 4 B shows three junction batteries of GaInP (1.8eV)/GaInAs (1.25eV)/Ge (0.7eV); And Fig. 4 C shows four junction batteries of GaInP (1.8eV)/GaAs (1.4eV)/GaInAs (1.25eV)/Ge (0.7eV).Be apparent that the advantage of more part of catching the spectrum of the sun is higher conversion efficiency.Fig. 5 shows the Utopian schematic diagram with cross-sectional form according to many knots electronic device of the pn knot that contains two extensions that texture arranged of the present invention, and wherein the pn knot is parallel to substrate surface.Fig. 5 shows and comprises following device: the metal or alloy substrate that texture is arranged on similar flexibility, crystalline, the crystallography of the substrate of describing to Fig. 1 and 2; The single of texture or multi-buffer layer are arranged on the crystallography; The semiconductor layer of selectable extension or on forming graduate template layer; Bottom battery texture, extension that has that comprises the pn knot; Tunnel junction; The top battery that comprises the pn knot; Transparent conductor layer; Antireflection coating and metal grid lines.A purposes of device shown in Figure 5 is for solar power generation.Fig. 6 shows the Utopian schematic diagram with cross-sectional form that contains many knots electronic device of three pn knots that texture arranged according to of the present invention, and wherein the pn knot is parallel to substrate surface.Fig. 6 shows and comprises following device: the metal or alloy substrate that texture is arranged on similar flexibility, crystalline, the crystallography of the substrate of describing to Fig. 1 and 2; The single of texture or multi-buffer layer are arranged on the crystallography; The semiconductor layer of selectable extension or on forming graduate template layer; Comprise that pn is knot, bottom battery that texture is arranged, extension; Tunnel junction; The middle cell that comprises the pn knot; Tunnel junction; The top battery that comprises the pn knot; Transparent conductor layer; Antireflection coating and metal grid lines.Similarly, device shown in Figure 6 purposes is for solar power generation.
The performance of electronic device depends on defect concentration.A mode that reduces the defect concentration in the semiconductor layer initiatively is to reduce the lattice mismatch of itself and top resilient coating.This can use " graduate resilient coating " approach to finish.Fig. 7 shows the Utopian schematic diagram with cross-sectional form such as the electronic device of describing among Fig. 1-6, the stacking thin resilient coating that different (gradually differing) lattice parameters is much arranged little by little that comprises of resilient coating wherein is to provide good Lattice Matching to the semiconductor layer of growing in top buffering template." graduate buffering approach " for the defect concentration that provides good Lattice Matching to minimize semiconductor layer to semiconductor is provided for this.The quantity of the layer of the graduate lattice parameter buffering that need to be deposited depends on the lattice mismatch between semiconductor and the substrate.
For defect concentration and better Lattice Matching semiconductor layer that makes higher-quality extension become possibility and to reduce in the semiconductor layer also can be by obtaining with the perovskite resilient coating rock salt structure resilient coating that mixes or mix, mixing or that mix, pyrochlore resilient coating mixing or doping.For example, can use rock salt structure oxide (AO, wherein A is metal), nitride (AN, wherein A is metal) and the oxynitride (AN of mixing xO 1-x, wherein A is metal), the perovskite (ABO that mixes 3, wherein A and B are metals), the pyrochlore (A that mixes 2B 2O 7, wherein A and B are metals) or the bixbyite (A that mixes 2O 3, wherein A is metal) and the structure oxide resilient coating comes the control lattice constant, to obtain the better Lattice Matching with semiconductor layer.The oxide of following mixing and nitride resilient coating receive special the concern:
1) the rock salt structure oxide and the nitride that mix, for example A xB 1-xO and A xB 1-xN, wherein A is different metals with B.For example, Ba 0.64Sr 0.36O, the solid solution of BaO and SrO provides the good Lattice Matching with Si.
2) oxynitride that mixes, for example A xB 1-xN yO 1-y, wherein A is different metals with B.
The bixbyite structure of 3) mixing, for example (A xB 1-x) 2O 3, wherein A is different metals with B.
4) perovskite (A that mixes xA ' 1-x) BO 3, (A xA ' 1-x) (B yB ' 1-y) O 3, wherein A, A ', B and B ' are different metals.For example, Ca 0.95Sr 0.05TiO 3, CaTiO 3And SrTiO 3Solid solution, the good Lattice Matching with Si is provided.
5) pyrochlore (A that mixes xA ' 1-x) 2B 2O 7, (A xA ' 1-x) 2(B yB ' 1-y) 2O 7, wherein A, A ', B and B ' are different metals.
In some cases, the defect concentration of using " graduate semiconductor die " approach to reduce in the active semiconductor layer that consists of electronic device is more expected.Fig. 8 shows the Utopian schematic diagram with cross-sectional form such as the electronic device of describing among Fig. 1-7, wherein the semiconductor module flaggy comprises the thin layer that little by little different lattice parameters is much arranged, with to semiconductor device layer or comprise pn knot and the first battery of growth above the semiconductor module flaggy provides good Lattice Matching." graduate semiconductor approach " for the defect concentration that provides good Lattice Matching further to minimize semiconductor device layer to semiconductor device layer is provided for this.In last situation, people it is contemplated that the combination of " graduate resilient coating " and " graduate semiconductor die " approach.Fig. 9 shows the Utopian schematic diagram with cross-sectional form such as the electronic device of describing among Fig. 1-8, and wherein resilient coating is stacking comprises a lot of thin resilient coatings, to provide good Lattice Matching to the semiconductor module flaggy of growing in top buffering template.In addition, the semiconductor module flaggy comprises a lot of thin layers, with to semiconductor device layer or comprise pn knot and the first battery of growth above the semiconductor module flaggy provides good Lattice Matching.Combination for " the graduate buffering approach " and " graduate semiconductor approach " of the defect concentration that provides good Lattice Matching to minimize this layer to semiconductor device layer is provided for this.
Embodiment 1: by one after the other cubic metal or alloy by the compression compacting or forge to large total deformation and and then recrystallization annealing temperature prepared the metal substrate of [100] single shaft texture.For example, use the NiW alloy that 3-9at%W is arranged, with its distortion with single shaft extruding boil down to 90%, then in stove at the annealing temperature of the primary recrystallization temperature that is higher than alloy.Formed primary recrystallization texture is [100] texture.By annealing temperature being increased to the high temperature near 1000 ℃, formed the mean grain size greater than 100 μ m.Then deposit the resilient coating of extension at substrate.For example, be under 300 ℃-600 ℃ the depositing temperature in temperature range, use the TiN layer of chemical vapour deposition (CVD) (CVD) deposition extension.Then under scope is 300 ℃-900 ℃ depositing temperature, use the Si layer of CVD type process deposits extension.This causes the formation of the Si device layer of [100] single shaft texture.Selectively, by changing the sedimentary condition of Si layer, obtain [110] crystallography texture relative with [100] texture.
Embodiment 2: by one after the other cubic metal or alloy by the compression compacting to large total deformation and and then recrystallization annealing temperature prepared the metal substrate of [110] single shaft texture.For example, use the NiW alloy that 3-9at%W is arranged, with its distortion with single shaft extruding boil down to 90%, then in stove at the annealing temperature of the primary recrystallization temperature that is higher than alloy.Formed primary recrystallization texture is [110] texture.By annealing temperature being increased to the high temperature near 1000 ℃, formed the mean grain size greater than 100 μ m.Then deposit the resilient coating of extension at substrate.For example, be under 300 ℃-600 ℃ the depositing temperature in temperature range, use the TiN layer of chemical vapour deposition (CVD) (CVD) deposition extension.Then under scope is 300 ℃-900 ℃ depositing temperature, use the Si layer of CVD type process deposits extension.This causes the formation of the Si device layer of [110] single shaft texture.Selectively, by changing the sedimentary condition of Si layer, obtain [100] crystallography texture relative with [100] texture.
Embodiment 3: Figure 10 shows has NiW alloy texture, flexible and at the Si semiconductor layer that texture is arranged above the alloy with between the Utopian schematic diagram with cross-sectional form of the resilient coating of the extension of the TiN that texture is arranged between them on the crystallography.This device is consistent with the device that Fig. 1 describes.By being the alloy coil that is obtained by powder metallurgy that thickness is the Ni-3at%W that the paper tinsel of about 2 mils or 50 microns has prepared the biaxial texture of [100] texture from the thickness continuous rolling of about 120 mils.The rolling crystallography texture of paper tinsel or band is the standard C u-shaped rolling texture of the FCC metal of very big distortion.After band degreasing and drying, band is loaded into the reel-to-reel high vacuum (10 of holding the radio frequency induction heating furnace -8Holder) in the chamber.Band is～3 * 10 -7Be pulled hot-zone by stove so that each part was heated to 1250 ℃ speed in 20 minutes under the local pressure of hydrogen sulfide gas of holder, form sulphur c (2 * 2) superstructure with the surface at band.After high annealing, the NiW band is cubic texture completely, and have corresponding to orientation 100}＜100〉and sharp keen texture, and have surface reconstruction corresponding to c (2 * 2) sulphur superstructure.Then TiN and the two epitaxial deposition of Si layer on the NiW band.Use stoichiometric hot pressing TiN target growth TiN.By 3 * 10 -8The holder reference pressure under under 700 ℃ with about 2-3J/cm 2Laser energy carry out 15 minutes pulse laser ablation and deposit these films with the repetition rate of 10Hz.Figure 11 shows typical (111) X ray utmost point figure of the sample of epitaxially grown TiN on the Ni-3at%W substrate of three axle texture.Only seen the peak of equivalence on four crystallography, this show by force 100}＜100〉be orientated.Use
Figure DEST_PATH_GSB00000569381800061
The half width (FWHM) of texture and use X-ray diffraction also represent at figure by the half width (FWHM) of the outer texture of face of (200) ω scanning survey in the face of scanning survey.Texture FWHM is normally about 6.6 in the face, and the outer FWHM of face is 3.2 for the deviation (rocking) along the rolling direction of substrate and is 6.6 for the deviation around rolling direction.After the width that counts ω scanning
Figure DEST_PATH_GSB00000569381800062
" real " FWHM of scanning is～5 ° approximately.Then (λ=248nm, the pulsed excimer laser of τ=25ns) is with～10 as the KrF of 5-7J-cm-2 to use energy density -7The benchmark vacuum of holder is deposited on silicon fiml on the TiN layer.Initially, in initial 2 minutes between the Si depositional stage, ablation velocity is 2Hz, and underlayer temperature is in 650 ℃-700 ℃ scope.After this, the temperature that is used for growth is reduced to 520 ℃-550 ℃ temperature range, and carries out Si growth 15 minutes with the repetition rate of 10Hz.Figure 12 shows the low multiplication factor TEM cross section of the sample of Ni-3at%W/TiN/Si.In microphoto, can clearly distinguish whole three layers.The TiN layer is that the thick and Si film of about 110nm is that about 1 μ m is thick.Figure 13 shows from obtaining with 0.6 micron spacing on hexagonal mesh and the orientation image microphoto of the electron backscattered Kikuchi diffraction pattern generation of index.The tonal gradation shadow representation that provides among Figure 13 A has the district that is connected to each other less than the misorientation of 2 degree.The tonal gradation shadow representation that provides among Figure 13 B has the district that is connected to each other less than the misorientation of 3 degree.Be clear that the large single crystal that the silicon layer representative has some to inlay.The particle of the crowned of seeing in the image the reason there is, film is to use the pulse laser ablation technology growth, knownly can form so granular feature in this technology.Make deposited by electron beam evaporation or chemical vapour deposition (CVD) come growing film will obtain the very high film of smoothness.Figure 13 shows that Si films extension, height-oriented, three axle texture can be deposited on the NiW/TiN substrate of three axle texture.Figure 14 shows the high-resolution cross sectional image at epitaxially grown Si/TiN interface.Microphoto clearly shows the extension essence of growth and the sharpness at the interface between TiN layer and the Si layer.Figure 15 shows along the high-resolution transmission electron microscope photo on the plane of the silicon layer of＜100〉the direction extensions of getting.Insertion illustrates fast Fourier transform (FFT) pattern of photo.Be apparent that the upper growth of NiW that the Si film of extension is being cushioned by TiN.Figure 16 show Si/TiN/NiW the transmission electron microscopy sample plane graph＜100〉crystal zone axis selected area diffraction patterns, show the arrangement of the extension of Si{220}, TiN{200} and Ni{200} diffraction spot.Clearly visible and done mark in diffraction pattern from the spot of whole three layers.45 ° rotation is arranged between Si and TiN, and on the TiN on the Ni also has cube cube the relation of (cubeon cube) extension.Figure 17 also show from the plane graph of the transmission electron microscopy sample of Si/TiN/NiW＜100〉crystal zone axis selected area diffraction patterns, show the arrangement of the extension of Si{220}, TiN{200} and Ni{200} diffraction spot.In this case, obtain the Qu Gengda of diffraction pattern.Although silicon is to use pulsed laser ablation deposition in this case, and the technology that much can be used for the Si deposition is arranged.Many summaries that obtained recently in these technology (are seen, for example, MichelleJ.McCann, Kylie R.Catchpole, Klaus J.Weber, Andrew W.Blakers, " A reviewof thin-film crystalline silicon for solar cell applications.Part 1:Nativesubstrates is (about the summary of the thin film silicon/crystalline silicon that is used for solar cell application.Part 1: natural substrate), " Solar Energy Materials and Solar Cells, the 68th volume, the 2nd phase, May calendar year 2001,135-171 page or leaf; Kylie R.Catchpole, Michelle J.McCann, Klaus J.Weber and Andrew W.Blakers, " A review of thin-film crystalline silicon forsolar cell applications.Part 2:Foreign substrates is (about the summary of the thin film silicon/crystalline silicon that is used for solar cell application.Part 1: external substrate), " Solar Energy Materials and SolarCells, the 68th volume, the 2nd phase, May calendar year 2001,173-215 page or leaf).The technology of electron beam evaporation sputter (electron-beam evaporation sputtering), ion beam sputtering, chemical vapour deposition (CVD), metal organic chemical vapor deposition (metallorganic chemical vapor deposition) and combustion chemical vapor deposition (combustion chemical vapor deposition) is the technology for the deposition of resilient coating and semiconductor layer.
It is also important that to it should be noted that in the situation that single resilient coating or multi-buffer layer are arranged, after the depositional stage of layer between below the resilient coating of top, can form the conversion zone that does not have with the crystallography texture of the orientation expected.These conversion zones do not affect the orientation of device layer, because the suitably layer of the buffering of orientation is arranged above device layer.Usually, in multilayer system, can occur polycrystalline, without the formation of the conversion zone of crystallography texture, as long as the deposition of the layer of its suitably orientation above the layer that comes into question finish after formation.
The twin boundary that links up that in silicon layer, has some first order.Therefore, the Si layer is not contain defectiveness fully.Yet such twin boundary that links up is not quite disadvantageous and is not (Hjemas, the P.C of active on the electronics, Lohne, O., Wandera, A., Tathgar, H.S., " The effect of grainorientations on the efficiency of multicrystalline solar cells (grain orientation is on the impact of the efficient of polycrystalline solar cell); " Solid State Phenonema, vol.95-96, pp.217-222,2004; B.Cunningham, H.Strunk and D.G.Ast, " First and second order twinboundaries in edge defined film growth silicon ribbon (the first order and second level twin boundary in the film growth silicon ribbon of fringe enclosing); Appl.Phys.Lett.; 40; pp.237-239,982).Although clearly do not observe other defective in the film of manufacturing, if the other defect of nucleation is arranged, they can be passivated to become on inactive on the electricity or the electronics almost harmless.The defective that needs passivation like this usually occurs in single-crystal wafer and the band of making for solar cell.There are many prior aries to confirm that such defective can be passivated (M.Rinio, M.Kaes, G.Hahn and D.Borchert, " Hydrogen passivation of extended defects in multicrystallinesilicon solar cells (the hydrogen passivation of the extended defect in the polysilicon solar cell), " is published in the 21 ThEuropean Photovoltaic Solar Energy Conference and Exhibition (the 21st European photovoltaic solar meeting and fair), Dresden (Dresden), Germany, 4-8 day in September, 2006; A.Ebong, M.HiIaIi, A.Rohtagi, D.Meier and D.S.Ruby, " Beltfurnace gettering and passivation of n-web silicon for high-efficiencyscreen-printed front-surface field solar cells (through furnace that is used for the n-network silicon of high efficiency reticulated printing front surface area solar cell is cooled down and passivation); " Progress in Photovoltaics:Research and Applications, 9, pp.327-332,2001; C.H.Seager, D.J.Sharp and J.K.G.Panitz, " Passivation of grain boundaries in silicon (passivation of crystal boundary in the silicon), " J.Vac.Sci.﹠amp; Tech., 20, pp.430-435,1982; N.H.Nickel, N.M.Johnson and W.B.Jackson, " Hydrigen passivation of grain boundary defects in polycrystallinesilicon thin films (the hydrogen passivation of the grain boundary defects in the polysilicon membrane); " Appl.Phys.Lett., 62, pp.3285-3287,1993; A.Ashok, " Research in hydrogen passivation of defectsand impurities in silicon (about the research of the hydrogen passivation of defect and impurity in the silicon); " NRELReport No.NREL/SR-520-36096, in May, 2004; M.Lipinski, P.Panek, S.Kluska, P.Zieba, A.Szyszka and B.Paszkiewicz, " Defect passivation ofmulticrystalline silicon solar cells by silicon nitride coatings (the defective passivation that the use silicon nitride of polysilicon solar cell coats); " Materials Science-Poland, vol.24, pp.1003-1007,2006; V.Yelundur, " Understanding and implementation ofhydrogen passivation of defects in string ribbon silicon for high-efficiency; manufacturable; silicon solar cells (being used for understanding and the realization of hydrogen passivation of defective of the wire drawing band silicon of the silicon solar cell that high efficiency can make); " Ph.D thesis, Georgia Institute ofTechnology, Atlanta, GA, Nov.2003).
Although all types of single shaft texture, biaxial texture or three axle texture are all paid close attention in the metal or alloy substrate, what be subject to special concern is the crystalline orientation of three types.These comprise 100}＜100 〉, 110}＜100〉and 210}＜100〉orientation.In all these,＜100〉direction be parallel to through the overheated machine tool process, the major axis of the band of rolling and recrystallization.100}＜100〉produce by the annealing temperature in the primary recrystallization temperature that is higher than metal or alloy.110}＜100〉and 210}＜100〉and the orientation produce by the annealing temperature in the secondary recrystallization temperature that is higher than metal or alloy.100}＜100〉be oriented in many Face-centred Cubic Metals and alloy, Ni, Al and Cu base alloy for example, in produce easily.110}＜100〉texture is at bcc metals and alloy, ferrous alloy for example, in the easiest generation.210}＜100〉be oriented in such as producing easily in the alloy of Ni-Fe alloy.Heat engine tool processing for the manufacture of such substrate that texture is arranged can be expanded substrate length and wide that has random length to manufacturing.
The very large part of the silicon wafer that uses in global photovoltaic industry is the form with 8 inches wafers, and the electronics industry refusal uses 8 inches wafers.These wafers that contain many defectives are monocrystalline on the crystallography in addition, and have the area of 50.2 square inches (50.2 square inches).Recently, global electronics manufacturing shop more exchange device to adapt to the silicon wafer of 12 larger inch diameters.Photovoltaic industry might be used the unaccepted defective wafer with area of 12 inches diameter and 113 square inches that contains.Yet, this be available and can be in the maximum of the single-crystal wafer of whole world growth may size.The present invention allows people to make semi-conducting material greater than the flexibility of 50.2 square inches or 113.0 square inches, large-area, monocrystalline or near single.Can use the processing and manufacturing of heat engine tool that metal and the alloy substrate of texture are arranged, with production have 100}＜100 〉, 110}＜100〉and 210}＜100〉material of texture.Under these circumstances, can make the continuous sheet of large-area substrate, deposit epitaxial layers thereon obtains the electronic device of three axle texture.Have the length that surpasses 100 meters and be possible near the substrate of one meter width.In addition, such as before instruction, some method that is used for produce single crystal continuously or single crystal grain metal and/or alloy substrate is possible.
Except the texturing by heat engine tool processing approach, also have other known manufacturing that the approach of substrate of the flexibility of texture, for example ion beam assisted depositing (IBAD), inclination substrate deposition (ISD) and the deposition in the presence of magnetic field are arranged.IBAD technique is at United States Patent (USP) the 6th, 632, and 539,6,214,772,5,650,378,5,872,080,5,432,151,6,361,598,5,872,080,6,190,752,6,756,139,6,884,527,6,899,928,6,921, describe in No. 741; ISD technique is at United States Patent (USP) the 6th, 190, and 752 and 6,265, describe in No. 353; And the biaxial texture that is formed by the deposition in the presence of magnetic field is described in No. the 6346181st, United States Patent (USP); All these patents all are incorporated herein by reference.Also can obtain texture in the face by Growing Process of Crystal Particles optionally to Ions Bombardment (Post-deposition ion-bombardment) after the deposition of the metal of the single shaft texture on the polycrystalline substrate of non-orientation and/or alloy film, and in extreme situation, film can become three axle texture.In all these techniques, used flexible, polycrystalline, untextured substrate or amorphous substrate, buffer layer deposition is on these substrates.In the crucial resilient coating one uses IBAD, ISD or the deposition in magnetic field and the layer that is deposited on the biaxial texture on this substrate.In case grown the resilient coating of texture is arranged, then semiconductor layer is having epitaxial growth on the resilient coating of texture.In in above-mentioned situation each, can grow can not be by the device of having of obtaining of silicon or any other semi-conductive crystal growth greater than 113.0 square inches area.
Figure 18 shows according to the present invention and the Utopian schematic diagram with cross-sectional form of the various other preferred embodiments of the sandwich construction of embodiment 1.That Figure 18 A shows is flexible, crystalline, the metal or alloy substrate of texture is arranged on the crystallography; Crystallography above substrate has the TiN resilient coating of texture, and the Si of extension or other semiconductor device or template layer.
Embodiment 4: the Ni-3at%W substrate with biaxial texture begins, and is the epitaxial loayer of the MgO that growth 10-75nm is thick under 300 ℃-850 ℃ the underlayer temperature in scope by electron beam evaporation, sputter, pulse laser ablation or chemical vapour deposition (CVD).Be the epitaxial loayer of the thick TiN of 300 ℃-850 ℃ underlayer temperature deposit 10-75nm in scope by electron beam evaporation, sputter, pulse laser ablation or chemical vapour deposition (CVD) subsequently.Use subsequently chemical vapour deposition (CVD) at the Si layer of 300 ℃-900 ℃ temperature range deposition extension.That Figure 18 B shows is flexible, crystalline, the metal or alloy substrate of texture is arranged on the crystallography; Crystallography above substrate has the MgO resilient coating of texture; Crystallography above the MgO layer has the TiN resilient coating of texture; And the Si of extension or other semiconductor device or template layer.
Embodiment 5: the Ni-3at%W substrate with biaxial texture begins, and is the thick Y of growth 10-75nm under 300 ℃-850 ℃ the underlayer temperature in scope by electron beam evaporation, sputter, pulse laser ablation or chemical vapour deposition (CVD) 2O 3Epitaxial loayer.Be the epitaxial loayer of the thick YSZ of 300 ℃-850 ℃ underlayer temperature deposit 10-75nm in scope by electron beam evaporation, sputter, pulse laser ablation or chemical vapour deposition (CVD) subsequently.Be the epitaxial loayer of the thick TiN of 300 ℃-850 ℃ underlayer temperature deposit 10-75nm in scope by electron beam evaporation, sputter, pulse laser ablation or chemical vapour deposition (CVD) subsequently.Use subsequently chemical vapour deposition (CVD) at the Si layer of 300 ℃-900 ℃ temperature range deposition extension.That Figure 18 C shows is flexible, crystalline, the metal or alloy substrate of texture is arranged on the crystallography; Crystallography above substrate has the Y of texture 2O 3Resilient coating; At Y 2O 3The YSZ resilient coating that texture is arranged on the crystallography of layer top; Crystallography above the YSZ layer has the TiN resilient coating of texture; And the Si of extension or other semiconductor device or template layer.
Embodiment 6: the Ni-3at%W substrate with biaxial texture begins, and is the thick Y of growth 10-75nm under 300 ℃-850 ℃ the underlayer temperature in scope by electron beam evaporation, sputter, pulse laser ablation or chemical vapour deposition (CVD) 2O 3Epitaxial loayer.Be the epitaxial loayer of the thick YSZ of 300 ℃-850 ℃ underlayer temperature deposit 10-75nm in scope by electron beam evaporation, sputter, pulse laser ablation or chemical vapour deposition (CVD) subsequently.Be the epitaxial loayer of the thick MgO of 300 ℃-850 ℃ underlayer temperature deposit 10-75nm in scope by electron beam evaporation, sputter, pulse laser ablation or chemical vapour deposition (CVD) subsequently.Be the epitaxial loayer of the thick TiN of 300 ℃-850 ℃ underlayer temperature deposit 10-75nm in scope by electron beam evaporation, sputter, pulse laser ablation or chemical vapour deposition (CVD) subsequently.Use subsequently chemical vapour deposition (CVD) at the Si layer of 300 ℃-900 ℃ temperature range deposition extension.That Figure 18 D shows is flexible, crystalline, the metal or alloy substrate of texture is arranged on the crystallography; Crystallography above substrate has the Y of texture 2O 3Resilient coating; At Y 2O 3The YSZ resilient coating that texture is arranged on the crystallography of layer top; Crystallography above the YSZ layer has the MgO resilient coating of texture; Crystallography above the MgO layer has the TiN resilient coating of texture; And the Si of extension or other semiconductor device or template layer.In in situation shown in Figure 180 each, can be at the at the interface formation nitride layer of top resilient coating and semiconductor device or template layer, for example silicon nitride or nitrogenize germanium layer.That this layer not necessarily needs to be to have texture or extension.
Figure 19 shows the other Utopian schematic diagram with cross-sectional form according to the various embodiments of sandwich construction of the present invention.That Figure 19 A shows is flexible, crystalline, the metal or alloy substrate of texture is arranged on the crystallography; At least one crystallography above substrate has cube nitride resilient coating of texture, and the Si of extension or other semiconductor device or template layer.That Figure 19 B shows is flexible, crystalline, the metal or alloy substrate of texture is arranged on the crystallography; Crystallography above substrate has the MgO resilient coating of texture; At least one crystallography above the MgO layer has cube nitride resilient coating of texture; And the Si of extension or other semiconductor device or template layer.That Figure 19 C shows is flexible, crystalline, the metal or alloy substrate of texture is arranged on the crystallography; Crystallography above substrate has the Y of texture 2O 3Resilient coating; At Y 2O 3The YSZ resilient coating that texture is arranged on the crystallography of layer top; At least one crystallography above the YSZ layer has cube nitride resilient coating of texture; And the Si of extension or other semiconductor device or template layer.That Figure 19 D shows is flexible, crystalline, the metal or alloy substrate of texture is arranged on the crystallography; Crystallography above substrate has the Y of texture 2O 3Resilient coating; At Y 2O 3The YSZ resilient coating that texture is arranged on the crystallography of layer top; Crystallography above the YSZ layer has the MgO resilient coating of texture; At least one crystallography above the MgO layer has cube nitride resilient coating of texture; And the Si of extension or other semiconductor device or template layer.In in situation shown in Figure 19 each, can be at the at the interface formation nitride layer of top resilient coating and semiconductor device or template layer, for example silicon nitride or nitrogenize germanium layer.That this layer not necessarily needs to be to have texture or extension.
Embodiment 7: the Ni-3at%W substrate with biaxial texture begins, and is the thick γ-Al of growth 10-75nm under 300 ℃-850 ℃ the underlayer temperature in scope by electron beam evaporation, sputter, pulse laser ablation or chemical vapour deposition (CVD) 2O 3Epitaxial loayer.Use subsequently chemical vapour deposition (CVD) at the Si layer of 300 ℃-900 ℃ temperature range deposition extension.Exist in the literature many about Si at γ-Al 2O 3On epitaxially grown report (see, for example, Liwen tan, Qiyuan Wang, Jun Wang, Yuanhuan Yu, Zhongli Liu and Lanying Lin, " Fabrication of novel double-hetero-epitaxial SOIstructure Si/ γ-Al 2O 3/ Si (novel dual heteroepitaxy SOI structure Si/ γ-Al 2O 3The manufacturing of/Si), " Journal of Crystal Growth, vol.247, pp.255-260,2003; K.Sawada, M.Ishida, T.Nakamura and N.Ohtake, " Metalorganic moelecular beam epitaxy of films onSi at low growth temperatures (the metal organic molecular beam epitaxy of the film under the low growth temperature on Si); " Appl.Phys.Lett., vol.52, pp.1672-1674,1988; M.Shahjahan, Y.Koji, K.Sawada and M.Ishida, " Fabrication of resonance tunnel diode bygamma-Al 2O 3/ Si multiple heterostructures (uses γ-Al 2O 3The multiple heterostructure of/Si is made resonant tunneling diode), " Japan.J.of Appl.Phys.Part 1, vol.41 (4B), pp.2602-2605,2002).Figure 20 shows according to the present invention and the Utopian schematic diagram with cross-sectional form of the various embodiments of the sandwich construction of present embodiment.That Figure 20 A shows is flexible, crystalline, the metal or alloy substrate of texture is arranged on the crystallography; Crystallography above substrate has the γ-Al of texture 2O 3Resilient coating, and the Si of extension or other semiconductor device or template layer.
Embodiment 8: the Ni-3at%W substrate with biaxial texture begins, and making deposited by electron beam evaporation, sputter, pulse laser ablation or chemical vapour deposition (CVD) is MgO or the TiN layer that epitaxial deposition 10-75nm is thick on the NiW substrate under 300 ℃-700 ℃ the underlayer temperature in scope.Be 300 ℃-850 ℃ the thick γ-Al of underlayer temperature deposit 10-75nm subsequently in scope by electron beam evaporation, sputter, pulse laser ablation or chemical vapour deposition (CVD) 2O 3Epitaxial loayer.Use subsequently chemical vapour deposition (CVD) at the Si layer of 300 ℃-900 ℃ temperature range deposition extension.Figure 20 B shows according to the present invention and the schematic diagram of present embodiment.That Figure 20 B shows is flexible, crystalline, the metal or alloy substrate of texture is arranged on the crystallography; Crystallography above substrate has the MgO resilient coating of texture; Crystallography above the MgO layer has the γ-Al of texture 2O 3Resilient coating; And the Si of extension or other semiconductor device or template layer.
Embodiment 9: the Ni-3at%W substrate with biaxial texture begins, make deposited by electron beam evaporation, sputter, pulse laser ablation or chemical vapour deposition (CVD) in scope be under 300 ℃-700 ℃ the underlayer temperature on the NiW substrate the thick Y of epitaxial deposition 10-75nm 2O 3Layer.Be the epitaxial loayer of the thick YSZ of 300 ℃-850 ℃ underlayer temperature deposit 10-75nm in scope by electron beam evaporation, sputter, pulse laser ablation or chemical vapour deposition (CVD) subsequently.Be 300 ℃-850 ℃ the thick γ-Al of underlayer temperature deposit 10-75nm subsequently in scope by electron beam evaporation or sputter or pulsed laser deposition 2O 3Epitaxial loayer.Use subsequently chemical vapour deposition (CVD) at the Si layer of 500 ℃-900 ℃ temperature range deposition extension.Figure 20 C shows according to the present invention and the schematic diagram of present embodiment.That Figure 20 C shows is flexible, crystalline, the metal or alloy substrate of texture is arranged on the crystallography; Crystallography above substrate has the Y of texture 2O 3Resilient coating; At Y 2O 3The YSZ resilient coating that texture is arranged on the crystallography of layer top; Crystallography above the YSZ layer has the γ-Al of texture 2O 3Resilient coating; And the Si of extension or other semiconductor device or template layer.
Embodiment 10: the Ni-3at%W substrate with biaxial texture begins, make deposited by electron beam evaporation, sputter, pulse laser ablation or chemical vapour deposition (CVD) in scope be under 300 ℃-700 ℃ the underlayer temperature on the NiW substrate the thick Y of epitaxial deposition 10-75nm 2O 3Layer.Be the epitaxial loayer of the thick YSZ of 300 ℃-850 ℃ underlayer temperature deposit 10-75nm in scope by electron beam evaporation, sputter, pulse laser ablation or chemical vapour deposition (CVD) subsequently.Be the epitaxial loayer of the thick MgO of 300 ℃-850 ℃ underlayer temperature deposit 10-75nm in scope by electron beam evaporation, sputter, pulse laser ablation or chemical vapour deposition (CVD) subsequently.Be 300 ℃-850 ℃ the thick γ-Al of underlayer temperature deposit 10-75nm subsequently in scope by electron beam evaporation, sputter, pulse laser ablation or chemical vapour deposition (CVD) 2O 3Epitaxial loayer.Use subsequently chemical vapour deposition (CVD) at the Si layer of 300 ℃-900 ℃ temperature range deposition extension.Figure 20 D shows according to the present invention and the schematic diagram of present embodiment.That Figure 20 D shows is flexible, crystalline, the metal or alloy substrate of texture is arranged on the crystallography; Crystallography above substrate has the Y of texture 2O 3Resilient coating; At Y 2O 3The YSZ resilient coating that texture is arranged on the crystallography of layer top; Crystallography above the YSZ layer has the MgO resilient coating of texture; Crystallography above the MgO layer has the γ-Al of texture 2O 3Resilient coating; And the Si of extension or other semiconductor device or template layer.Figure 21 shows the configuration similar to Figure 20, and different is to use any other cubic oxide thing to replace γ-Al 2O 3Resilient coating.This cubic oxide thing layer also can be graduate oxide skin(coating), provides better Lattice Matching with the semiconductor layer to extension.
Embodiment 11: the experimental arrangement with embodiment 1-10 begins, and germanium (Ge) or Si are deposited on top resilient coating or the selectable semiconductor module flaggy.Deposit subsequently the GaAs layer of extension by chemical vapour deposition (CVD).Deposit subsequently the InGaP layer of extension.Then the deposit transparent conductor deposits antireflection coating and metal grid lines subsequently.Made now the schematically illustrated device of Figure 22.The purpose of making such multijunction device above has been discussed, and target is that the larger part of the spectrum by catching the sun improves photoelectric conversion efficiency in Figure 4 and 5.Can be prepared with according to the instruction among the embodiment 1-10 resilient coating and the selectable substrate that the semiconductor module flaggy of texture is arranged.During the manufacturing of the device shown in the present embodiment, can be forming at the interface of top resilient coating untextured or the conversion zone of texture is arranged, to form nitride or oxide, for example silicon nitride or silicon dioxide layer with semiconductor.
Embodiment 12: with the polycrystalline on surface that level and smooth and cleaning are arranged, flexible Ni alloy substrate begins (can come the surface of clean substrate and make that it is more level and smooth by chemical etching and/or planarization, reactive ion etching, mechanical polishing or by electropolishing), uses inclination substrate deposition (ISD) by the MgO layer of texture is arranged on the electron-beam evaporation crystallography.Before by inclination substrate deposition deposition techniques MgO layer, can deposit layer selectable amorphous or polycrystalline.During ISD, substrate angle with 25 °-30 ° between depositional stage tilts towards the MgO steam.The high deposition rate of use＞3nm/s.Use is covered growth that (shadowing) carry out and is only selected to cause MgO crystal grain to have in the good face to arrange and about 20 ° surface tilt.Use sputters at depositing TiN layer on this MgO layer.Deposit subsequently the silicon layer of extension.For further resilient coating combination, the instruction among the applicable embodiment 1-11.
Embodiment 13: the experimental arrangement with embodiment 10 begins, deposit Germanium (Ge) layer on the Si of extension layer.Deposit subsequently the GaAs layer of extension by chemical vapour deposition (CVD).Deposit subsequently the InGaP layer of extension.Then the deposit transparent conductor deposits antireflection coating and metal grid lines subsequently.
Embodiment 14: with the polycrystalline on surface that level and smooth and cleaning are arranged, flexible Ni alloy substrate begins (can come the surface of clean substrate and make that it is more level and smooth by chemical etching and/or planarization, reactive ion etching, mechanical polishing or by electropolishing), uses inclination substrate deposition (ISD) by the MgO layer of texture is arranged on the electron-beam evaporation crystallography.Before by inclination substrate deposition deposition techniques MgO layer, can deposit layer selectable amorphous or polycrystalline.During ISD, substrate angle with 25 °-30 ° between depositional stage tilts towards the MgO steam.The high deposition rate of use＞3nm/s.Use is covered the growth carried out and is only selected to cause MgO crystal grain to have in the good face to arrange and about 20 ° surface tilt.Be to make deposited by electron beam evaporation at the thick γ-Al of this MgO layer deposition 50nm under 700 ℃-850 ℃ the underlayer temperature in scope 2O 3Epitaxial loayer.Deposit subsequently the silicon layer of extension.
Embodiment 15: the experimental arrangement with embodiment 14 begins, deposit Germanium (Ge) layer on the Si of extension layer.Deposit subsequently the GaAs layer of extension by chemical vapour deposition (CVD).Deposit subsequently the InGaP layer of extension.Then the deposit transparent conductor deposits antireflection coating and metal grid lines subsequently.
Embodiment 16: with the polycrystalline on surface that level and smooth and cleaning are arranged, flexible Ni alloy substrate begins (can come the surperficial of clean substrate and make that it is more level and smooth by chemical etching and/or with the planarization of the deposition of amorphous layer, reactive ion etching, mechanical polishing or by electropolishing), use the technique of United States Patent (USP) 6190752 instructions, use ion beam assisted depositing (IBAD), by the MgO layer of texture is arranged on electron beam evaporation or the sputtering sedimentation crystallography.By before the IBAD deposition techniques MgO layer, can deposit layer selectable amorphous or polycrystalline.Then use sputter, evaporation or chemical vapour deposition (CVD) Direct precipitation TiN layer on the layer of this ion assisted deposition.Deposit subsequently the silicon layer of extension.
Embodiment 17: the experimental arrangement with embodiment 16 begins, deposit Germanium (Ge) layer on the Si of extension layer.Deposit subsequently the GaAs layer of extension by chemical vapour deposition (CVD).Deposit subsequently the InGaP layer of extension.Then the deposit transparent conductor deposits antireflection coating and metal grid lines subsequently.
Embodiment 18: with the polycrystalline on surface that level and smooth and cleaning are arranged, flexible Ni alloy substrate begins (can come the surface of clean substrate and make that it is more level and smooth by chemical etching and/or planarization, reactive ion etching, mechanical polishing or by electropolishing), use R.H ü hne, S.
Figure BPA00001232177800371
B.Holzapfel, " Thin biaxially textured TiN films on amorphous substratesprepared by ion-beam assisted pulsed laser deposition (by the TiN film of Assisted by Ion Beam pulsed laser deposition at the thin biaxial texture of amorphous substrate preparation); " Appl.Phys.Lett., vol.85, pp.2744-2746, the technique of 2004 instructions, use ion beam assisted depositing (IBAD), by the TiN layer of texture is arranged on the electron-beam evaporation crystallography.Then do not use the auxiliary selectable deposition of finishing the TiN of homoepitaxy of ion.By before the IBAD deposition techniques MgO layer, can deposit layer selectable amorphous or polycrystalline.Deposit subsequently the silicon layer of extension.
Embodiment 19: the experimental arrangement with embodiment 18 begins, deposit Germanium (Ge) layer on the Si of extension layer.Deposit subsequently the GaAs layer of extension by chemical vapour deposition (CVD).Deposit subsequently the InGaP layer of extension.Then the deposit transparent conductor deposits antireflection coating and metal grid lines subsequently.
Embodiment 20: begin with the instruction among the embodiment 1, form the heterostructure of NiW/TiN/Si.Then deposit the graduate semiconductor module flaggy of Si-Ge at the Si layer.4% lattice mismatch is arranged between silicon and germanium.If directly deposit at the Si layer by epitaxial deposition, this lattice mismatch applies huge stress at the Ge film so, and can cause occurring many crystal defects.Therefore, when the Si-Ge layer growth, the content of germanium is increased to gradually is almost pure germanium.The Ge layer is provided for the good Lattice Matching of the growth of GaAs.Graduate semiconductor die approach has also reduced semiconductor module flaggy and the thermal expansion mismatch between the semiconductor device layer (thermal expansion mismatch) of top.
Embodiment 21: begin with the instruction among the embodiment 1, form the heterostructure of NiW/TiN.Then be deposited on the upper graduate nitride layer of composition, with the good Lattice Matching of formation in top layer with silicon.Then at " graduate resilient coating " upper epitaxial deposition Si.Then deposit the graduate semiconductor module flaggy of Si-Ge at the Si layer.4% lattice mismatch is arranged between silicon and germanium.If directly deposit at the Si layer by epitaxial deposition, this lattice mismatch applies huge stress at the Ge film so, and can cause occurring many crystal defects.Therefore, when the Si-Ge layer growth, the content of germanium is increased to gradually is almost pure germanium.The Ge layer is provided for the good Lattice Matching of the growth of GaAs.Graduate semiconductor die approach has also reduced the semiconductor module flaggy of top and the thermal expansion mismatch between the semiconductor device layer.
Embodiment 22: the Ni-3at%W substrate with biaxial texture begins, make deposited by electron beam evaporation, sputter or chemical vapour deposition (CVD) in scope be under 300 ℃-700 ℃ the underlayer temperature on the NiW substrate the thick Y of epitaxial deposition 10-75nm 2O 3Layer.Subsequently according to Jin-Hyo Boo, S.A.Ustin and W.Ho, " Supersonic jet epitaxy of single crystalline cubic SiC thin films on Sisubstrates from t-Butyldimethylsilane (on the Si substrate, being carried out the supersonic jet extension of single crystalline cube SiC film by tert-butyl group dimethylsilane); " Thin solid Films, vol.324, pp.124-128,1998 program is used the thick cube SiC of chemical vapour deposition (CVD) deposition 10-75nm or the epitaxial loayer of β-SiC.Use subsequently chemical vapour deposition (CVD) at the Si layer of 300 ℃-900 ℃ temperature range deposition extension.
Although the GaAs layer can combine by described above with large-area, flexible substrate, GaAs also can be directly at perovskite oxide SrTiO for example 3Upper growth (see, for example, K.Eisenbeiser, R.Emrick, R.Droopad, Z.Yu, J.Finder, S.Rockwell, J.Holmes, C.Overgaard, and W.Ooms, " GaAs MESFETs Fabricated on Si SubstratesUsing a SrTiO 3Buffer Layer (uses SrTiO at the Si substrate 3The GaAsMESFET that resilient coating is made), " IEEE Electron Device Letters, Vol.23, No.6, pp.300-302,2002; Droopad R, Yu ZY, Li H, Liang Y, Overgaard C, Demkov A, Zhang XD, MooreK, Eisenbeiser K, Hu M, Curless J, Finder J, " the Development of integrated heterostructures on silicon by MBE heterostructure of MBE growth one (on the silicon by), " Journal of Crystal Growth, vol.251 (1-4), pp.638-644,2003).In this research, reported the substrate that is used for such as the epitaxially grown compliance of the compound semiconductor of GaAs.At first epitaxial growth perovskite type buffer layer, for example SrTiO on the Si single-crystal wafer 3After growth, at SrTiO 3Forming thickness between layer and the Si substrate is the SiO of about 20 dusts 2Thin amorphous layer.This thin amorphous layer as on mechanics with the elastic membrane of Si substrate uncoupling (decoupled).If also keep SrTiO 3Layer is as thin as about 50 dusts, and the final mismatch ratio 4% between GaAs layer and the Si is much lower so, if GaAs directly grows at Si.This obtains the GaAs layer of the better quality of less defective certainly.
Embodiment 23: the Ni-3at%W substrate with biaxial texture begins, make deposited by electron beam evaporation, sputter or chemical vapour deposition (CVD) in scope be under 300 ℃-700 ℃ the underlayer temperature on the NiW substrate the thick Y of epitaxial deposition 10-75nm 2O 3Layer.Under 300 ℃-700 ℃ substrate deposition temperature, use radio frequency sputtering (rf-sputtering) at Y subsequently 2O 3The thick SrTiO of epitaxial deposition 100nm on the layer 3Layer.Then use at K.Eisenbeiser R.Emrick, R.Droopad, Z.Yu, J.Finder, S.Rockwell, J.Holmes, C.Overgaard and W.Ooms, " GaAs MESFETs Fabricated on SiSubstrates Using a SrTiO 3Buffer Layer, " IEEE Electron Device Letters, Vol.23; No.6, pp.300-302,2002 and Droopad R; Yu ZY, Li H, Liang Y; OvergaardC; Demkov A, Zhang XD, Moore K; Eisenbeiser K, Hu M, Curless J, Finder J, " Development of integrated hetero structures on silicon by MBE; " Journal ofCrystal Growth, vol.251 (1-4), pp.638-644, the program of general introduction in 2003 uses molecular beam epitaxy (MBE) at SrTiO 3Heteroepitaxy deposition GaAs layer on the layer.
Embodiment 24: with the polycrystalline on surface that level and smooth and cleaning are arranged, flexible Ni alloy substrate begins (can come the surface of clean substrate and make that it is more level and smooth by chemical etching and/or planarization, reactive ion etching, mechanical polishing or by electropolishing), uses the thick SiO of magnetron sputtering deposition 50nm in room temperature 2Layer.Then in the gold thin film of high vacuum condition deposit single shaft texture.Before deposited gold film, cleaned SiO in 1 minute with 1keV Ar+ bombardment 2The surface of layer obtains strong (111) fibrous texture in the golden film.Then use 1.0-3.5MeV N+, Ne+ and Ar+ ion, to become the ion beam direction irradiation gold thin film of 35.24 angle with surface normal.Use 10 17Ion/cm 2Ion current density (ionfluence) and the target current in the scope of 10-100nA scope, depend on ionic species.Between the light period, temperature is remained on liquid nitrogen temperature.After this program, golden film all shows texture in all directions.For the manufacture of the program of the golden film of near single general introduction (Olliges S in more detail in the prior art, Gruber P, Bardill A, Ehrler D, Carstanjen HD and Spolenak R, " Convertingpolycrystals into single crystals-Selective grain growth by high-energy ionbombardment (polycrystal is converted into monocrystalline--use the selectivity grain growth of high-energy ion bombardment); " Acta Meterialia, vol.54, pp.5393-5399).Then use reactive sputtering extension depositing TiN layer on this gold film, subsequently by CVD epitaxial deposition Si layer.This obtains the semiconductor layer that crystallography on the polycrystalline substrate has texture.
Another kind of epitaxial deposition thereon comprises that the multilayer of resilient coating and semiconductor device layer is to obtain the substrate that still has large mean grain size that high performance suitable substrate is single shaft texture.For example, know, simply by the single shaft extruding, can in a lot of metals and alloy, obtain very sharp keen single shaft texture.Single shaft texture is all arranged the axis perpendicular to substrate of all crystal grains.If improve mean grain size by annealing and/or abnormal grain growth now, so mean grain size can become very large and at diameter above 100 microns.As long as grain size is larger than semi-conductive recombination length, semiconductor layer will not be subjected to spread from substrate the impact of the crystal boundary the semiconductor layer basically so.When substrate itself be non-orientation and polycrystalline or amorphous the time, also can in resilient coating, give the strong single shaft texture of large grain size.This can be by abnormal grain growth (for example, with reference to prior art J.M.E.Harper, J.Gupta, D.A.Smith, J.W.Chang, K.L.Holloway, D.P.Tracey and D.B.Knorr, " Crystallographic texture change during abnormal grain growth inCu-Co thin films (the crystallography texture during the abnormal grain growth in the Cu-Co film changes); " Appl.Phys.Lett, vol.65, pp.177-179,1994) or the grain growth by Ions Bombardment (for example, with reference to prior art T.Ohmi, T.Saito, M.Otsuki, T.Shibuta and T.Nitta, " Formation of copper thin films by a low kinetic energy particle process (forming the copper film by low kinetic energy particle technique), " J.of Electrochemical Soc, vol.138, pp.1089-1097,1991) finish.In all these situations, in fact device has " part " of large grain size three axle texture is arranged.This photovoltaic cell that will cause having the efficient similar to the efficient of photovoltaic cell that basically is monocrystalline on length dimension greater than the biaxial texture for the manufacture of the part of the semi-conductive recombination length of polycrystalline device layer will not be because crystal boundary will affect performance.
Can use a lot of technology to carry out the deposition of semiconductor layer.Many summaries that obtained recently in these technology (are seen, for example, Michelle J.McCann, Kylie R.Catchpole, Klaus J.Weber, Andrew W.Blakers, " A review of thin-film crystalline silicon for solar cell applications.Part 1:Native substrates, " Solar Energy Materials and SolarCells, the 68th volume, the 2nd phase, May calendar year 2001,135-171 page or leaf; Kylie R.Catchpole, Michelle J.McCann, Klaus J.Weber and Andrew W.Blakers, " A review ofthin-film crystalline silicon for solar cell applications.Part 2:Foreignsubstrates ", Solar Energy Materials and Solar Cells, the 68th volume, the 2nd phase, May calendar year 2001, the 173-215 page or leaf).In addition, any preparation technology in low temperature also all receives publicity, because it will further reduce the phase counterdiffusion of element from the metal/alloy substrate to semiconductor device layer.Having explored many preparation technology in low temperature for Si (sees, for example, Lars Oberbeck, Jan Schmidt, Thomas A.Wagner and RaIf B.Bergman, " High rate deposition of epitaxiallayers for efficient low-temperature thin film epitaxial silicon solar cells (high rate deposition of the epitaxial loayer of high efficient cryogenic thin film epitaxy silicon solar cell); " Progress inPhotovoltaics:Research and Applications, vol.9, pp.333-340,2001; J.Carabe and J.J.Gandia, " Thin-film-silicon Solar Cells (thin film silicon solar cell), " OPTO-Electronics Review, vol.12, pp.1-6,2004; S Summers, H S Reehal and G H Shirkoohi, " The effects of varying plasma parameters on silicon thin filmgrowth by ECR plasma CVD (different plasma parameters is to using the silicon thin film affects on the growth of ECR plasma CVD); " J.Phys.D:Appl.Phys.Vol.34, pp.2782-2791,2001; Thomas A.Wagner, Ph.D thesis, " Low temperature silicon epitaxy:Defects and electronic properties (Low-temperature Si epitaxy: defective and electronic property); " Institut furPhysikalische Elektronik der Universit at Stuttgart (Universitaet Stuttgart physical electronic institute journal), 2003; Hattangady, S.V., Posthill, J.B., Fountain, G.G., Rudder R.A., Mantini and M.J., Markunas, R.J., " 300 ℃ of withremote plasma of Epitaxial silicon deposition at processing using SiH 4/ H 2Mixtures (uses SiH at 300 ℃ 4/ H 2The epitaxial silicon deposition that mixture is processed with remote plasma), " Appl.Phys.Lett., vol.59 (3), pp.339-341,1991; Wagner, T.A., Oberbeck, L., and Bergmann, R.B., " Lowtemperature epitaxial silicon films deposited by ion-assisted deposition (by the low-temperature epitaxy silicon thin film of ion assisted deposition deposition), " Materials Science ﹠amp; EngineeringB-Solid State Materials for Advanced Technology, vol.89, pp.1-3,2002; Overbeck, L., Schmidt, J., Wagner, T.A., and Bergmann R.B., " High-ratedeposition of epitaxial layers for efficient low-temperature thin film epitaxial silicon solar cells (high rate deposition of the epitaxial loayer of high efficient cryogenic thin film epitaxy silicon solar cell); " Progress in Photovoltaics, vol.9 (5), pp.333-340,2001; Thiesen, J., Iwaniczko, E., Jones, K.M., Mahan, A., and Crandall, R., " Growth of epitaxialsilicon at low temperatures using hot-wire chemical vapor deposition (using hot line chemical vapor deposition growth epitaxial silicon under the low temperature), " Appl.Phys.Lett., vol.75 (7), pp.992-994,1999; Ohmi, T., Hashimoto, K., Morita, M., Shibata, T., " 250 ℃ of in low-energybias of Study onfurther reducing the epitaxial silicon temperature down to sputtering (and about in the low energy bias sputtering with the research of 250 ℃ of the further descending systems of epitaxial silicon temperature), " Journal of Appl.Phys., vol.69 (4), pp.2062-2071,1991).
Low temperature chemical vapor deposition (CVD) technique about the deposition that is used for semiconductor layer, hot line CVD (Qi Wang, Charles W.Teplin, Paul Stradins, Bobby To, Kim M.Jones and Howard M.Branz, " Significant improvement in silicon chemical vapordeposition epitaxy above the surface dehydrogenation temperature (the remarkable improvement of chemistry of silicones vapour deposition extension when being higher than surperficial desorption temperature); " J.of Appl.Phys., 100,093520,2006 and Charles W.Teplin, Qi Wang, Eugene Iwaniczko, Kim M.Jones, Mowafak Al-Jassim, Robert C.Reedy, Howard M.Branz, " Low-temperature silicon homoepitaxy by hot-wire chemical vapor depositionwith a Ta filament (the low temperature silicon homoepitaxy of being undertaken by the hot wire chemical vapour deposition (CVD) of using the Ta silk); " Journal of Crystal Growth 287 (2006) 414-418), the plasma assisted CVD (" Very Low Temperature Epitaxial Growth of Silicon Films for SolarCells (utmost point low-temperature epitaxy growth of the silicon fiml of solar cell); " Jap.J.of Appl.Phys.46,12,7612-7618,2007), the ECR plasma CVD, applying plasma CVD (mesoplasma CVD) (Jose Mario A.Diaz, Munetaka Sawayanagi, Makoto Kambara, andToyonobu Yoshida, " Electrical Properties of Thick Epitaxial Silicon FilmsDeposited at High Rates and Low Temperatures by Mesoplasma ChemicalVapor Deposition (passing through the thick epitaxial silicon film of ionic medium chemical vapour deposition (CVD) deposition with two-forty and low temperature); " Japanese Journal of Applied Physics, Vol.46, No.8A, 2007, pp.5315-5317) and gas jet plasma CVD (R.G.Sharafutdinov, V.M.Karsten, S.Ya.Khmel, A.G.Cherkov, A.K.Gutakovskii, L.D.Pokrovsky and O.I.Semenova, " Epitaxial silicon films deposited at high rates by gas-jet electron beam plasma CVD (by the epitaxial silicon film of gas jet electron beam plasma CVD with high rate deposition); " Surface and Coatings Technology, the 174-175 volume, in September, 2003-October, the 1178-1181 page or leaf), plasma CVD (the Yagi of electron-beam excitation, Y., Motegi, H., Ohshita, Y., Kojima, N., Yamaguchi, M., " High-speed growth of silicon thinfilms by EBEP-CVD using Si 2H 6(by using Si 2H 6EBEP-CVD high-speed rapid growth silicon thin film), " the 3rd photovoltaic energy conversion international conference, 2003, the 2 volumes, 12-16 phase, in May, 2003,1667-1670 page or leaf Vol.2) receive publicity.
Also can use ex situ process deposits semiconductor layer.In this technique, the precursor film of depositing semiconductor layers at first, the semiconductor layer epitaxial crystallization (is seen, for example, title is the international patent application WO 2004/033769 A1 number of " Fabricationmethod for crystalline semiconductor on foreign substrates (be used for foreign substrate make crystalline method for semiconductor) "; Ngo Duong Sinh, Gudrun Andra, Fritz Falk, Ekkehart Ose, Joachim Bergmann, " Optimization of Layered Laser Crystallization for Thin-Film CrystallineSilicon Solar Cells (being used for the optimization of the layering laser crystallization of film crystal silicon solar cell), " Solar Energy Materials; Solar Cells 74 (2002), 295-303; Nickel, N.H.; Brendel, K.; Saleh, R., " Laser crystallization of hydrogenated amorphoussilicon (laser crystallization of amorphous silicon hydride); " Physica status solidi.C.Conferences andcritical reviews, vol.1, no5, pp.1154-1168,2004; J.B.Boyce, J.P.Lu,, J.Ho, R.A.Street, K.van Schuylenbergh and Y.Wang, " Pulsed laser crystallizationof amorphous silicon for polysilicon flat panel imagers (being used for the pulse laser crystallization of the amorphous silicon of polysilicon flat panel imaging instrument), " Journal of Non-Crystalline Solids, Vol.299-302, pp.731-735,2002; Lulli, G.; Merli, P.G.; Antisari, M.Vittori, " Solid-phase epitaxy of amorphous silicon induced by electron irradiation atroom temperature (solid phase epitaxy of the amorphous silicon of at room temperature being induced by electron radiation); " Physical Review B (Condensed Matter), the 36th volume, the 15th phase, on November 15th, 1987, pp.8038-8042; Mohadjeri, B.; Linnros, J.; Svensson, B.G.; Ostling, M., " Nickel-enhanced solid-phase epitaxial regrowth of amorphous silicon (solid phase epitaxial regrowth with the nickel enhancing of amorphous silicon); " Physical Review Letters, the 68th volume, the 12nd phase, on March 23rd, 1992, pp.1872-1875; Yann Civale, Lis K.Nanver, PeterHadley, Egbert J.G.Goudena, and Hugo Schellevis, " Sub-500 ℃ of Solid-Phase Epitaxy of Ultra-Abrupt p+-Silicon Elevated Contacts and Diodes (super sudden change silicon top layer contactor and diode in the solid phase epitaxy below 500 ℃), " IEEE Electron DeviceLetters, Vol.27,2006; Cline H.E., " A single crystal silicon thin-film formed bysecondary recrystallization (by the monocrystalline silicon thin film of secondary recrystallization formation); " Journal ofAppl.Phys., vol.55 (12), pp.4392-4397,1984; Santos, P.V.; Trampert, A.; Dondeo, F.; Comedi, D.; Zhu, H.J.; Ploog, K.H.; Zanatta, A.R.; Chambouleyron, I. " Epitaxial pulsed laser crystallization of amorphousgermanium on GaAs (the extension pulse laser crystallization of amorphous germanium on GaAs); " Journal ofApplied Physics, Vol.90, pp.2575-2581,2001; T.Sameshima, H.Watakabe, H.Kanno, T.Sadoh and M.Miyao, " Pulsed laser crystallization ofsilicon-germanium films (the pulse laser crystallization of silicon-germanium film), " Thin Solid Films Vol.487 pp.67-71,2005; R.D.Ott, P.Kadolkar, C.A.Blue, A.C.Cole and G.B.Thompson, " The Pulse Thermal Processing of Nanocrystalline SiliconThin-Films (pulse heat of Nano silicon-crystal thin film is processed), " JOM, vol.56, pp.45-47, Oct., 2004).
Cu (In, Ga) Se based on polycrystalline 2(CIGS) solar cell of film also is subject to greatly paying close attention to, and verified laboratory scale 19.2% record efficiency.The expansion scale of this technique on the substrate of flexibility continues to carry out in industry, yet the efficient that obtains in process of production is much lower.Even using the high efficiency solar cell of CIGS thin film fabrication also is polycrystalline, the mean grain size of the 2 μ m that have an appointment.Up to the present, definite effect or the impact of crystal boundary in the CIGS solar cell not yet obtains a lot of confirmations.Propose, oxygen can passivation originally will be the crystal boundary that is harmful to (see, for example, D.Cahen and R.Noufi, " Defect chemical explanation for theeffect of air anneal on CdS/CuInSe 2Solar cell performance (anneals to CdS/CuInSe for air 2The defect chemistry of the impact of solar cell properties is explained), " Appl.Phys.Lett., vol.54, pp.558-560,1989).Also propose, sodium (Na) to this useful oxidation of the diffusing catalyst of crystal boundary (see, for example, L.Kronik, D.Cahen, and H.W.Schock, " Effects ofSodium on Polycrystalline Cu (In, Ga) Se 2(sodium is to polycrystalline Cu (In, Ga) Se for and Its Solar Cell Performance 2Impact with its solar cell properties), " Advanced Materials, vol.10, pp.31-36,1999).Also propose, (see in that the compound electric charge carrier of the compound electric charge carrier of grain boundaries and block is different, for example, M.J.Romero, K.Ramanathan, M.A.Contreras, M. M.Al-Jassim, R.Noufi, and P.Sheldon, " Cathodoluminescence ofCu (In, Ga) Se 2Thin films used in high-efficiency solar cells (Cu (In, the Ga) Se that is used for high efficiency solar cell 2The cathodoluminescence of film), " Appl.Phys.Lett., vol.83, pp.4770-4772,2003).Propose, owing at the wider breach of grain boundaries, (see, for example Persson C in the passivation (intrinsic passivation) of grain boundaries generation intrinsic, Zunger A., " Anomalous grain boundary physics in polycrystalline CuInSe 2: the existenceof a hole barrier (polycrystalline CuInSe 2In unusual crystal boundary physics: the existence of hole barrier), " Phys.Rev.Lett.vol.91, pp.266401-266406,2003).Propose, depending on Ga content at the useful local built-in potential (built-in potential) of grain boundaries (sees, for example, C.-S.Jiang, R.Noufi, K.Ramanathan, J.A.AbuShama, H.R.Moutinho and M.M.Al-Jassim, " Local Built-in Potential on Grain Boundary of Cu (In, Ga) Se 2Thin Films (Cu (In, Ga) Se 2Local built-in potential on the crystal boundary of film), " meeting paper, NREL/CP-520-36981,2005).Report, there are the minimizing of Cu content and this less adverse effect that causes crystal boundary (to see at grain boundaries, for example, M.J.Hetzer, Y.M.Strzhemechny, M.Gao, M.A.Contreras, A.Zunger and L.J.Brillson, " Direct observation ofcopper depletion and potential changes at copper indium gallium diselenidegrain boundaries (for the direct observation of and potential change most at the copper loss of copper indium callium diselenide (CIGS) compound grain boundaries); " Appl.Phys.Lett.vol.86, pp.162105-162107,2005).Also propose, crystallography texture also is important for the solar cell based on CIGS of greater efficiency, (see, for example, S.Chaisitsak, A.Yamada and M.Konagai, " Preferred Orientation Controlof Cu (In 1-xGa x) Se 2(x ≈ 0.28) Thin Films and Its Influence on Solar CellCharacteristics is (to Cu (In 1-xGa x) Se 2The control of the preferred orientation of (x ≈ 0.28) film with and on the impact of characteristic of solar cell), " Jpn.J.Appl.Phys.vol.41, pp.507-513,2002).Gather, more than these are researched and proposed, although crystal boundary may be harmful to usually in based on the solar cell of CIGS very much, importantly which kind of composition crystal boundary is, to control its electronically active.This need to be for the very good control of grain boundary structure, and this is impossible in the CIGS film of random texture or bad single shaft texture.If control the orientation of all CIGS crystal grain by making the battery that texture is arranged on the crystallography, then aborning (in run after run), the composition of CIGS film crystal boundary will be identical.This will allow people to make the large-area battery based on CIGS of very high efficient in industrial setting, and this is impossible at present.
Figure 23 shows the version that can be used for metal or alloy substrate of the present invention.Figure 23 A shows the Utopian schematic diagram with cross-sectional form of compound substrate, described compound substrate contains and has or not bottom crystallography texture or that do not arrange, and having has top surface texture or that arrange on the crystallography, so that all crystal grains in this layer is arranged in 10 degree in all directions.Figure 23 B shows the Utopian schematic diagram with cross-sectional form of compound substrate, described compound substrate contains and has or not center crystallography texture or that do not arrange, and having has top surface and basal surface texture or that arrange on the crystallography, so that all crystal grains in this layer is arranged in 10 degree in all directions.
Other application of the electronic instrument of the flexibility that the present invention relates to or circuit be flexible, the space is saved or production constraint limited rigid circuit board or manually in the various application of the applicability of wiring as attachment.The general application of another of flexible circuit is in computer keyboard is made; Current most of keyboards of making use flexible circuit as switch matrix.
In electronics industry, usually carry out the manufacturing in the mode of extension on substrate of device layer or film, be used for many application, for example relate to those application of superconductor, semiconductor, magnetic material and electrooptical material.In many in these are used, by the oldered array of combining nano point, nanometer rods or nano particle second-phase material, can improve significantly or the performance of enhance device layer.In other cases, the combination of the oldered array of nano dot, nanometer rods or nano particle second-phase material just can not made in this way can not be getable new and character novelty.In addition, in many in these are used, need large-area and long device layer.This can be by containing nano dot, nanometer rods or nano particle second-phase material the epitaxial growth of device layer on the substrate of biaxial texture of oldered array realize.For example, in the high-temperature superconductor field, can use sheet metal strip, to form the extension superconducting layer with long (km) length by the epitaxial growth on the substrate of made biaxial texture, be used for the application such as the low-loss power line.Can use the texturing of heat engine tool, substrate by texture is arranged on ion beam assisted depositing or the crystallography by the manufacturing of inclination substrate deposition manufacture of intraocular (patent is incorporated into way of reference, illustrates in the instruction content about the mode of the substrate making above).
In preferred embodiment of the present invention, at the growing period of the device layer self-assembled nanometer point in conjunction with the second-phase material.This can carry out with the in-situ deposition technology that high temperature carries out that is deposited on of many wherein films.Original position film deposition technique comprises pulse laser ablation (PLD), chemical vapour deposition (CVD) (CVD), molecular chemistry vapour deposition (MOCVD), direct current (DC) or radio frequency (rf) sputter, electron beam coevaporation, hot coevaporation and pulsed electron deposition (PED).
Owing to the unbecoming strain (misfit strain) between second-phase and the base film (matrix film), formed self-assembled nanometer point and/or the nanometer rods of second-phase material.When the lattice parameter of the lattice parameter of the epitaxial film of growing and second-phase material not simultaneously, lattice mismatch occurs, obtain unbecoming strain.Therefore nano dot and/or nanometer rods self self assembly is to minimize strain and to minimize the energy of composite membrane.The composition of the specific sedimentary condition of using at the film growing period and the second-phase of institute's combination or size, shape and the orientation of volume fraction control nano dot and/or nanometer rods.The lattice mismatch greater than 3% that has between the material of film matrix and formation nano dot and/or nanometer rods is preferred.Be equal to or higher than in the situation of this lattice mismatch, obtaining significant strain, and obtaining the clear and definite ordered arrangement of nano dot and nanometer rods.
In addition, carrying out independent or in device layer, be another important benefit of the present invention in conjunction with such self-assembled nanometer point of second-phase material and/or the ability of nanometer rods during simultaneously deposition.This has reduced the complexity of the device layer of making such novelty significantly.Specific implementation of the present invention is consisting of YBa 2Cu 3O x(YBCO) obtain confirmation in the high temperature superconducting film, in described high temperature superconducting film, consisted of BaZrO 3Use PLD from the single target combination of the mixture of the nanometer powder that contains YBCO and BZO between second-phase nano dot (BZO) and nanometer rods depositional stage at the same time.
Embodiment 23: by carrying out laser ablation in conjunction with self-assembled nanometer point and the nanometer rods of non-superconducting phase from the single target that comprises YBCO powder and the mixture of selected non-superconducting nano particle mutually.Material is BZO, CaZrO for example 3(CZO), YSZ, Ba xSr 1-xTiO 3(BST) etc. nano particle can for example Sigma-Aldrich be commercially available from supplier.There is these scope to mix well with the YBCO powder by mechanical mixture at the nano particle of the sharp keen particle size distribution of 10-100nm, then colds pressing to form initial target.Then in the oxygen that flows at 950 ℃ of sintering targets.Then target is installed on the target holder in pulsed laser deposition (PLD) experimental facilities.Important technically have Ni-5at%W (50 μ m)/Y 2O 3(75nm)/YSZ (75nm)/CeO 2Deposit on rolling auxiliary biaxial texture substrate (RABiTS) substrate of formation (75nm).Use XeCl (308nm) excimer laser LPX 305, with the repetition rate of 10Hz, 790 ℃ substrate deposition temperature and the partial pressure of oxygen of 120mTorr, carry out the PLD deposition.
By the preformed YBCO micron powder of mechanical mixture and commodity BZO nanometer powder, colding pressing subsequently prepares the PLD target with sintering to form target.By the processing and manufacturing of heat engine tool and by the Grown film of the biaxial texture of the near single that forms Ni-3at%W or Ni-5at%W.Before the growth of multiple device layer, deposit Y at the metal alloy substrate 2O 3, yttria-stabilized zirconia (yttria stabilized zirconia) (YSZ) and CeO 2The multi-buffering-layer of extension.Substrate is installed on the heater block, and handle component is heated to the depositing temperature that presets.Measure the Optimal Temperature of film growth by normal experiment.Also measure to be used for optimal distance between the substrate of the target of PLD and deposited film by normal experiment.Also be determined at the depositional stage chien shih in order to form the background gas pressure that wherein YBCO and BZO are stable zones (regime) by normal experiment.Figure 24 shows the thick YBa of 0.2 μ m of the self-assembled nanometer point of epitaxially grown BZO on the substrate of the biaxial texture of the buffering that extension is arranged 2Cu 3O x(YBCO) cross section transmission electron microscopy (TEM) image of layer.In the YBCO layer, can see BaZrO 3The post of self-assembled nanometer point (BZO).The ab face that post represents perpendicular to the parallel lattice fringe by in the YBCO layer of YBCO, and be parallel to the c-axis of YBCO.Black arrow among the figure shows some the position in the post of self-assembled nanometer point of BZO.Figure 25 shows the schematic diagram of cross section of the structure of this expectation in the mode of more summarizing.There is shown crystallography at the self-assembled nanometer point that contains the second-phase material and have the epitaxial device film on the substrate of texture.In this case, all posts of self-assembled nanometer point are all arranged well in the direction perpendicular to substrate.Figure 26 shows crystallography at the self-assembled nanometer point that contains the second-phase material and has the schematic diagram of the epitaxial device film on the substrate of texture, and wherein the post of self-assembled nanometer point tilts well with respect to the direction perpendicular to substrate.Figure 27 shows crystallography at the self-assembled nanometer point that contains the second-phase material and has the schematic diagram of the epitaxial device film on the substrate of texture, and wherein self-assembled nanometer point is not smooth but crooked.The combination of the effect shown in Figure 25,26 and 27 also can occur at the film growing period.
Because the present invention obtains having on the crystallography device texture or near single, their performance is good.Yet the present invention also obtains lower-cost device.For example, in the typical production cost of crystal silicon solar energy battery module is analyzed, the cut-out of Si substrate, Battery disposal and module assembled account for module total cost 70%.Use the present invention to make solar cell, do not need to cut off and module assembled.Module assembled relates to Si wafers of much having processed is assembled into module, its account for individually solar module total cost 35%.In the present invention, can use the continuous or static very large-area solar cell that texture is arranged of process manufacturing.Then be suitably to the designs pattern, in large-area module, to divide various batteries.
Can be used for being selected from according to electronic device of the present invention comprise photovoltaic device, flat-panel monitor, thermo-photovoltaic device, ferro-electric device, LED device, computer hard disc driver device, based on the device of magnetic resistance, the application of group of device, nonvolatile memory device, dielectric devices, thermoelectric device and quantum dot laser spare based on luminescence generated by light.In preferred embodiments, electronic device has the area greater than 50 square inches.Again further in the preferred embodiment, electronic device has the area greater than 113 square inches.Can comprise at least a device that comprises following group that is selected from according to electronic device of the present invention: Double-end device, for example diode; Three termination devices, for example transistor, thyristor or rectifier; And multiterminal head device, for example microprocessor, random access memory, read-only memory or charge coupled device.
Be to be understood that, embodiment described herein and embodiment only are used for illustrative purpose, and various modifications of carrying out according to these embodiment and embodiment or change and will be proposed and be included in the application's the spirit and scope by those skilled in the art.The present invention can take other particular forms, and does not depart from the attribute of spirit of the present invention or essence.

Claims (65)

1. polycrystalline electronic device comprises:
A. metal or alloy substrate flexible, annealing, its have corresponding to 100}＜100〉and primary recrystallization texture or secondary recrystallization texture, have inlaying or sharpness less than the texture of 10 degree;
B. at least one resilient coating on described substrate, described at least one resilient coating be selected from comprise metal, alloy, nitride, boride, oxide, fluoride, carbide, silicide, with the intermetallic alloy of germanium or the group of its combination, described at least one resilient coating also have corresponding to 100}＜100〉and crystallography texture or 45 ° of rotations 100}＜100〉texture, and have the inlaying or sharpness of texture less than 10 degree; And
C. at least one epitaxial semiconductor device layers of the electronic material on the resilient coating of top, described at least one epitaxial semiconductor device layers comprises: indirect gap semiconductor, direct gap semiconductor, multiband semiconductor or its combination; Wherein, described at least one epitaxial semiconductor device layers have 100}＜100〉and texture or have the anglec of rotation rotation 100}＜100〉texture.
2. electronic device according to claim 1, wherein, described indirect gap semiconductor is Si, Ge or GaP.
3. electronic device according to claim 1, wherein, described direct gap semiconductor is CdTe, CuInGaSe 2(CIGS), GaAs, AlGaAs, GaInP or AIInP.
4. electronic device according to claim 1, wherein, described multiband semiconductor is II-O-VI material or III-N-V material.
5. electronic device according to claim 4, wherein, described II-O-VI material is Zn 1-yMn yO xTe 1-x
6. electronic device according to claim 4, wherein, described III-N-V material is GaN xAs 1-x-yP y
7. each described electronic device according to claim 1-6, wherein, described at least one epitaxial semiconductor device layers comprises be used to trace doped dose that obtains needed N-shaped or p-type semiconductor property.
8. electronic device according to claim 1, wherein, described epitaxial semiconductor device layers is the compound semiconductor that mainly is comprised of two or more elements not of the same clan from the periodic table of elements, comprises the compound of III-th family and V family, and the compound of II family and VI family.
9. electronic device according to claim 8, wherein, element from described III-th family is selected from B, Al, Ga and In, element from described V family is selected from N, P, As, Sb and Bi, element from described II family is selected from Zn, Cd and Hg, and is selected from O, S, Se and Te from the element of described VI family.
10. according to claim 8 or 9 described electronic devices, wherein, described compound semiconductor be binary and comprise compound from described III-th family and V family.
11. electronic device according to claim 10, wherein, described compound semiconductor is AlN, AlP, AlAs, GaN, GaP, GaAs, InP, InAs or InSb.
12. according to claim 8 or 9 described electronic devices, wherein, described compound semiconductor be binary and comprise compound from described II family and VI family.
13. electronic device according to claim 12, wherein, described compound semiconductor is ZnS, ZnSe, ZnTe, CdTe or HgTe.
14. according to claim 8 or 9 described electronic devices, wherein, described compound semiconductor is ternary.
15. electronic device according to claim 14, wherein, described compound semiconductor is InGaAs, AlGaAs, InGaN or CdHgTe.
16. according to claim 8 or 9 described electronic devices, wherein, described compound semiconductor is quaternary.
17. electronic device according to claim 16, wherein, described compound semiconductor is InGaAsP or AlInGaP.
18. electronic device according to claim 1, wherein, described epitaxial semiconductor device layers is corresponding to elemental semiconductor or the alloy of the element in the identical family, or comprises the compound semiconductor of element of IB family, group III A and the VIA family of the periodic table of elements.
19. electronic device according to claim 18, wherein, elemental semiconductor or the alloy of the element in the described identical family are SiC or SiGe.
20. electronic device according to claim 18, wherein, the compound semiconductor of the element of described IB family, group III A and the VIA family that comprises the periodic table of elements is the alloy of copper, indium, gallium, aluminium, selenium and sulphur.
21. electronic device according to claim 1, wherein, described substrate has the mean grain size greater than 100 microns.
22. electronic device according to claim 1, wherein, described substrate have rotation 100}＜100〉texture, have the anglec of rotation less than 45 °.
23. electronic device according to claim 1, wherein, the outer texture of the face of described substrate take less than 5 ° inlay or FWHM as feature.
24. electronic device according to claim 1, wherein, described resilient coating has the rock salt crystal structure that is selected from the crystal structure that comprises following group: formula AN or AO, and wherein A is that metal and N and O are corresponding to nitrogen and oxygen; Formula ABO 3Perovskite crystal structure, wherein A and B are that metal and O are oxygen; Formula A 2B 2O 7The pyrochlore crystal structure, wherein A and B are that metal and O are oxygen; And formula A 2O 3The bixbyite crystal structure, wherein A is that metal and O are oxygen.
25. electronic device according to claim 1, wherein, described resilient coating has and is selected from the chemical formula that comprises following group: have formula A xB 1-xO and A xB 1-xThe rock salt crystal structure of the mixing of N, wherein A is different metals with B; Has formula A xB 1-xN yO 1-yThe oxynitride of mixing, wherein A is different metals with B; Has formula (A xB 1-x) 2O 3The bixbyite structure of mixing, wherein A is different metals with B; Has formula (A xA ' 1-x) BO 3, (A xA ' 1-x) (B yB ' 1-y) O 3The perovskite of mixing, wherein A, A ', B and B ' are different metals; And has a formula (A xA ' 1-x) 2B 2O 7, (A xA ' 1-x) 2(B yB ' 1-y) 2O 7The pyrochlore of mixing, wherein A, A ', B and B ' are different metals.
26. electronic device according to claim 1, wherein, described at least one resilient coating is oxide buffer layer, and described oxide buffer layer is selected from and comprises following group: γ-Al 2O 3(Al 2O 3Cube form); Perovskite; Adulterated with Ca and Ti ore; The layering perovskite; Pyrochlore; Fluorite; Rock salt oxide and spinelle.
27. electronic device according to claim 26, wherein, described perovskite is SrTiO 3, (Sr, Nb) TiO 3, BaTiO 3, (Ba, Ca) TiO 3, LaMnO 3Or LaAlO 3
28. electronic device according to claim 26, wherein, described adulterated with Ca and Ti ore is (La, Sr) MnO 3Or (La, Ca) MnO 3
29. electronic device according to claim 26, wherein, described layering perovskite is Bi 4Ti 3O 12
30. electronic device according to claim 26, wherein, described pyrochlore is La 2Zr 2O 7, Ca 2Zr 2O 7Or Gd 2Zr 2O 7
31. electronic device according to claim 26, wherein, described fluorite is Y 2O 3Or YSZ.
32. electronic device according to claim 26, wherein, described rock salt oxide is MgO.
33. electronic device according to claim 26, wherein, described spinelle is MgAl 2O 4
34. electronic device according to claim 1, wherein, described at least one resilient coating be the silicide resilient coating or with the intermetallic alloy of germanium, described silicide resilient coating or with the intermetallic alloy of germanium corresponding to having chemical formula MSi or MSi 2, MSi 3, MGe or MGe 2, MGe 3Layer, wherein M is metal.
35. electronic device according to claim 34, wherein, described metal is Ni, Cu, Fe, Ir or Co.
36. electronic device according to claim 1, wherein, described at least one resilient coating is the carbide resilient coating, and described carbide resilient coating is corresponding to cube form of SiC.
37. electronic device according to claim 1, wherein, described resilient coating is " graduate resilient coating on forming ", comprises the multi-buffer layer with different lattice parameters, to provide good Lattice Matching to described epitaxial semiconductor device layers.
38. electronic device according to claim 1, also be included in the semiconductor module flaggy of last resilient coating top, to provide good Lattice Matching to described epitaxial semiconductor device layers, wherein, described resilient coating is " graduate resilient coating on forming ", comprise the multi-buffer layer with different lattice parameters, to provide good Lattice Matching to described semiconductor module flaggy.
39. electronic device according to claim 1, wherein, described at least one resilient coating conducts electricity.
40. electronic device according to claim 1 also is included in the semiconductor module flaggy of last resilient coating top, to provide good Lattice Matching to described epitaxial semiconductor device layers.
41. described electronic device according to claim 40, wherein, described semiconductor module flaggy is " graduate semiconductor die on the forming " layer with multilayer of different lattice parameters, to provide good Lattice Matching to described epitaxial semiconductor device layers.
42. electronic device according to claim 1, wherein, described substrate is selected from the group that comprises Cu, Ni, Al, Mo, Nb and Fe and alloy thereof.
43. electronic device according to claim 1, wherein, described resilient coating is buffer stack.
44. described electronic device according to claim 43, wherein, described buffer stack is selected from multilayer, the Y that comprises a cube nitride layer, MgO/ cube nitride 2O 3The multilayer of/YSZ/ cube of nitride, Y 2O 3Multilayer, the Y of the multilayer of/YSZ/MgO/ cube of nitride, cubic oxide thing layer, MgO/ cubic oxide thing 2O 3Multilayer and the Y of/YSZ/ cubic oxide thing 2O 3The resilient coating structure of the multilayer of/YSZ/MgO/ cubic oxide thing.
45. described electronic device according to claim 44, wherein, described cube of nitride layer is TiN.
46. described electronic device according to claim 44, wherein, described cubic oxide thing layer is γ-Al 2O 3
47. described electronic device according to claim 44, wherein, described cube of nitride is graduate nitride layer on forming, to provide good Lattice Matching to described semiconductor device or template layer.
48. described electronic device according to claim 44, wherein, described cubic oxide thing is graduate oxide skin(coating) on forming, to provide good Lattice Matching to described semiconductor device or template layer.
49. electronic device according to claim 1, wherein, described at least one resilient coating be polycrystalline with crystallography on arrange, and be the result of the reaction between two adjacent layers in the device stack.
50. electronic device according to claim 1, wherein, described metal or alloy substrate is the MULTILAYER COMPOSITE substrate, wherein only described top surface have corresponding to 100}＜100〉and crystallography texture and less than 10 ° inlay.
51. electronic device according to claim 1, wherein, described metal or alloy substrate is the MULTILAYER COMPOSITE substrate, wherein only top layer and bottom have corresponding to 100}＜100〉and crystallography texture and less than 10 ° inlay.
52. electronic device according to claim 1, wherein, at least a portion in the described substrate comprises the Ni base alloy of the W content with 3-9 atomic percentage.
53. electronic device according to claim 1, wherein, described electronic device be selected from comprise photovoltaic device, flat-panel monitor, thermo-photovoltaic device, ferro-electric device, LED device, computer hard disc driver device, based on the device of magnetic resistance, the group of device, nonvolatile memory device, dielectric devices, thermoelectric device and quantum dot laser spare based on luminescence generated by light.
54. electronic device according to claim 1, wherein, described electronic device comprises at least a device that comprises following group that is selected from: the Double-end device; Three termination devices and multiterminal head device.
55. 4 described electronic devices according to claim 5, wherein, described Double-end device is diode.
56. 4 described electronic devices according to claim 5, wherein, described three termination devices are transistor, thyristor or rectifier.
57. 4 described electronic devices according to claim 5, wherein, described multiterminal head device is microprocessor, random access memory, read-only memory or charge coupled device.
58. electronic device according to claim 1, wherein, described electronic device forms the parts of dull and stereotyped active matrix liquid crystal display (AMLCD) or dull and stereotyped active-matrix Organic Light Emitting Diode (AMOLED) display.
59. electronic device according to claim 1, wherein, described electronic device layer is the photovoltaic device that comprises that at least one pn that is parallel to substrate surface ties.
60. 9 described electronic devices according to claim 5, wherein, described photovoltaic device comprises having at least two multijunction cells that are parallel to the pn knot of described substrate surface.
61. 0 described electronic device according to claim 6, wherein, described photovoltaic device comprises having three multijunction cells that are parallel to the pn knot of described substrate surface.
62. 9 described electronic devices according to claim 5, wherein, the conversion efficiency of described photovoltaic device is greater than 13%.
63. 9 described electronic devices according to claim 5, wherein, the conversion efficiency of described photovoltaic device is greater than 1 5%.
64. electronic device according to claim 1, wherein, described electronic device layer is comprised of the nano dot of the arrangement that another crystallization different from described device layer forms, and wherein the diameter of nano dot is in the scope of 2-1 00 nanometer.
65. 4 described electronic devices according to claim 6, wherein, described nano dot 80% with normal arrangement in 60 degree of described device layer.
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