CN101981685B - [100] or [110] aligned, semiconductor-based, large-area, flexible, electronic devices - Google Patents

[100] or [110] aligned, semiconductor-based, large-area, flexible, electronic devices Download PDF

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CN101981685B
CN101981685B CN200880128188.0A CN200880128188A CN101981685B CN 101981685 B CN101981685 B CN 101981685B CN 200880128188 A CN200880128188 A CN 200880128188A CN 101981685 B CN101981685 B CN 101981685B
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electronic devices
layer
devices according
texture
semiconductor
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CN101981685A (en
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阿米特·戈亚尔
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Abstract

Novel articles and methods to fabricate the same resulting in flexible, large-area, [100] or [110] textured, semiconductor-based, electronic devices are disclosed. Potential applications of resulting articles are in areas of photovoltaic devices, flat-panel displays, thermophotovoltaic devices, ferroelectric devices, light emitting diode devices,, computer hard disc drive devices, magnetoresistance based devices, photoluminescence based devices, non-volatile memory devices, dielectric devices, thermoelectric devices and quantum dot laser devices.

Description

[100] or [110] large-area flexible electronic device of based semiconductor of arranging
About the research of federal funding or the statement of exploitation
The present invention is making according under the governmental support of No. DE-AC05-000R22725th, the contract of being rewarded by USDOE.Government enjoys some right in the present invention.
Invention field
The manufacture that the present invention relates to the high performance electronics comprising various types of semiconductor and the goods obtained thus.
Background of invention
This international application is the U.S. Patent application the 12/011st corresponding to submitting on January 28th, 2008, the PCT application of No. 454.U.S. Patent application the 12/011st, No. 454 is the U.S. Patent application the 11/715th submitted on March 8th, 2007, the part continuation application of No. 047.International Application Serial No. PCT/US2008/002944 and U.S. Patent application the 11/715th, be correlated with for No. 047.U.S. Patent application the 12/011st, No. 454 or undocumented U.S. Patent application the 11/498th, the part continuation application of No. 120.
The electronic device of based semiconductor, such as diode, transistor and integrated circuit can be seen everywhere.For these application in many, if the cost of device is significantly reduced, so it is contemplated that more application.Particularly for photovoltaic application or Application of Solar Energy, for all transducers, and for other applications, such as ferro-electric device, the storage application for light-emitting diode, the such as computer hard disc driver of solid-state illumination application, the device based on magnetic resistance, the device based on luminescence generated by light, nonvolatile memory application, dielectric devices, thermoelectric device, really so.
The future in this world that the use of regenerative resource is lived just wherein for us is necessary.Solar energy has unlimited potentiality meeting on global energy requirement.But in the past twenty years, the rosy prospect of solar energy fails to realize all the time.This mainly due to the solar cell produced now cannot gratifying cost performance.Further technological innovation have realize for reduce price with make solar energy than fossil fuel cheap or on cost the necessary potentiality that with coml break through economically equal to fossil fuel.
Film photovoltaic cell (PV) has significant advantage relative to traditional crystal Si battery based on wafer.The major advantage of film is material lower compared with single crystal technology and manufacturing cost and higher productivity ratio.Film uses 1/20 to 1/100 of the material required for crystal Si PV, and looks the production that the cost that is suitable for more automation is lower.At present, three kinds of membrane technologies are obtaining the very big concern from extensive PV industry: amorphous Si, CuInSe 2and CdTe.In most of the cases, module efficiency and battery efficiency closely related, have the loss (~ 10%) of trace that some loss and some ohmic loss due to effective area cause.In order to raise the efficiency further and in order to the renewable place of production high efficiency battery of based thin film can be manufactured, need the micro-structural feature controlling limiting performance.Although remain unclear for the understanding completely of the micro-structural feature of limiting performance, reasonably quite it is clear that, in crystal boundary, crystal grain, recombining of defect and impurity place is crucial.In order to minimize the effect of crystal boundary, the film having large grain size or the only GB of low energy is an object.
With high costs to unavailable due to single crystalline substrate, so most of thin-film solar cells is the device layer based on polycrystalline.Because described device layer is polycrystalline, so they do not have clear and definite crystalline orientation (crystallographic orientation) (both in outside face and face).Crystalline orientation can have two important effects.First is the orientation effect of the aufwuchsplate when combining dopant, intrinsic defect and other impurity.Above-mentioned shows the research of multiple dopant, based on crystalline orientation, the change of 1 to 2 order of magnitude can occur.An extreme effect of anisotropy doping is the doping of Si in GaAs film.The doping of Si in GaAs film causes the N-shaped on (111) Type B GaAs to conduct electricity, but has p-type electric-conducting on (111) A type GaAs.Second effect of crystalline orientation is the change of the growth rate of the film be deposited.Both experiment and simulation all show, and under certain conditions, growth rate can with 1 to 2 order of magnitude change as the function of crystalline orientation.There is the uncontrolled crystalline orientation in the PV material of megacryst granularity therefore can cause reproducibility problems, and therefore during producing in enormous quantities, reduce productive rate.Certainly, the crystal boundary of the infall of the crystal grain in polycrystal film is as disadvantageous recombination center.
The most of micro-structural features being considered to the thin-film solar cells performance limiting polycrystalline at present can be avoided by growing epitaxial film in the single crystalline substrate of Lattice Matching.But the high cost of single crystalline substrate prevents their uses in real world applications.If grain size enough large (having the granularity of minimum impact to depend on doped level inter alia on character), the effect of crystal boundary can be inhibited in polycrystalline photovoltaic film.But in the film, grain growth is normally constrained to the twice of the thickness being only film.Therefore, the crystal boundary in polycrystalline film has the conclusive impact on efficiency.A lot of research has reported the impact of crystal boundary on Photovoltaic Properties.
Although the major part of above discussion has concentrated in solar cell application, but also have many application, in such applications, when required monocrystalline effective size be diametrically about 100 μm or hundreds of micron time, in fact what need the low cost of the semiconductor film (single crystal-likesemiconductor film) for the manufacture of near single can expand large-scale method.In addition, for some application, semiconductor surface/film/wafer needs to be flexible, thus make the semiconductor wherein bent may be expect application become possibility.Such as, for solar cell application, the profile making PV module meet top when it is placed may be expect.Thin-film transistor is for the manufacture of display.In this application, people also can easily recognize flexibility with the purposes on large area display.
For electronic device, the oldered array of three-dimensional manometer point and nanometer rods provides hope device physics being extended to two dimension or three-dimensional restriction (quantum wire and quantum dot) completely.Multidimensional restriction in these low dimensional structures for a long time by prophesy by the transport that changes significantly compared with block or planar heterojunction structure and optical property.In recent years, charge quantization have stimulated on the impact of the transport of little semiconductor-quantum-point the research that many transmission to wherein Single Electron are enough to the single-electron device of control device.Promotion is the semiconductor band gap process capability of the rapid expansion provided by modern epitaxial growth to the most important factor of the active research of quantum effect.Possible application comprises spin transistor and single-electronic transistor.Other possible application of three-dimensional order nano dot and nanometer rods are included in the potential application on optoelectronics and transducer.Such as, the array of the luminous ordered nano point in residuite may be used for the device using luminescence generated by light effect.Other apply the application be included in high efficiency photovoltaic, solid-state lighting device etc.
Summary of the invention
The present invention relates to the manufacture large-area, flexible, based semiconductor, there is high performance electronic device.The present invention obtains (crystallographically texture) semiconductor device crystallography having texture.Texture that the present invention obtains " single shaft ", " twin shaft " texture and the manufacture of semiconductor device layer of " three axles " texture.Device is " flexibility " still.
As used herein, " three axle texture " refer to that three crystallographic axis of all crystal grains in material all relative to each other arrange.The structure cell of all material can with three reference axis a, b and c for feature.The orientation of the single crystal grain in polycrystalline specimen can be defined by its a, b and c crystallographic axis and reference coupon coordinate system angulation." one-axial texture " refers to any one arrangement in these axles in the crystal grain of all formation polycrystalline specimens." one-axial texture degree (degree ofuniaxial texture) " can be used Electron Back-Scattered Diffraction or be measured by X-ray diffraction.Usually, it is found that, crystal grain has the normal distribution or the Gaussian Profile that there are feature bell curve of orientation.The half width (FWHM) of this Gaussian Profile or peak are " one-axial texture degree ", and define " sharpness (sharpness ofthetexture) of texture ".The sharpness of texture is also called as " inlaying (mosaic) ".Biaxial texture refers to two situations about arranging with certain degree or sharpness in three crystallographic axis of wherein all crystal grains.Three axle texture refer to the situation that whole three crystallographic axis of wherein all crystal grains arrange with certain degree or sharpness.Such as, the three axle texture being feature with the FWHM of 10 ° are meant to three crystallographic axis, i.e. a, b and c of all crystal grains of constituent material, the independent distribution of orientation can be described to the distribution that half width is 10 °.
As used herein, " flexible " refer to device around 12 inches bent spindle and do not cause the ability of the weakening of device electronic character.
In order to realize the above-mentioned goods with other, and according to the such as concrete object of the present invention implemented and describe widely in this article, the invention provides electronic device goods, it comprises: (a) is flexible, large grain size, crystalline metal or alloy substrate, it has macroscopical, [100] or the one-axial texture of [110], the sharpness that the half width (FWHM) be less than with 10 degree is feature, (b) at least one resilient coating over the substrate, at least one resilient coating described is selected from and comprises metal, alloy, nitride, boride, oxide, fluoride, carbide, silicide, with intermetallic alloy or its group combined of germanium, and top buffer layer has the one-axial texture of [100] or [110] of macroscopic view, the sharpness that the half width (FWHM) be less than with 10 degree is feature, and at least one epitaxial loayer of (c) electronic material on described resilient coating, at least one epitaxial loayer of described electronic material is selected from the group included but not limited to based on following: indirect gap semiconductor, such as Si, Ge, GaP, direct gap semiconductor, such as CdTe, CuInGaSe 2(CIGS), GaAs, AlGaAs, GaInP and AlInP, multiband semiconductor, such as, as Zn 1-ymn yo xte 1-xiI-O-VI material, and III-N-V multiband semiconductor, such as GaN xas 1-x-yp y, and its combination.At least one epitaxial loayer of described electronic material comprises trace doped dose of the other materials for the N-shaped that obtains or p-type semiconductor character in semiconductor layer.
In a preferred embodiment of the present invention, described semiconductor layer in goods is the compound semiconductor formed primarily of two or more elements not of the same clan from the periodic table of elements, comprise for compd A lN, AlP, AlAs, GaN, GaP, GaAs, InP, InAs, InSb, AlInGaP, AlGaAs, III-th family (the B of InGaN etc., Al, Ga, and V race (N In), P, As, Sb, Bi) compound, and II race (Zn, Cd, and VI race (O Hg), S, Se, Te) compound, such as ZnS, ZnSe, ZnTe, CdTe, HgTe, CdHgTe etc.Except above binary compound, also comprise ternary compound (three kinds of elements, such as InGaAs) and quaternary compound (four kinds of elements, such as InGaAsP).
In a preferred embodiment of the present invention, described semiconductor layer in goods comprises elemental semiconductor or the alloy of the element in identical race, such as SiC and SiGe, or comprise the compound semiconductor of element of the IB race of the periodic table of elements, group III A and VIA race, the such as alloy of copper, indium, gallium, aluminium, selenium and sulphur.
In a preferred embodiment of the present invention, the substrate of texture (textured substrate) is had to have the grain size being greater than 100 microns.
Semiconductor device according to the invention goods also can comprise at least one resilient coating over the substrate, and this at least one resilient coating is selected from and comprises metal, alloy, nitride, boride, oxide, fluoride, carbide, silicide or its group combined.
In a preferred embodiment of the present invention, described resilient coating has the crystal structure being selected from and comprising following group: the rock salt crystal structure (rock-salt crystal structure) of formula AN or AO, wherein A be metal and N and O corresponding to nitrogen and oxygen; Formula ABO 3perovskite crystal structure, wherein A and B is metal and O is oxygen; Formula A 2b 2o 7pyrochlore crystal structure, wherein A and B is metal and O is oxygen; And formula A 2o 3bixbyite crystal structure, wherein A is metal and O is oxygen.
In a preferred embodiment of the present invention, described resilient coating has the chemical formula being selected from and comprising following group: have formula A xb 1-xo and A xb 1-xthe rock salt crystal structure of the mixing of N, wherein A and B is different metals; The oxynitride of mixing, such as A xb 1-xn yo 1-y, wherein A and B is different metals; The bixbyite structure of mixing, such as (A xb 1-x) 2o 3, wherein A and B is different metals; The perovskite of mixing, such as (A xa ' 1-x) BO 3, (A xa ' 1-x) (B yb ' 1-y) O 3, wherein A, A ', B and B ' are different metals; And the pyrochlore of mixing, such as (A xa ' 1-x) 2b 2o 7, (A xa ' 1-x) 2(B yb ' 1-y) 2o 7, wherein A, A ', B and B ' are different metals.
In another preferred embodiment of the present invention, resilient coating can be selected from the oxide buffer layer comprising following group: γ-Al 2o 3(Al 2o 3cube form); Perovskite, such as but not limited to SrTiO 3, (Sr, Nb) TiO 3, BaTiO 3, (Ba, Ca) TiO 3, LaMnO 3, LaAlO 3, adulterated with Ca and Ti ore, such as (La, Sr) MnO 3, (La, Ca) MnO 3; Layered perovskites, such as Bi 4ti 3o 12; Pyrochlore, such as but not limited to La 2zr 2o 7, Ca 2zr 2o 7, Gd 2zr 2o 7; Fluorite (flourite), such as Y 2o 3, YSZ; Rock salt oxide (rock-salt oxide), such as but not limited to MgO; Spinelle, such as but not limited to MgAl 2o 4.
In another preferred embodiment, the buffer stack of formation electronic device is selected from multilayer, the Y from comprising a cube nitride layer, MgO/ cube nitride 2o 3the multilayer of/YSZ/ cube of nitride, Y 2o 3multilayer, the Y of the multilayer of/YSZ/MgO/ cube of nitride, cubic oxide nitride layer, MgO/ cubic oxide thing 2o 3the multilayer of/YSZ/ cubic oxide thing and Y 2o 3the resilient coating structure of the group selection of the multilayer of/YSZ/MgO/ cubic oxide thing.
In another preferred embodiment, the buffer stack forming electronic device is selected from from comprising TiN layer, the multilayer of MgO/TiN, Y 2o 3the multilayer of/YSZ/TiN, Y 2o 3the multilayer of/YSZ/MgO/TiN, cubic oxide nitride layer, MgO/ γ-Al 2o 3multilayer, Y 2o 3/ YSZ/ γ-Al 2o 3multilayer and Y 2o 3/ YSZ/MgO/ γ-Al 2o 3multilayer group selection resilient coating structure.
Resilient coating can be silicide resilient coating or the intermetallic alloy with germanium, described silicide resilient coating or with the intermetallic alloy of germanium corresponding to there being chemical formula MSi or MSi 2, MSi 3, MGe or MGe 2, MGe 3layer, wherein M is metal, such as but not limited to Ni, Cu, Fe, Ir and Co.
Resilient coating also can be the carbide lamella of cube form corresponding to SiC.
In preferred embodiments, at least top buffer layer is conduction.
In still another preferred embodiment, resilient coating can be " graduate resilient coating ", includes the multi-buffer layer of different lattice parameters, to provide good Lattice Matching to semiconductor layer.
In preferred embodiments, electronic device is also included in the semiconductor module flaggy between resilient coating and semiconductor device layer, to provide good Lattice Matching to semiconductor device layer.
Semiconductor module flaggy can be " graduate semiconductor die " layer of the multilayer with different lattice parameters, to provide good Lattice Matching to semiconductor device layer.
In preferred embodiments, form the substrate of electronic device have make all crystal grains in the face of substrate other two crystallographic axis also there to be the crystallographic texture of texture for feature of the FWHM being less than 10 degree.
In preferred embodiments, form at least one resilient coating of electronic device have make all crystal grains in the face of substrate other two crystallographic axis also there to be the crystallographic texture of texture for feature of the FWHM being less than 10 degree.
In preferred embodiments, form the described electronic device layer of electronic device to have and make other two crystallographic axis of all crystal grains in the face of substrate there to be the crystallographic texture of texture for feature of the FWHM being less than 10 degree.
In preferred embodiments, substrate is selected from the group comprising Cu, Ni, Al, Mo, Nb and Fe and alloy thereof.
In preferred embodiments, substrate is the Ni base alloy of the W content had in the scope of 3-9at%W (atomic percentage W).
In preferred embodiments, substrate is MULTILAYER COMPOSITE substrate, and in MULTILAYER COMPOSITE substrate, only top layer has crystallography arrangement, and the relative to each other arrangement in 10 degree in all directions of the crystallographic axis of all crystal grains in this layer.
In preferred embodiments, substrate is MULTILAYER COMPOSITE substrate, and in MULTILAYER COMPOSITE substrate, only top layer and bottom have crystallography arrangement, and the relative to each other arrangement in 10 degree in all directions of the crystallographic axis of all crystal grains in these layers.
In preferred embodiments, electronic device is the photovoltaic device comprising the pn knot that at least one is parallel to substrate surface.
In still another preferred embodiment, electronic device includes at least two and the photovoltaic device of the preferred multijunction cell of three pn knots being parallel to substrate surface.
In preferred embodiments, the photovoltaic conversion efficiency of described device layer is greater than 13% and is preferably greater than 15%.
In preferred embodiments, described electronic device layer is made up of the nano dot of the arrangement formed in another diametrically different from device layer crystallizations.
In still another preferred embodiment, 80% of nano dot arrange in 60 degree with the normal of device layer.
Electronic device according to the present invention may be used for being selected from the application of the group comprising photovoltaic device, flat-panel monitor, thermo-photovoltaic device, ferro-electric device, LED device, computer hard disc driver device, the device based on magnetic resistance, the device based on luminescence generated by light, nonvolatile memory device, dielectric devices, thermoelectric device and quantum dot laser device.
In preferred embodiments, electronic device has the area being greater than 50 square inches.Again further in preferred embodiment, electronic device has the area being greater than 113 square inches.
In preferred embodiments, at least one can be comprised according to electronic device of the present invention and be selected from the device comprising following group: Double-end device, such as diode; Three termination devices, such as transistor, thyristor or rectifier; And multiterminal head device, such as microprocessor, random access memory, read-only memory or charge coupled device (charge-coupled device).
Accompanying drawing is sketched
By the reading repeatedly to following detailed description and accompanying drawing, will understanding more completely the present invention and its characteristic sum benefit be realized, in the accompanying drawings:
Fig. 1 show according to the various embodiments of sandwich construction of the present invention with the Utopian schematic diagram of cross-sectional form.Figure 1A shows the most basic structure, the metal or alloy substrate of the flexibility of texture outside the face namely having a macroscopic view of [100] or [110] with the half width (FWHM) being less than 10 °; Single or the multi-buffer layer of texture outside the face having [100] or [110] of the FWHM being less than 10 ° of this metal or alloy types of flexure; Selectable epitaxial semiconductor template layer or graduate semiconductor module flaggy, to provide the Lattice Matching of improvement to device layer square on the buffer layer; And conclusively, epitaxial semiconductor device layers, it is simple layer or multilayer, and is selected from the group of the layer included but not limited to based on indirect gap semiconductor, direct gap semiconductor and multi-band-gap semiconductor (multibandgap semiconductor).Figure 1B comprises following device architecture, it comprises: the crystalline metal or alloy substrate of the flexibility of texture outside the face having [100] or [110] with the FWHM being less than 10 °, and wherein other two of all crystal grains vertical crystallographic axis arrange with the FWHM of 10 °; At the single of types of flexure or multi-buffer layer, texture outside its face having [100] or [110] with the FWHM being less than 10 °, and wherein other two of all crystal grains vertical crystallographic axis with arrangement within 10 °; Selectable epitaxial semiconductor template layer square on the buffer layer or graduate semiconductor module flaggy, to provide the Lattice Matching of improvement to device layer; And epitaxial semiconductor device layers, it is simple layer or multilayer, and is selected from the group of the layer included but not limited to based on indirect gap semiconductor, direct gap semiconductor and multi-band-gap semiconductor.
Fig. 2 show according to the electronic device having the pn of texture tie containing extension of the present invention with the Utopian schematic diagram of cross-sectional form, wherein pn ties and is parallel to substrate surface.Fig. 2 shows and comprises following device: metal or alloy substrate that the is flexibility similar to the substrate shown in Fig. 1, crystalline, that crystallography has texture; Also similar to the resilient coating shown in Fig. 1 crystallography there are the single of texture or multi-buffer layer; The semiconductor module flaggy of selectable extension or graduate semiconductor module flaggy, to provide the Lattice Matching of improvement to device layer square on the buffer layer; The p-type and the n-type semiconductor layer that have the extension of texture on top buffer layer or selectable semiconductor module flaggy; Transparent conductor layer and the antireflection coating having metal grid lines.A purposes of such device is as shown in Figure 2 for solar power generation.
Fig. 3 A shows the idealized schematic of simple active-matrix Organic Light Emitting Diode (active-matrix organiclight emitting diode) (AMOLED).Fig. 3 B shows according to the Utopian schematic diagram containing the multijunction cell of three batteries of the present invention.In typical multijunction cell, each battery of different band gap is had to be stacked on top each other.Each battery is stacking in the mode making daylight and be first radiated on the material with maximum band gap.In first battery, absorbed photon is not transferred to second battery, the part that then second battery energy of absorbing remaining solar radiation is higher, simultaneously lower to energy photon keep through.These selective absorbing process lasts, until arrive the final battery with minimum band gap.Substantially, multijunction device be each single junction cell with band gap (Eg) successively decrease order stacking.Top battery catches high-energy photon, and remaining photon transfer is gone down to absorb with the battery lower by band gap.
Fig. 4 shows the cross section of the multijunction cell that some has been reported in the literature.Schematic diagram show the part of being caught by multijunction cell in the spectrum of the sun and these batteries whole close to 40% the conversion efficiency of expection.Fig. 4 A shows three junction batteries of GaInP (1.8eV)/GaAs (1.4eV)/Ge (0.7eV); Fig. 4 B shows three junction batteries of GaInP (1.8eV)/GaInAs (1.25eV)/Ge (0.7eV); And Fig. 4 C shows four junction batteries of GaInP (1.8eV)/GaAs (1.4eV)/GaInAs (1.25eV)/Ge (0.7eV).
Fig. 5 show according to of the present invention contain two many knots electronic devices having the pn of the extension of texture to tie with the Utopian schematic diagram of cross-sectional form, wherein pn knot be parallel to substrate surface.Fig. 5 shows and comprises following device: metal or alloy substrate that the is flexibility similar to the substrate that Fig. 1 and 2 describes, crystalline, that crystallography has texture; Crystallography there are the single of texture or multi-buffer layer; The semiconductor layer of selectable extension or on composition graduate (compositionally graded) template layer; Comprise the bottom battery having the extension of texture of pn knot; Tunnel junction; Comprise the top battery of pn knot; Transparent conductor layer; Antireflection coating and metal grid lines.A purposes of the device shown in Fig. 5 is for solar power generation.
Fig. 6 show according to of the present invention contain three many knots electronic devices having the pn of texture to tie with the Utopian schematic diagram of cross-sectional form, wherein pn knot be parallel to substrate surface.Fig. 6 shows and comprises following device: metal or alloy substrate that the is flexibility similar to the substrate that Fig. 1 and 2 describes, crystalline, that crystallography has texture; Crystallography there are the single of texture or multi-buffer layer; The semiconductor layer of selectable extension or on composition graduate template layer; Comprise the bottom battery having the extension of texture of pn knot; Tunnel junction; Comprise the middle cell of pn knot; Tunnel junction; Comprise the top battery of pn knot; Transparent conductor layer; Antireflection coating and metal grid lines.A purposes of the device shown in Fig. 6 is for solar power generation.
Fig. 7 show as in Fig. 1-6 describe electronic device with the Utopian schematic diagram of cross-sectional form, wherein resilient coating is stacking comprises a lot of thin resilient coating, to provide good Lattice Matching to the semiconductor layer grown in top cushion template.This is called as providing good Lattice Matching to minimize " on composition the graduate buffer approach " of the defect concentration in semiconductor layer to semiconductor.
Fig. 8 show as in Fig. 1-7 describe electronic device with the Utopian schematic diagram of cross-sectional form, wherein semiconductor module flaggy comprises a lot of thin layer, with to semiconductor device layer or comprise pn knot and above semiconductor module flaggy growth the first battery good Lattice Matching is provided.This is called as providing good Lattice Matching to minimize further " the graduate semiconductor approach " of the defect concentration in semiconductor device layer to semiconductor device layer.
Fig. 9 show as in Fig. 1-9 describe electronic device with the Utopian schematic diagram of cross-sectional form, wherein resilient coating is stacking comprises a lot of thin resilient coating, to provide good Lattice Matching to the semiconductor module flaggy grown in top cushion template.In addition, semiconductor module flaggy comprises a lot of thin layer, with to semiconductor device layer or comprise pn knot and above semiconductor module flaggy growth the first battery good Lattice Matching is provided.This is called as providing good Lattice Matching to minimize the combination of " the graduate buffer approach " and " graduate semiconductor approach " of the defect concentration in this layer to semiconductor device layer.
Figure 10 show the flexibility of texture NiW alloy, above alloy have the Si semiconductor layer of texture and the TiN between them have the resilient coating of the extension of texture with the Utopian schematic diagram of cross-sectional form.
Figure 11 shows (111) X ray pole figure of the sample of the TiN at the Ni-3at%W substrate Epitaxial growth having texture.Only see the peak of equivalence in four crystallography, this shows { 100}<100> orientation by force.Use in the face of scanning survey texture half width (FWHM) and use X-ray diffraction also to be represented on figure by the half width (FWHM) of texture outside the face of (200) ω scanning survey.
Figure 12 shows the low multiplication factor TEM cross section of the sample of Ni-3at%W/TiN/Si.Clearly can distinguish whole three layers in the micrograph.
Figure 13 shows and obtains with the spacing of 0.6 micron the orientation image microphoto that electron backscattered Kikuchi diffraction pattern produces with index (indexing) from hexagonal mesh.What the tonal gradation shade (grey scale shading) provided in Figure 13 A indicated the misorientation being less than 2 degree is connected to each other district.What the tonal gradation shadow representation provided in Figure 13 B had a misorientation being less than 3 degree is connected to each other district.It is clear that silicon layer represents the large single crystal having some to inlay.The particle reason there of the crowned seen in image is, film uses pulse laser ablation technology growth, knownly can form so granular feature in this technology.Make deposited by electron beam evaporation or chemical vapour deposition (CVD) carry out growing film and will obtain the very high film of smoothness.
What Figure 14 showed Si/TiN interface shows epitaxially grown high-definition picture.
Figure 15 shows the high-resolution transmission electron microscope photo of the plane of the silicon layer of the extension along <100>.Insert fast Fourier transform (FFT) pattern illustrating photo.
Figure 16 shows the selected area electron diffraction pattern of the <100> crystal zone axis of the plane graph of the transmission electron microscopy sample from Si/TiN/NiW, shows the arrangement of the extension of Si{220}, TiN{200} and Ni{200} diffraction spot.
Figure 17 also shows the selected area electron diffraction pattern of the <100> crystal zone axis of the plane graph of the transmission electron microscopy sample from Si/TiN/NiW, shows the arrangement of the extension of Si{220}, TiN{200} and Ni{200} diffraction spot.In this case, the Qu Geng great of diffraction pattern can be obtained.
Figure 18 show according to the various embodiments of sandwich construction of the present invention with the Utopian schematic diagram of cross-sectional form.Figure 18 A shows the metal or alloy substrate flexible crystalline crystallography having texture; The crystallography of types of flexure has the TiN resilient coating of texture, and the Si of extension or other semiconductor device or template layer.Figure 18 B shows the metal or alloy substrate flexible crystalline crystallography having texture; The crystallography of types of flexure has the MgO resilient coating of texture; Crystallography above MgO layer there is the TiN resilient coating of texture; And the Si of extension or other semiconductor device or template layer.Figure 18 C shows the metal or alloy substrate flexible crystalline crystallography having texture; The crystallography of types of flexure has the Y of texture 2o 3resilient coating; At Y 2o 3the crystallography of layer top there is the YSZ resilient coating of texture; Crystallography above YSZ layer there is the TiN resilient coating of texture; And the Si of extension or other semiconductor device or template layer.Figure 18 D shows the metal or alloy substrate flexible crystalline crystallography having texture; The crystallography of types of flexure has the Y of texture 2o 3resilient coating; At Y 2o 3the crystallography of layer top there is the YSZ resilient coating of texture; Crystallography above YSZ layer there is the MgO resilient coating of texture; Crystallography above MgO layer there is the TiN resilient coating of texture; And the Si of extension or other semiconductor device or template layer.
Figure 19 show according to the various embodiments of sandwich construction of the present invention with the Utopian schematic diagram of cross-sectional form.Figure 19 A shows the metal or alloy substrate flexible crystalline crystallography having texture; At least one crystallography of types of flexure has cube nitride buffer layer of texture, and the Si of extension or other semiconductor device or template layer.Figure 19 B shows the metal or alloy substrate flexible crystalline crystallography having texture; The crystallography of types of flexure has the MgO resilient coating of texture; At least one crystallography above MgO layer there is cube nitride buffer layer of texture; And the Si of extension or other semiconductor device or template layer.Figure 19 C shows the metal or alloy substrate flexible crystalline crystallography having texture; The crystallography of types of flexure has the Y of texture 2o 3resilient coating; At Y 2o 3the crystallography of layer top there is the YSZ resilient coating of texture; At least one crystallography above YSZ layer there is cube nitride buffer layer of texture; And the Si of extension or other semiconductor device or template layer.Figure 19 D shows the metal or alloy substrate flexible crystalline crystallography having texture; The crystallography of types of flexure has the Y of texture 2o 3resilient coating; At Y 2o 3the crystallography of layer top there is the YSZ resilient coating of texture; Crystallography above YSZ layer there is the MgO resilient coating of texture; At least one crystallography above MgO layer there is cube nitride buffer layer of texture; And the Si of extension or other semiconductor device or template layer.
Figure 20 show according to the various embodiments of sandwich construction of the present invention with the Utopian schematic diagram of cross-sectional form.Figure 20 A shows the metal or alloy substrate flexible crystalline crystallography having texture; The crystallography of types of flexure has the γ-Al of texture 2o 3resilient coating, and the Si of extension or other semiconductor device or template layer.Figure 20 B shows the metal or alloy substrate flexible crystalline crystallography having texture; The crystallography of types of flexure has the MgO resilient coating of texture; Crystallography above MgO layer there is the γ-Al of texture 2o 3resilient coating; And the Si of extension or other semiconductor device or template layer.Figure 20 C shows the metal or alloy substrate flexible crystalline crystallography having texture; The crystallography of types of flexure has the Y of texture 2o 3resilient coating; At Y 2o 3the crystallography of layer top there is the YSZ resilient coating of texture; Crystallography above YSZ layer there is the γ-Al of texture 2o 3resilient coating; And the Si of extension or other semiconductor device or template layer.Figure 20 D shows the metal or alloy substrate flexible crystalline crystallography having texture; The crystallography of types of flexure has the Y of texture 2o 3resilient coating; At Y 2o 3the crystallography of layer top there is the YSZ resilient coating of texture; Crystallography above YSZ layer there is the MgO resilient coating of texture; Crystallography above MgO layer there is the γ-Al of texture 2o 3resilient coating; And the Si of extension or other semiconductor device or template layer.
Figure 21 show according to the various embodiments of sandwich construction of the present invention with the Utopian schematic diagram of cross-sectional form.Figure 21 A shows the metal or alloy substrate flexible crystalline crystallography having texture; At least one crystallography of types of flexure has the cubic oxide thing resilient coating of texture, and the Si of extension or other semiconductor device or template layer.Figure 21 B shows the metal or alloy substrate flexible crystalline crystallography having texture; The crystallography of types of flexure has the MgO resilient coating of texture; At least one crystallography above MgO layer there is the cubic oxide thing resilient coating of texture; And the Si of extension or other semiconductor device or template layer.Figure 21 C shows the metal or alloy substrate flexible crystalline crystallography having texture; The crystallography of types of flexure has the Y of texture 2o 3resilient coating; At Y 2o 3the crystallography of layer top there is the YSZ resilient coating of texture; At least one crystallography above YSZ layer there is the cubic oxide thing resilient coating of texture; And the Si of extension or other semiconductor device or template layer.Figure 21 D shows the metal or alloy substrate flexible crystalline crystallography having texture; The crystallography of types of flexure has the Y of texture 2o 3resilient coating; At Y 2o 3the crystallography of layer top there is the YSZ resilient coating of texture; Crystallography above YSZ layer there is the MgO resilient coating of texture; At least one crystallography above MgO layer there is the cubic oxide thing resilient coating of texture; And the Si of extension or other semiconductor device or template layer.
Figure 22 show according to of the present invention containing crystallography has the electronic device of the semiconductor device of texture with the Utopian schematic diagram of cross-sectional form.Device comprises the metal/alloy substrate flexible crystallography having texture; Crystallography there is the resilient coating of texture; Selectable crystallography there is the semiconductor module flaggy of texture; The crystallography of silicon and/or germanium there is the epitaxial loayer of texture; Crystallography there is the GaAs layer of the extension of texture; Crystallography there is the InGaP layer of the extension of texture; Transparent conductor layer, and selectable antireflection coating and metal grid lines.This represents the general basis that form forms device.People it is contemplated that with the other semiconductor layer of this multiple-level stack or knot and/or resilient coating.A purposes of such device is for solar power generation.
Figure 23 A show compound substrate with the Utopian schematic diagram of cross-sectional form, described compound substrate containing with or without crystallographic texture or the bottom that do not arrange, and there is top surface that is that crystallography has texture or that arrange, all crystal grains in this layer is arranged in all directions in 10 degree.Figure 23 B show compound substrate with the Utopian schematic diagram of cross-sectional form, described compound substrate containing with or without crystallographic texture or the center that do not arrange, and there are top surface that is that crystallography has texture or that arrange and basal surface, all crystal grains in this layer is arranged in all directions in 10 degree.
Figure 24 shows the thick YBa of 0.2 μm of the self-assembled nanometer point of the BZO of the substrate Epitaxial growth of the biaxial texture in the buffering having extension 2cu 3o x(YBCO) cross-sectional transmission electron microscope (TEM) image of layer.BaZrO can be seen in YBCO layer 3(BZO) post of self-assembled nanometer point.Post perpendicular to the ab face represented by the parallel lattice fringe in YBCO layer of YBCO, and is parallel to the c-axis of YBCO.Black arrow in figure shows the position of some in the post of the self-assembled nanometer point of BZO.
That Figure 25 shows self assembly in the device layer of substrate Epitaxial growth or orderly nano dot with the Utopian schematic diagram of cross-sectional form.In this case, there is the ordered arrangement of nano dot, make the vertical column forming nano dot.
That Figure 26 shows self assembly in the device layer of substrate Epitaxial growth or orderly nano dot with the Utopian schematic diagram of cross-sectional form.In this case, the ordered arrangement of nano dot can be there is in some way, thus form the post of the inclination of nano dot.
The Utopian schematic diagram of that Figure 27 shows self assembly in the device layer of substrate Epitaxial growth or orderly nano dot.In this case, the ordered arrangement of nano dot is vertical, but nano dot has as directed bending to self.
The detailed description of preferred embodiment
The present invention relates to the manufacture of large-area, flexible, that crystallography has texture, that there is high performance based semiconductor electronic device.The present invention also makes the use reel-to-reel of such device deposit, and (reel-to-reel deposition) carry out creates possibility continuously.
Fig. 1 show according to the various embodiments of sandwich construction of the present invention with the Utopian schematic diagram of cross-sectional form.Figure 1A shows the most basic structure, the metal or alloy substrate of the flexibility of texture outside the macroscopical face namely having [100] or [110] with the half width (FWHM) being less than 10 °; Single or the multi-buffer layer of texture outside the face having [100] or [110] with the FWHM being less than 10 ° of this metal or alloy types of flexure; Selectable, epitaxial semiconductor template layer or graduate semiconductor module flaggy, to provide the Lattice Matching of improvement to the device layer of side on the buffer layer; And conclusively, epitaxial semiconductor device layers, it is simple layer or multilayer, and is selected from the group of the group included but not limited to based on indirect gap semiconductor, direct gap semiconductor and multi-band-gap semiconductor.Figure 1B comprises: device architecture, flexibility, the crystalline metal or alloy substrate of texture outside its face including [100] or [110] with the FWHM being less than 10 °, and wherein other two of all crystal grains vertical crystallographic axis arrange with the half width of 10 °; At the single of types of flexure or multi-buffer layer, texture outside its face having [100] or [110] with the FWHM being less than 10 °, and wherein other two of all crystal grains vertical crystallographic axis with arrangement within 10 °; Selectable epitaxial semiconductor template layer square on the buffer layer or graduate semiconductor module flaggy, to provide the Lattice Matching of improvement to device layer; And epitaxial semiconductor device layers, it is simple layer or multilayer, and is selected from the group of the group included but not limited to based on indirect gap semiconductor, direct gap semiconductor and multi-band-gap semiconductor.
[100] or the semiconductor of [110] texture be useful for realizing high device performance.The metal or alloy template of one-axial texture can pass through thermomechanical process technology, such as rolling and anneal, suppress or punching press and anneal, forge and anneal, draw and anneal and squeeze forging and anneal, manufacture.The combination of these distortion and annealing steps also may be used for use routine experiment and manufactures the metal or alloy substrate with one-axial texture and large mean grain size outside sharpness and clear and definite face.For all thermomechanicals processing approach, the crystallographic texture that we point out in the present invention or present patent application is the recrystallization texture of annealing and is not deformation texture." deformation texture " is the crystallographic texture developed in metal and alloy when mechanical deformation, and the process of distortion obtains the crystal grain of plastic deformation.Deformation texture also can have very large sharpness and can be twin shaft, and has some the specific orientation in cubic material.Details about the typical deformation texture that can be produced by mechanical deformation in metal and alloy can find in following textbook: " Structure of Metals (structure of metal) ", author Charles Barrett and T.B.Massalski, the third edition, Pergamon publishing house, 1980,541-566 page; " Recrystallisation and related annealing phenomena (recrystallization and relevant annealing phenomena) ", author FJ Humphreys, M Hatherly, published by Elsevier, 2004,43-54 page.Recrystallization be a kind of strained crystal grain by one group of new nucleation and growth until the process that replaces of undeformed crystal grain that initial crystal grain has all been consumed.The detailed definition of recrystallization can obtain from the document of this area, or from the network address of online free encyclopaedical Wikipedia http:// en.wikipedia.orq/wiki/Recrystallization (metallurgy)obtain.The crystallographic texture of the process of annealed or recrystallization is called as recrystallization texture.About how can be found in following book by the details of thermomechanical processing generation recrystallization texture: exercise question is " Recrystallisation and related annealing phenomena (recrystallization and relevant annealing phenomena) ", author FJ Humphreys, M Hatherly, published by Elsevier, 2004,327-415 page; " Structure of Metals (structure of metal) ", author Charles Barrett and T.B.Massalski, the third edition, Pergamon publishing house, 1980,568-582 page; The all lists of references pointed out in book are also incorporated to as relevant references.Details about the mode forming one-axial texture, biaxial texture and three axle recrystallization textures can find in above-mentioned book.Especially, about cube, the details that forms the mode of [100] or [110] recrystallization texture in the metal of the center of area and body-centered and alloy discusses in detail in book.In the present invention, crystallography has texture and the metal of recrystallization and alloy are concerned about especially fully.This is because rolled and have the metal of texture and the surface of alloy to be not easy to be used to the epitaxial growth of other materials.In addition, common deformation texture does not have the crystalline orientation for the expectation be combined with semiconductor by suitable resilient coating.The stay in place form that resilient coating grows thereon for providing chemical barrier layer and semiconductor layer.Need chemical barrier layer to prevent element from metal/alloy or ceramic substrate to the diffusion of semiconductor layer.Resilient coating can be selected from and comprise metal, alloy, nitride, boride, oxide, fluoride, carbide, silicide or its group combined.Resilient coating can be the nitride buffer layer of the composition corresponding to MN, and wherein N is nitrogen and M is selected from the group comprising Ti, Ce, Y, Zr, Hf, V, Nb, Nd, La and Al and combination thereof.Resilient coating can be selected from the oxide buffer layer comprising following group: γ-A1 2o 3(Al 2o 3cube form); Perovskite, such as but not limited to SrTiO 3, (Sr, Nb) TiO 3, BaTiO 3, (Ba, Ca) TiO 3, LaMnO 3, LaAlO 3, doping perovskite, such as (La, Sr) MnO 3, (La, Ca) MnO 3; Layered perovskites, such as Bi 4ti 3o 12; Pyrochlore, such as but not limited to La 2zr 2o 7, Ca 2zr 2o 7, Gd 2zr 2o 7; Fluorite, such as Y 2o 3, YSZ; Rock salt oxide, such as but not limited to MgO; Spinelle, such as but not limited to MgAl 2o 4.Resilient coating also can include chemical formula MN xo ythe nitride of (1 < x, y > 0) and hopcalite, wherein N is nitrogen and O is oxygen, and M is selected from the group comprising Ti, Ce, Y, Zr, Hf, V, Nb, Nd, La and Al and combination thereof.Need the stay in place form comprising resilient coating, to obtain the good Lattice Matching with the semiconductor layer grown, thus minimize the defect concentration in semiconductor layer.
In some cases, before semiconductor device layer, other semiconductor module flaggy is used.This semiconductor module flaggy is also for providing better Lattice Matching to semiconductor device layer.Another function of top buffer layer is to provide stable, the level and smooth and surface of densification, grows on a surface to make semiconductor layer.Buffer-layer surface can regulate with chemical means or hot means.In Chemical Regulation, use with the surface of one or more chemical substance modification resilient coatings of gaseous state or solution form.In thermal conditioning, resilient coating is heated to the high temperature that surface reconstruction occurs.That surface modulation also can use standard and full-fledged technology, namely plasma etching and reactive ion etching come (see, such as, Siliconprocessing for the VSLI Era (the silicon process in very lagre scale integrated circuit (VLSIC) epoch), the 1st volume, S.Wolf and R.N.Tanber edits, 539-574 page, Lattice publishing house, Sunset Park, CA, 1986).
The semiconductor device layer of [100] or [110] texture described in Fig. 1 can be selected from the group included but not limited to based on those following semiconductor device layer: indirect gap semiconductor, such as Si, Ge, GaP; Direct gap semiconductor, such as CdTe, CuInGaSe 2(CIGS), GaAs, AlGaAs, GaInP and AlInP; Multiband semiconductor, such as, as Zn 1-ymn yo xte 1-xiI-O-VI material, and III-N-V multiband semiconductor, such as GaN xas 1-x-yp y, and its combination.This comprises trace doped dose for the other materials of the N-shaped that obtains or p-type semiconductive character in semiconductor layer.The definition of " directly ", " indirectly " and " multiband " semiconductor can obtain from the document of this area, or from online free encyclopaedical Wikipedia ( http:// en.wikipedia.org/wiki/Main Page) obtain.Such as, as stated in Wikipedia, the definition of direct gap semiconductor and indirect gap semiconductor is, " in semiconductor physics, direct band gap means the minimum value of conduction band in momentum space and is located immediately at above the maximum of valence band.In direct gap semiconductor, the electronics at conduction band minimum place can directly be combined with the hole at valence band maximum place, keeps momentum simultaneously.The energy crossing over the compound of band gap is launched with the form of the photon of light.Radiation recombination that Here it is, also referred to as spontaneous emission.In the indirect gap semiconductor of such as crystalline silicon, conduction band minimum is not identical with the momentum of valence band maximum, so the direct transition of crossing over band gap does not keep momentum and is forbidden.Compound occurs in the third party allowing the conservation of momentum, and such as phonon or crystal defect, during as medium.These compounds will often discharge the band-gap energy of the non-phonon as phonon, and thus not utilizing emitted light.Therefore, very poor efficiency and faint is launched from the light of indirect semiconductor.There is the photoemissive new technology improved from indirect semiconductor.See indirect band gap, to obtain explanation.The main example of direct gap semiconductor is GaAs, a kind of material usually used in laser diode.”
In a preferred embodiment of the present invention, described semiconductor layer in goods is the compound semiconductor formed primarily of two or more elements not of the same clan from the periodic table of elements, comprise: III-th family (B, Al, Ga, and V race (N In), P, As, Sb, Bi) compound, such as compd A lN, AlP, AlAs, GaN, GaP, GaAs, InP, InAs, InSb, AlInGaP, AlGaAs, InGaN etc., and II race (Zn, Cd, and VI race (O Hg), S, Se, Te) compound, such as ZnS, ZnSe, ZnTe, CdTe, HgTe, CdHgTe etc.Except above binary compound, also comprise ternary compound (three kinds of elements, such as InGaAs) and quaternary compound (four kinds of elements, such as InGaAsP).
Semiconductor layer in goods also can comprise elemental semiconductor or the alloy of the element in identical race, such as SiC and SiGe, or comprise the compound semiconductor of element of the IB race of the periodic table of elements, group III A and VIA race, the such as alloy of copper, indium, gallium, aluminium, selenium and sulphur.
Fig. 2 show according to according to the present invention containing extension, electronic device that the pn that has texture tie with the Utopian schematic diagram of cross-sectional form, wherein pn ties and is parallel to substrate surface.Fig. 2 shows and comprises following device: metal or alloy substrate that the is flexibility similar to the substrate shown in Fig. 1, crystalline, that crystallography has texture; Also similar to the resilient coating shown in Fig. 1 crystallography there are the single of texture or multi-buffer layer; The semiconductor module flaggy of selectable extension or graduate semiconductor module flaggy, to provide the Lattice Matching of improvement to device layer square on the buffer layer; On top buffer layer or selectable semiconductor module flaggy have texture, the p-type of extension and n-type semiconductor layer; Transparent conductor layer; With the antireflection coating having metal grid lines.P-type semiconductor obtains by implementing doping process, and in doping process, the atom of some type is incorporated in semiconductor, to improve freely the quantity of (in this case, positive) charge carrier.When dopant material is added into, dopant material takes away from semiconductor atom (weakly-bound) outer-shell electron that (acceptance) weak beam ties up.Such dopant is also referred to as acceptor material (acceptor material), and the semiconductor atom having lost electronics is called as hole.The object of p-type doping produces abundant hole.For the situation of silicon, replace entering in lattice with triad (such as, usually from the group III A of the periodic table of elements, boron or aluminium).Result loses an electronics from four covalent bonds normal for silicon crystal lattice.Thus dopant atom can accept electronics to make the 4th key complete from the covalent bond of the atom adjoined.Such dopant is called as acceptor.Dopant atom accepts electronics, causes the loss of the half of a key from the atom adjoined, and causes the formation in " hole ".Each hole is associated with the dopant ion of neighbouring negative electrical charge, and semiconductor keeps electric neutrality as a whole.But once each hole is formed in dot matrix, a proton so in the atom of the position in described hole will be " exposure ", and or else can be neutralized by electronics.Therefore, a certain amount of positive charge is played in hole.When adding the acceptor atom of enough large quantity, the quantity in hole exceedes greatly by the quantity of the electronics of thermal excitation.Therefore, hole is the carrier occupied the majority, and electronics is the carrier occupied the minority in p-type material.N-type semiconductor obtains by implementing doping process, namely by adding the impurity of pentad (valence-five element) to tetravalence semiconductor (valence-four semiconductor), to increase freely the quantity of (in this case, bearing) charge carrier.When dopant material is added into, dopant material abandons to semiconductor atom the outer-shell electron that (providing) weak beam ties up.Such dopant is also referred to as donor material (donor material), because it abandons some in its electronics.The object of N-shaped doping produces abundant moveable or " carrier " electronics in the material.In order to help to understand the mode realizing N-shaped doping, consider the situation of silicon (Si).Si atom has four valence electrons, wherein eachly forms covalent bond with in four Si atoms adjoined.If there is the atom of five valence electrons, such as phosphorus (P), arsenic (As) or antimony (Sb), be incorporated into lattice and replace Si atom, then this atom will have four covalent bonds and a free electronics.This extra electronics is only faintly combined with atom, and can easily be excited in conduction band.At normal temperature, all such electronics are all excited in conduction band substantially.The formation not causing hole is excited, so the quantity of electronics far exceeds the quantity in hole in such material due to these electronics.In this case, electronics is the carrier occupied the majority, and hole is the carrier occupied the minority.Can " provide " because five electronic atoms have extra electronics, so they are referred to as donor atom.Therefore, p-type semiconductor and n-type semiconductor can be manufactured by the suitable doping of element.Device in Fig. 2 relates to p-n junction, and wherein knot is parallel to substrate surface.The combination of p-type layer and n-layer is called as monocell.This device shown in Fig. 2 is only the simple example of the possible device architecture that can manufacture based on the present invention.The possible purposes of such device is solar cell or photovoltaic cell as daylight being converted into electric energy.Can modification layer, i.e. p-type or N-shaped, order.In addition, in some cases, comprising the very large p+ layer of wherein excessive removable hole concentration may be expect.Similarly, n+ layer can be deposited.Such layer also may be used for manufacturing the electric contact in device.
Basic structure shown in Fig. 1 and Fig. 2 may be used for manufacturing large-scale electronic device, such as photovoltaic device, flat-panel monitor, thermo-photovoltaic device, ferro-electric device, LED device, computer hard disc driver device, the device based on magnetic resistance, the device based on luminescence generated by light, nonvolatile memory device, dielectric devices, thermoelectric device and quantum dot laser device.The electronic device that can easily imagine is Double-end device, such as diode; Three termination devices, such as transistor, thyristor or rectifier; And multiterminal head device, such as microprocessor, random access memory, read-only memory or charge coupled device.
Some in the most exciting application is in photovoltaic cell or solar cell and for display, such as thin-film transistor.In these two fields, there is the trend using film on the metallic substrate.But for these situations, semiconductor is unbodied or polycrystalline, and the performance therefore having the performance that obtains than the single crystal device from identical semiconductor low.Electronic instrument flexible on mechanics has and does not allow to use rigid substrate part to realize the potentiality of novel application with the restriction of mechanics at physics.In addition, using flexible substrate, it is contemplated that the rolling type manufacture (roll-to-rollmanufacturing) similar to there being the printing machine of the treating capacity manufactured higher than normal discrete semiconductor device significantly.In some in application mentioned above, there is the requirement on devices comparing the relative loose of other semiconductor device.The combination in the metal of large-area flexibility, alloy and ceramic substrate of the semiconductor layer of the near single of three axle texture and device greatly can change these application in these fields.Single crystal device on the substrate of flexibility will obtain high efficiency photovoltaic cell and the thin-film transistor (TFT) having higher electron mobility.
The metal or alloy paper tinsel of flexibility manufactures TFT circuit and causes very big concern.See, such as, Thesis S.D. and Wagner S., " Amorphous silicon thin-film transistors on steel foilsubstrates (amorphous silicon film transistor on steel foil substrate); " IEEE Electron Device Lett., vol.17, no.12, pp.578-580, Dec.1996; Serikawa T. and Omata F., " High-mobility poly-Si TFT ' s fabricated on flexible stainless steel substrates (the high mobility multi-crystal TFT manufactured on flexible stainless steel substrate); " IEEE ElectronDevice Lett., vol.20, no.11, pp.574-576, Nov.1999; Afentakis T. and Hatalis M., " High performance polysilicon circuits on thin metal foils (the high-performance polycrystal silicon circuit on thin metal foil), " Proc.SPIE, vol.5004, pp.122-126,2003; Howell R.S., Stewart M., Karnik S.V., Saha S.K. and Hatalis M.K., IEEE Electron DeviceLett., vol.21, no.2, pp.70-72, Feb.2000.In these four sections of papers all, result be the polycrystalline having orientation or the Si layer of amorphous.In use polycrystalline Si in most cases, polycrystalline Si is the laser crystallization layer of Si.First the amorphous layer of Si is deposited on substrate, is then crystallisation step.Also can use and provide the infrared lamp of the high rate of heat addition to complete this crystallization.Similar process can be used to manufacture the epitaxial silicon on substrate disclosed by the invention.The process that then precursor film of this first deposited amorphous Si carries out follow-up crystallisation step is called as " ex situ (ex-situ) " process.Crystalline silicon also can at high temperature directly epitaxial deposition on the substrate of near single.The single crystal device of three axle texture in the metal of flexibility, alloy and ceramic substrate will obtain the thin-film transistor (TFT) of the electron mobility higher than the electron mobility of the thin-film transistor that the silicon of non-oriented can be used to manufacture, and therefore have the potentiality greatly changing this application veritably.Advanced flat-panel monitor, comprise active matrix liquid crystal display (LCD) (active matrix liquid crystal display), mainly use heavy sheet glass as substrate, heavy sheet glass provides the advantage of transparency and stability aspect, but very fragile and heavy.Substrate in this paper will be firm and lightweight, and due to device layer be three axle texture or near single, this substrate by have those excellent performances presumable in specific rigidity glass substrate many performance.The wide range of flat panel display applications, and comprise computer monitor, TV, electronic billboard, mobile phone, calculator and the display screen on the consumer electronics of the whole series.For portable display, active matrix liquid crystal display (AMLCD) and active-matrix Organic Light Emitting Diode (AMOLED), the polycrystalline Si being used in the K cryogenic treatment on glass is being considered broadly for large-scale application.Active Matrix OLED (AMOLED) display is made up of Organic Light Emitting Diode (OLED) pixel, wherein organic light-emitting diode pixel has been deposited or has been attached on thin-film transistor (TFT) array, the picture element matrix of luminescence when being electrically excited to be formed in.Contrary with passive-matrix OLED screens, if electricity distributes line by line, so active-matrix TFT rear board is as controlling the array flowing through the switch of the amount of the electric current of each OLED pixel.Tft array continuously control flow check to the electric current of pixel, with the brightness of each pixel light emission of signal controlling.Usually, this continuous print electric current is controlled by least two TFT in each pixel, the charging of a start and stop holding capacitor, and second provides the voltage source of the level required for generation constant current to pixel.Therefore, AMOLED runs all the time (that is, for whole frame scan), avoids the needs to the very high electric current required for passive-matrix operation.Polysilicon rear board technology for the manufacture of tft array is the current one preferred technique for OLED (technology-of-choice), because its provide meet OLED current drive requirement rational mobility (see, such as, Afentakis T., Hatalis M., Voutsas T. and Hartzell J., " Poly-silicon TFT AM-OLED on thin flexible metalsubstrates (the multi-crystal TFT AM-OLED in thin flexible metal substrate); " Proc.SPIE, vol.5004, pp.187-191,2003).Polycrystalline silicon technology also allows the combination of drive circuit directly on substrate.But, the challenge of the key having many needs to overcome: the threshold voltage inhomogeneities reducing polysilicon, and the productivity ratio proving viable commercial.This problem can be expected to use device of the present invention to solve, in device of the present invention, three axle texture of semiconductor device layer or the character of near single reduction inhomogeneities is boosted productivity, improve mobility significantly and remain lightweight, because do not use glass.Fig. 3 A illustrates the schematic diagram of simple AMOLED device.Fig. 3 A, when combining with Fig. 1 and 2, shows the mode that can manufacture based on AMOLED of the present invention, wherein uses the present invention to manufacture TFT/ substrate array.
An important application of device disclosed by the invention is at photovoltaic art.The device schematically shown in Fig. 2 can be used as photovoltaic cell or solar cell.These devices will be large-area and flexibility, and can be placed on roof.Flexible solar cell is also useful to space application, because the large array of photovoltaic module or spool can be wrapped and then at too In-Flight Deployment.
A kind of mode manufacturing the higher solar cell of efficiency finds the larger part of the spectrum from daylight-from infrared ray to visible ray to the material of ultraviolet-catch energy.When photovoltaic material absorbs the light wave of the energy containing the amount identical with its band gap, energy is from photon transfer to photovoltaic material.Band gap is that electronics is pushed to energy (Eg) required for conduction band that electronics freely flows wherein from the valence band of material.Fig. 3 B shows the schematic diagram of the device having the photovoltaic cell of different band gap containing three.This structure is also referred to as tandem cell (cascade cell) or laminated cell (tandem cell), and this structure can realize higher total conversion efficiency by catching the larger part of solar spectrum.In this typical multijunction cell, each battery with different band gap is stacked on top each other.Each battery is stacked in the mode making daylight and be first radiated on the material with maximum band gap.In first battery, absorbed photon is not transferred to second battery, the part that then second battery energy of absorbing remaining solar radiation is higher the photon lower to energy keep through.These selective absorbing process lasts, until arrive the final battery with minimum band gap.Such multijunction cell can obtain very high efficiency.The principle of multijunction cell can obtain (MartinA.Green from prior art, Keith Emery, Klaus B ü cher, David L.King, Sanekazu Igari, " Solarcell efficiency tables (version 11) (solar battery efficiency table (the 11st edition); " Progressin Photovoltaics:Research and Applications, the 6th volume, the 1st phase, 35-42 page, on May 4th, 1999; Karam, N.H.; King, R.R.; Cavicchi, B.T.; Krut, D.D.; Ermer, J.H.; Haddad, M.; Li Cai; Joslin, D.E.; Takahashi, M.; Eldredge, J.W.; Nishikawa, W.T.; Lillington, D.R.; Keyes, B.M.; Ahrenkiel, R.K., " Development and characterization of high-efficiency Ga0.5ln0.5P/GaAs/Gedual-and triple-junction solar cells (exploitation of high efficiency Ga0.5ln0.5P/GaAs/Ge binode and three-joint solar cell and sign); " Electron Devices, IEEE Transactions on, Vol.46, No.10, pp.2116-2125, Oct.1999; H.Hou, K.Reinhardt, S.Kurtz, J.Gee, A.Allerman, B.Hammons, P.Chang, E.Jones, Novel InGaAsN pn junction forhigh-efficiency multiple-junction solar cells (the novel I nGaAsN pn for the multiple joint solar cell of high efficiency ties), The Second World Conference on PV EnergyConversion (meeting of Second Committee world PV power conversion), 1998, pp.3600-3603; D.Friedman, J.Geisz, S.Kurtz, J.Olson, 1-eV GaInNAs solar cells for ultra highefficiency multijunction devices (the 1-eV GaInNAs solar cell for Ultra-High Efficiency multijunction device), the meeting of Second Committee international PV power conversion, 1998, pp.3-7; T.V.Torchynska and G.Polupan, " High efficiency solar cells for space applications (high efficiency solar cell for space application); " Superficies y Vacio 17 (3), 21-25, in September, 2004; R.McConnell and M.Symko-Davies, " DOE High Performance Concentrator PV Project (DOE high-performance concentrator PV engineering); " Intemational Conference on Solar Concentrators for the Generation of Electricity or Hydrogen (about for generating electricity or the international conference of solar condenser of hydrogen manufacturing), 1-5 May 2005, Scottsdale, Arizona, NREL/CD-520-38172).
Fig. 4 shows the cross section of the multijunction cell that some has been reported in the literature.Schematic diagram show the part of being caught by multijunction cell in the spectrum of the sun and these batteries whole close to 40% the conversion efficiency of expection.Fig. 4 A shows three junction batteries of GaInP (1.8eV)/GaAs (1.4eV)/Ge (0.7eV); Fig. 4 B shows three junction batteries of GaInP (1.8eV)/GaInAs (1.25eV)/Ge (0.7eV); And Fig. 4 C shows four junction batteries of GaInP (1.8eV)/GaAs (1.4eV)/GaInAs (1.25eV)/Ge (0.7eV).Be apparent that, the advantage of catching the more part of the spectrum of the sun is higher conversion efficiency.Fig. 5 show according to of the present invention contain two many knots electronic devices having the pn of the extension of texture to tie with the Utopian schematic diagram of cross-sectional form, wherein pn knot be parallel to substrate surface.Fig. 5 shows and comprises following device: metal or alloy substrate that the is flexibility similar to the substrate that Fig. 1 and 2 describes, crystalline, that crystallography has texture; Crystallography there are the single of texture or multi-buffer layer; The semiconductor layer of selectable extension or on composition graduate template layer; Comprise pn knot have texture, the bottom battery of extension; Tunnel junction; Comprise the top battery of pn knot; Transparent conductor layer; Antireflection coating and metal grid lines.A purposes of the device shown in Fig. 5 is for solar power generation.Fig. 6 show according to of the present invention contain three many knots electronic devices having the pn of texture to tie with the Utopian schematic diagram of cross-sectional form, wherein pn knot be parallel to substrate surface.Fig. 6 shows and comprises following device: metal or alloy substrate that the is flexibility similar to the substrate that Fig. 1 and 2 describes, crystalline, that crystallography has texture; Crystallography there are the single of texture or multi-buffer layer; The semiconductor layer of selectable extension or on composition graduate template layer; Comprise pn knot, have texture, the bottom battery of extension; Tunnel junction; Comprise the middle cell of pn knot; Tunnel junction; Comprise the top battery of pn knot; Transparent conductor layer; Antireflection coating and metal grid lines.Similarly, a purposes of the device shown in Fig. 6 is for solar power generation.
The performance of electronic device depends on defect concentration.The mode reducing the defect concentration in active semiconductor layer reduces the lattice mismatch of itself and top buffer layer.This can use " graduate resilient coating " approach to complete.Fig. 7 show as in Fig. 1-6 describe electronic device with the Utopian schematic diagram of cross-sectional form, wherein resilient coating is stacking comprises the thin resilient coating much having little by little different (graduallydiffering) lattice parameters, to provide good Lattice Matching to the semiconductor layer grown in top cushion template.This is called as providing good Lattice Matching to minimize " the graduate buffer approach " of the defect concentration in semiconductor layer to semiconductor.The quantity of the layer needing the graduate lattice parameter be deposited to cushion depends on the lattice mismatch between semiconductor and substrate.
In order to make higher-quality extension become may and reduce the defect concentration in semiconductor layer with the better Lattice Matching of semiconductor layer also can by use rock salt structure resilient coating that is that mix or that adulterate, mixing or adulterate perovskite resilient coating, mixing or the pyrochlore resilient coating that adulterates obtain.Such as, the rock salt structure oxide (AO, wherein A is metal) of mixing, nitride (AN, wherein A is metal) and oxynitride (AN can be used xo 1-x, wherein A is metal), mixing perovskite (ABO 3, wherein A and B is metal), mixing pyrochlore (A 2b 2o 7, wherein A and B is metal) or mixing bixbyite (A 2o 3, wherein A is metal) and structure oxide resilient coating carrys out control lattice constant, to obtain the better Lattice Matching with semiconductor layer.The oxide of following mixing and nitride buffer layer receive special concern:
1) the rock salt structure oxide mixed and nitride, such as A xb 1-xo and A xb 1-xn, wherein A and B is different metals.Such as, Ba 0.64sr 0.36the solid solution of O, BaO and SrO, provides the excellent Lattice Matching with Si.
2) oxynitride mixed, such as A xb 1-xn yo 1-y, wherein A and B is different metals.
3) the bixbyite structure mixed, such as (A xb 1-x) 2o 3, wherein A and B is different metals.
4) perovskite (A mixed xa ' 1-x) BO 3, (A xa ' 1-x) (B yb ' 1-y) O 3, wherein A, A ', B and B ' are different metals.Such as, Ca 0.95sr 0.05tiO 3, CaTiO 3and SrTiO 3solid solution, the excellent Lattice Matching with Si is provided.
5) pyrochlore (A mixed xa ' 1-x) 2b 2o 7, (A xa ' 1-x) 2(B yb ' 1-y) 2o 7, wherein A, A ', B and B ' are different metals.
In some cases, the defect concentration using " graduate semiconductor die " approach to reduce in the active semiconductor layer forming electronic device is more expected.Fig. 8 show as in Fig. 1-7 describe electronic device with the Utopian schematic diagram of cross-sectional form, wherein semiconductor module flaggy comprises the thin layer much having little by little different lattice parameters, with to semiconductor device layer or comprise pn knot and above semiconductor module flaggy growth the first battery good Lattice Matching is provided.This is called as providing good Lattice Matching to minimize further " the graduate semiconductor approach " of the defect concentration in semiconductor device layer to semiconductor device layer.When last, people it is contemplated that " graduate resilient coating " and the combination of " graduate semiconductor die " approach.Fig. 9 show as in Fig. 1-8 describe electronic device with the Utopian schematic diagram of cross-sectional form, wherein resilient coating is stacking comprises a lot of thin resilient coating, to provide good Lattice Matching to the semiconductor module flaggy grown in top cushion template.In addition, semiconductor module flaggy comprises a lot of thin layer, with to semiconductor device layer or comprise pn knot and above semiconductor module flaggy growth the first battery good Lattice Matching is provided.This is called as providing good Lattice Matching to minimize the combination of " the graduate buffer approach " and " graduate semiconductor approach " of the defect concentration in this layer to semiconductor device layer.
Embodiment 1: by one after the other cubic metal or alloy by compression compacting or forging to large total deformation and and then recrystallization annealing temperature prepared the metal substrate of [100] one-axial texture.Such as, use and have the NiW alloy of 3-9at%W, by it with the distortion of single shaft extruding boil down to 90%, then in stove at the annealing temperature of the primary recrystallization temperature higher than alloy.The primary recrystallization texture formed is [100] texture.By annealing temperature being increased to the high temperature close to 1000 DEG C, define the mean grain size being greater than 100 μm.Then at the resilient coating of deposited on substrates extension.Such as, be under the depositing temperature of 300 DEG C-600 DEG C in temperature range, use the TiN layer of chemical vapour deposition (CVD) (CVD) deposit epitaxial.Then be under the depositing temperature of 300 DEG C-900 DEG C in scope, use the Si layer of CVD type process deposits extension.The formation of the Si device layer of this causes [100] one-axial texture.Selectively, by changing the sedimentary condition of Si layer, [110] crystallographic texture relative with [100] texture is obtained.
Embodiment 2: by one after the other cubic metal or alloy by compression compacting to large total deformation and and then recrystallization annealing temperature prepared the metal substrate of [110] one-axial texture.Such as, use and have the NiW alloy of 3-9at%W, by it with the distortion of single shaft extruding boil down to 90%, then in stove at the annealing temperature of the primary recrystallization temperature higher than alloy.The primary recrystallization texture formed is [110] texture.By annealing temperature being increased to the high temperature close to 1000 DEG C, define the mean grain size being greater than 100 μm.Then at the resilient coating of deposited on substrates extension.Such as, be under the depositing temperature of 300 DEG C-600 DEG C in temperature range, use the TiN layer of chemical vapour deposition (CVD) (CVD) deposit epitaxial.Then be under the depositing temperature of 300 DEG C-900 DEG C in scope, use the Si layer of CVD type process deposits extension.The formation of the Si device layer of this causes [110] one-axial texture.Selectively, by changing the sedimentary condition of Si layer, [100] crystallographic texture relative with [100] texture is obtained.
Embodiment 3: Figure 10 show crystallography has texture, flexible NiW alloy and above alloy have the Si semiconductor layer of texture and between them have the resilient coating of the extension of the TiN of texture with the Utopian schematic diagram of cross-sectional form.This device is consistent with the device that Figure 1A and B describes.By the alloy coil obtained by powder metallurgy having been prepared the Ni-3at%W of the biaxial texture of [100] texture from the paper tinsel of the thickness continuous rolling of about 120 mils to be thickness be about 2 mils or 50 microns.The crystallographic texture of the rolling of paper tinsel or band is the standard C u-shaped rolling texture of the FCC metal of greatly distortion.After band degreasing and drying, band is loaded into the reel-to-reel high vacuum (10 holding radio frequency induction heating furnace -8holder) in room.Band is ~ 3 × 10 -7the hot-zone by stove is pulled, to form sulphur c (2 × 2) superstructure on the surface of the strip with the speed making each part be heated to 1250 DEG C in 20 minutes under the local pressure of the hydrogen sulfide gas of holder.After the high temperature anneal, NiW band is cubic texture completely, and have corresponding to orientation { the sharp keen texture of 100}<100>, and there is the surface reconstruction corresponding to c (2 × 2) sulphur superstructure.Then the epitaxial deposition of both TiN and Si layers on NiW band.Stoichiometric hot pressing TiN target is used to grow TiN.By 3 × 10 -8holder reference pressure under at 700 DEG C with about 2-3J/cm 2laser energy carry out the pulse laser ablation of 15 minutes and deposit these films with the repetition rate of 10Hz.Figure 11 shows typical (111) X ray pole figure of the sample of the TiN of the Ni-3at%W substrate Epitaxial growth in three axle texture.Only see the peak of equivalence in four crystallography, this shows { 100}<100> orientation by force.Use in the face of scanning survey texture half width (FWHM) and use X-ray diffraction also to be represented on figure by the half width (FWHM) of texture outside the face of (200) ω scanning survey.Texture FWHM normally about 6.6 in face, and outside face, FWHM is 3.2 for the deviation (rocking) of the rolling direction along substrate and is 6.6 for the deviation around rolling direction.After the width counting ω scanning " real " FWHM of scanning is about ~ 5 °.Then energy density is used to be 5-7J-cm -2krF (λ=248nm, τ=25ns) pulsed excimer laser with ~ 10 -7holder base vacuum film deposition in TiN layer.Initially, in initial 2 minutes between Si depositional stage, ablation velocity is 2Hz, and underlayer temperature is in the scope of 650 DEG C-700 DEG C.After this, the temperature for growing is reduced to the temperature range of 520 DEG C-550 DEG C, and carries out Si with the repetition rate of 10Hz and grow 15 minutes.Figure 12 shows the low multiplication factor TEM cross section of the sample of Ni-3at%W/TiN/Si.Clearly can distinguish whole three layers in the micrograph.TiN layer to be the thick and Si film of about 110nm be about 1 μm thick.Figure 13 shows from obtaining the orientation image microphoto produced with the electron backscattered Kikuchi diffraction pattern of index on hexagonal mesh with the spacing of 0.6 micron.What the tonal gradation shadow representation provided in Figure 13 A had a misorientation being less than 2 degree is connected to each other district.What the tonal gradation shadow representation provided in Figure 13 B had a misorientation being less than 3 degree is connected to each other district.It is clear that silicon layer represents the large single crystal having some to inlay.The particle reason there of the crowned seen in image is, film uses pulse laser ablation technology growth, knownly can form so granular feature in this technology.Make deposited by electron beam evaporation or chemical vapour deposition (CVD) carry out growing film and will obtain the very high film of smoothness.Figure 13 shows, and Si film that is extension, height-oriented, three axle texture can be deposited on the NiW/TiN substrate of three axle texture.Figure 14 shows the high-resolution cross sectional image at epitaxially grown Si/TiN interface.Microphoto clearly shows the sharpness at the extension essence of growth and the interface between TiN layer and Si layer.Figure 15 shows the high-resolution transmission electron microscope photo of the plane of the silicon layer of the extension of getting along <100> direction.Insert fast Fourier transform (FFT) pattern illustrating photo.Be apparent that, growth on the NiW that the Si film of extension is being cushioned by TiN.Figure 16 shows the selected area diffraction patterns of the <100> crystal zone axis of the plane graph of the transmission electron microscopy sample of Si/TiN/NiW, shows the arrangement of the extension of Si{220}, TiN{200} and Ni{200} diffraction spot.Clearly visible and mark in diffraction pattern from the spot of whole three layers.Between Si and TiN, have the rotation of 45 °, and the TiN on Ni also to have cube on cube the relation of (cubeon cube) extension.Figure 17 also shows the selected area diffraction patterns of the <100> crystal zone axis of the plane graph of the transmission electron microscopy sample from Si/TiN/NiW, shows the arrangement of the extension of Si{220}, TiN{200} and Ni{200} diffraction spot.In this case, the Qu Geng great of diffraction pattern is obtained.Although silicon uses pulsed laser ablation deposition in this case, there is the technology that much can be used for Si deposition.Many in these technology obtained recently summary (see, such as, MichelleJ.McCann, Kylie R.Catchpole, Klaus J.Weber, Andrew W.Blakers, " A reviewof thin-film crystalline silicon for solar cell applications.Part 1:Nativesubstrates is (about the summary of the thin film silicon/crystalline silicon for solar cell application.Part 1: native substrate), " Solar Energy Materials and Solar Cells, the 68th volume, the 2nd phase, May calendar year 2001,135-171 page; Kylie R.Catchpole, Michelle J.McCann, Klaus J.Weber and Andrew W.Blakers, " A review of thin-film crystalline silicon for solar cell applications.Part 2:Foreign substrates is (about the summary of the thin film silicon/crystalline silicon for solar cell application.Part 1: foreign substrates), " Solar Energy Materials and SolarCells, the 68th volume, the 2nd phase, May calendar year 2001,173-215 page).The technology of electron beam evaporation sputtering (electron-beam evaporation sputtering), ion beam sputtering, chemical vapour deposition (CVD), metal organic chemical vapor deposition (metallorganic chemical vapor deposition) and combustion chemical vapor deposition (combustion chemical vapor deposition) is for the technology in the deposition of resilient coating and semiconductor layer.
It is also important that and it should be noted that when having single resilient coating or multi-buffer layer, between the depositional stage of layer afterwards, the conversion zone of the crystallographic texture without the orientation expected can be formed in the below of top buffer layer.These conversion zones do not affect the orientation of device layer, because there is the layer of the buffering of orientation suitably above device layer.Usually, can occur in multilayer system polycrystalline, without the formation of the conversion zone of crystallographic texture, as long as the deposition of the layer of its orientation suitably above the layer come into question is formed after completing.
There is the coherent twin boundary of some first order in a layer of silicon.Therefore, Si layer is not completely not containing defectiveness.But so coherent twin boundary is not quite disadvantageous and is not active (Hjemas, P.C on electronics, Lohne, O., Wandera, A., Tathgar, H.S., " The effect of grainorientations on the efficiency of multicrystalline solar cells (grain orientation is on the impact of the efficiency of polycrystalline solar cell); " Solid State Phenonema, vol.95-96, pp.217-222,2004; B.Cunningham, H.Strunk and D.G.Ast, " First and second order twinboundaries in edge defined film growth silicon ribbon (first order in the film growth silicon ribbon of fringe enclosing and second level twin boundary); Appl.Phys.Lett.; 40; pp.237-239,982).Although clearly do not observe other defect in manufactured film, if there is the other defect of nucleation, they can be passivated to become almost harmless on inactive in electricity or electronics.The defect of passivation that needs like this usually occurs in for the single-crystal wafer of solar cell manufacture with in being with.Such defect can be passivated (M.Rinio to have many prior aries to confirm, M.Kaes, G.Hahn and D.Borchert, " Hydrogen passivation of extended defects in multicrystallinesilicon solar cells (hydrogen passivation of the extended defect in polysilicon solar cell), " is published in the 21 theuropean Photovoltaic Solar Energy Conference and Exhibition (the 21st European photovoltaic solar meeting and fair), Dresden (Dresden), Germany, 4-8 day in September, 2006; A.Ebong, M.HiIaIi, A.Rohtagi, D.Meier and D.S.Ruby, " Beltfurnace gettering and passivation of n-web silicon for high-efficiencyscreen-printed front-surface field solar cells (through furnace for the n-network silicon of high efficiency reticulated printing front surface area solar cell is cooled down and passivation); " Progress in Photovoltaics:Research and Applications, 9, pp.327-332,2001; C.H.Seager, D.J.Sharp and J.K.G.Panitz, " the Passivation of grain boundaries in silicon passivation of crystal boundary (in the silicon), " J.Vac.Sci. & tech., 20, pp.430-435,1982; N.H.Nickel, N.M.Johnson and W.B.Jackson, " Hydrigen passivation of grain boundary defects in polycrystallinesilicon thin films (the hydrogen passivation of the grain boundary defects in polysilicon membrane); " Appl.Phys.Lett., 62, pp.3285-3287,1993; A.Ashok, " Research in hydrogen passivation of defectsand impurities in silicon (research about the hydrogen passivation of defect and impurity in silicon); " NRELReport No.NREL/SR-520-36096, in May, 2004; M.Lipinski, P.Panek, S.Kluska, P.Zieba, A.Szyszka and B.Paszkiewicz, " Defect passivation ofmulticrystalline silicon solar cells by silicon nitride coatings (the defect passivation that the use silicon nitride of polysilicon solar cell is coated); " Materials Science-Poland, vol.24, pp.1003-1007,2006; V.Yelundur, " Understanding and implementation ofhydrogen passivation of defects in string ribbon silicon for high-efficiency; manufacturable; silicon solar cells (understanding of the hydrogen passivation of the defect in the wire drawing band silicon of the silicon solar cell that can manufacture for high efficiency and realization); " Ph.D thesis, Georgia Institute ofTechnology, Atlanta, GA, Nov.2003).
Although all types of one-axial texture, biaxial texture or three axle texture are all pay close attention in metal or alloy substrate, what be subject to special concern is the crystalline orientation of three types.These comprise { 100}<100>, { 110}<100> and { 210}<100> orientation.In all these, <100> direction is parallel to the major axis of the band through thermo-mechanical processi, rolling and recrystallization.{ 100}<100> is by producing at the annealing temperature of the primary recrystallization temperature higher than metal or alloy.{ 110}<100> is with { 210}<100> orientation is by producing at the annealing temperature of the secondary recrystallization temperature higher than metal or alloy.100}<100> is oriented in many Face-centred Cubic Metals and alloy, such as Ni, Al and Cu base alloy, and in easily produce.110}<100> texture such as, at bcc metals and alloy, ferrous alloy, and in the most easily produce.{ 210}<100> is oriented in the alloy of such as Ni-Fe alloy and easily produces.For the manufacture of such have the thermomechanical of the substrate of texture to process can be expanded to manufacture there is the length of random length and wide substrate.
The very large part of the silicon wafer used in global photovoltaic industry is with the form of 8 inches of wafers, and electronics industry refusal use 8 inches of wafers.These wafers containing many defects are monocrystalline in crystallography in addition, and have the area of 50.2 square inches (50.2 square inches).Recently, global electronic manufacture workshop more exchange device to adapt to the silicon wafer of 12 larger inch diameters.Photovoltaic industry likely uses unaccepted containing the defective wafer with the diameter of 12 inches and the area of 113 square inches.But this is available and can in the maximum possible size of the single-crystal wafer of whole world growth.The present invention allows people to manufacture to be greater than semi-conducting material that the is flexibility of 50.2 square inches or 113.0 square inches, large-area, monocrystalline or near single.Thermomechanical processing and manufacturing can be used to have metal and the alloy substrate of texture, there is to produce { 100}<100>, { 110}<100> and the { material of 210}<100> texture.Under these circumstances, the continuous print sheet of large-area substrate can be manufactured, deposit epitaxial layers thereon, obtain the electronic device of three axle texture.There is the length more than 100 meters and be possible close to the substrate of the width of a meter.In addition, as instructed before, some method for produce single crystal or single grained metals and/or alloy substrate is continuously possible.
Except the texturing by thermomechanical processing approach, other known manufacture is also had to have the approach of the substrate of the flexibility of texture, such as ion beam assisted depositing (IBAD), inclination substrate deposition (ISD) and the deposition under the existence in magnetic field.IBAD technique at United States Patent (USP) the 6th, 632,539,6,214,772,5,650,378,5,872,080,5,432,151,6,361,598,5,872,080,6,190,752,6, describe in 756,139,6,884,527,6,899,928,6,921, No. 741; ISD technique at United States Patent (USP) the 6th, 190,752 and 6,265, in No. 353 describe; And the biaxial texture formed by the deposition under the existence in magnetic field describes in No. 6346181st, United States Patent (USP); All these patents are all incorporated herein by reference.Also texture in face can be obtained by optionally Growing Process of Crystal Particles to post-deposition ion bombardment (Post-deposition ion-bombardment) of the metal of the one-axial texture on the polycrystalline substrates of non-oriented and/or alloy film, and in extreme situations, film can become three axle texture.In all these techniques, employ flexible, polycrystalline, untextured substrate or amorphous substrate, buffer layer deposition on such substrates.One in crucial resilient coating is the layer using IBAD, ISD or the deposition in magnetic field and deposit biaxial texture over the substrate.Once grown the resilient coating of texture, then semiconductor layer is having the resilient coating Epitaxial growth of texture.In each in above-mentioned situation, the device having the area being greater than 113.0 square inches that can not be obtained by the crystal growth of silicon or any other semiconductor can be grown.
Figure 18 show the various preferred embodiments in addition of the sandwich construction according to the present invention and embodiment 1 with the Utopian schematic diagram of cross-sectional form.Figure 18 A shows metal or alloy substrate that is flexible, crystalline, that crystallography has texture; The crystallography of types of flexure has the TiN resilient coating of texture, and the Si of extension or other semiconductor device or template layer.
Embodiment 4: start with the Ni-3at%W substrate of biaxial texture by electron beam evaporation, sputtering, pulse laser ablation or chemical vapour deposition (CVD) is the epitaxial loayer growing the thick MgO of 10-75nm under the underlayer temperature of 300 DEG C-850 DEG C in scope.By electron beam evaporation, sputtering, pulse laser ablation or chemical vapour deposition (CVD) be the epitaxial loayer depositing the thick TiN of 10-75nm under the underlayer temperature of 300 DEG C-850 DEG C subsequently in scope.Use chemical vapour deposition (CVD) at the Si layer of the temperature range deposit epitaxial of 300 DEG C-900 DEG C subsequently.Figure 18 B shows metal or alloy substrate that is flexible, crystalline, that crystallography has texture; The crystallography of types of flexure has the MgO resilient coating of texture; Crystallography above MgO layer there is the TiN resilient coating of texture; And the Si of extension or other semiconductor device or template layer.
Embodiment 5: start with the Ni-3at%W substrate of biaxial texture by electron beam evaporation, sputtering, pulse laser ablation or chemical vapour deposition (CVD) is grow the thick Y of 10-75nm under the underlayer temperature of 300 DEG C-850 DEG C in scope 2o 3epitaxial loayer.By electron beam evaporation, sputtering, pulse laser ablation or chemical vapour deposition (CVD) be the epitaxial loayer depositing the thick YSZ of 10-75nm under the underlayer temperature of 300 DEG C-850 DEG C subsequently in scope.By electron beam evaporation, sputtering, pulse laser ablation or chemical vapour deposition (CVD) be the epitaxial loayer depositing the thick TiN of 10-75nm under the underlayer temperature of 300 DEG C-850 DEG C subsequently in scope.Use chemical vapour deposition (CVD) at the Si layer of the temperature range deposit epitaxial of 300 DEG C-900 DEG C subsequently.Figure 18 C shows metal or alloy substrate that is flexible, crystalline, that crystallography has texture; The crystallography of types of flexure has the Y of texture 2o 3resilient coating; At Y 2o 3the crystallography of layer top there is the YSZ resilient coating of texture; Crystallography above YSZ layer there is the TiN resilient coating of texture; And the Si of extension or other semiconductor device or template layer.
Embodiment 6: start with the Ni-3at%W substrate of biaxial texture by electron beam evaporation, sputtering, pulse laser ablation or chemical vapour deposition (CVD) is grow the thick Y of 10-75nm under the underlayer temperature of 300 DEG C-850 DEG C in scope 2o 3epitaxial loayer.By electron beam evaporation, sputtering, pulse laser ablation or chemical vapour deposition (CVD) be the epitaxial loayer depositing the thick YSZ of 10-75nm under the underlayer temperature of 300 DEG C-850 DEG C subsequently in scope.By electron beam evaporation, sputtering, pulse laser ablation or chemical vapour deposition (CVD) be the epitaxial loayer depositing the thick MgO of 10-75nm under the underlayer temperature of 300 DEG C-850 DEG C subsequently in scope.By electron beam evaporation, sputtering, pulse laser ablation or chemical vapour deposition (CVD) be the epitaxial loayer depositing the thick TiN of 10-75nm under the underlayer temperature of 300 DEG C-850 DEG C subsequently in scope.Use chemical vapour deposition (CVD) at the Si layer of the temperature range deposit epitaxial of 300 DEG C-900 DEG C subsequently.Figure 18 D shows metal or alloy substrate that is flexible, crystalline, that crystallography has texture; The crystallography of types of flexure has the Y of texture 2o 3resilient coating; At Y 2o 3the crystallography of layer top there is the YSZ resilient coating of texture; Crystallography above YSZ layer there is the MgO resilient coating of texture; Crystallography above MgO layer there is the TiN resilient coating of texture; And the Si of extension or other semiconductor device or template layer.In each when shown in Figure 18, nitride layer can be formed in the interface of top buffer layer and semiconductor device or template layer, such as silicon nitride or nitrogenize germanium layer.This layer not necessarily needs to be have texture or extension.
It is other with the Utopian schematic diagram of cross-sectional form that Figure 19 shows according to the various embodiments of sandwich construction of the present invention.Figure 19 A shows metal or alloy substrate that is flexible, crystalline, that crystallography has texture; At least one crystallography of types of flexure has cube nitride buffer layer of texture, and the Si of extension or other semiconductor device or template layer.Figure 19 B shows metal or alloy substrate that is flexible, crystalline, that crystallography has texture; The crystallography of types of flexure has the MgO resilient coating of texture; At least one crystallography above MgO layer there is cube nitride buffer layer of texture; And the Si of extension or other semiconductor device or template layer.Figure 19 C shows metal or alloy substrate that is flexible, crystalline, that crystallography has texture; The crystallography of types of flexure has the Y of texture 2o 3resilient coating; At Y 2o 3the crystallography of layer top there is the YSZ resilient coating of texture; At least one crystallography above YSZ layer there is cube nitride buffer layer of texture; And the Si of extension or other semiconductor device or template layer.Figure 19 D shows metal or alloy substrate that is flexible, crystalline, that crystallography has texture; The crystallography of types of flexure has the Y of texture 2o 3resilient coating; At Y 2o 3the crystallography of layer top there is the YSZ resilient coating of texture; Crystallography above YSZ layer there is the MgO resilient coating of texture; At least one crystallography above MgO layer there is cube nitride buffer layer of texture; And the Si of extension or other semiconductor device or template layer.In each when shown in Figure 19, nitride layer can be formed in the interface of top buffer layer and semiconductor device or template layer, such as silicon nitride or nitrogenize germanium layer.This layer not necessarily needs to be have texture or extension.
Embodiment 7: start with the Ni-3at%W substrate of biaxial texture by electron beam evaporation, sputtering, pulse laser ablation or chemical vapour deposition (CVD) is grow the thick γ-Al of 10-75nm under the underlayer temperature of 300 DEG C-850 DEG C in scope 2o 3epitaxial loayer.Use chemical vapour deposition (CVD) at the Si layer of the temperature range deposit epitaxial of 300 DEG C-900 DEG C subsequently.Exist in the literature many about Si at γ-Al 2o 3on epitaxially grown report (see, such as, Liwen tan, Qiyuan Wang, Jun Wang, Yuanhuan Yu, Zhongli Liu and Lanying Lin, " Fabrication of novel double-hetero-epitaxial SOIstructure Si/ γ-Al 2o 3/ Si (novel dual heteroepitaxy SOI structure Si/ γ-Al 2o 3the manufacture of/Si), " Journal of Crystal Growth, vol.247, pp.255-260,2003; K.Sawada, M.Ishida, T.Nakamura and N.Ohtake, " Metalorganic moelecular beam epitaxy of films onSi at low growth temperatures (the Metal Organic Molecular Beam extension of the film under low growth temperature on Si); " Appl.Phys.Lett., vol.52, pp.1672-1674,1988; M.Shahjahan, Y.Koji, K.Sawada and M.Ishida, " Fabrication of resonance tunnel diode bygamma-Al 2o 3/ Si multiple heterostructures (uses γ-Al 2o 3the multiple heterostructure of/Si manufactures resonant tunneling diode), " Japan.J.of Appl.Phys.Part 1, vol.41 (4B), pp.2602-2605,2002).Figure 20 show the various embodiments of the sandwich construction according to the present invention and the present embodiment with the Utopian schematic diagram of cross-sectional form.Figure 20 A shows metal or alloy substrate that is flexible, crystalline, that crystallography has texture; The crystallography of types of flexure has the γ-Al of texture 2o 3resilient coating, and the Si of extension or other semiconductor device or template layer.
Embodiment 8: start with the Ni-3at%W substrate of biaxial texture, makes deposited by electron beam evaporation, sputtering, pulse laser ablation or the chemical vapour deposition (CVD) MgO that epitaxial deposition 10-75nm is thick on NiW substrate under scope is the underlayer temperature of 300 DEG C-700 DEG C or TiN layer.By electron beam evaporation, sputtering, pulse laser ablation or chemical vapour deposition (CVD) be deposit the thick γ-Al of 10-75nm under the underlayer temperature of 300 DEG C-850 DEG C subsequently in scope 2o 3epitaxial loayer.Use chemical vapour deposition (CVD) at the Si layer of the temperature range deposit epitaxial of 300 DEG C-900 DEG C subsequently.Figure 20 B shows the schematic diagram according to the present invention and the present embodiment.Figure 20 B shows metal or alloy substrate that is flexible, crystalline, that crystallography has texture; The crystallography of types of flexure has the MgO resilient coating of texture; Crystallography above MgO layer there is the γ-Al of texture 2o 3resilient coating; And the Si of extension or other semiconductor device or template layer.
Embodiment 9: start with the Ni-3at%W substrate of biaxial texture, makes deposited by electron beam evaporation, sputtering, pulse laser ablation or the chemical vapour deposition (CVD) Y that epitaxial deposition 10-75nm is thick on NiW substrate under scope is the underlayer temperature of 300 DEG C-700 DEG C 2o 3layer.By electron beam evaporation, sputtering, pulse laser ablation or chemical vapour deposition (CVD) be the epitaxial loayer depositing the thick YSZ of 10-75nm under the underlayer temperature of 300 DEG C-850 DEG C subsequently in scope.Under scope is the underlayer temperature of 300 DEG C-850 DEG C, the thick γ-Al of 10-75nm is deposited subsequently by electron beam evaporation or sputtering or pulsed laser deposition 2o 3epitaxial loayer.Use chemical vapour deposition (CVD) at the Si layer of the temperature range deposit epitaxial of 500 DEG C-900 DEG C subsequently.Figure 20 C shows the schematic diagram according to the present invention and the present embodiment.Figure 20 C shows metal or alloy substrate that is flexible, crystalline, that crystallography has texture; The crystallography of types of flexure has the Y of texture 2o 3resilient coating; At Y 2o 3the crystallography of layer top there is the YSZ resilient coating of texture; Crystallography above YSZ layer there is the γ-Al of texture 2o 3resilient coating; And the Si of extension or other semiconductor device or template layer.
Embodiment 10: start with the Ni-3at%W substrate of biaxial texture, makes deposited by electron beam evaporation, sputtering, pulse laser ablation or the chemical vapour deposition (CVD) Y that epitaxial deposition 10-75nm is thick on NiW substrate under scope is the underlayer temperature of 300 DEG C-700 DEG C 2o 3layer.By electron beam evaporation, sputtering, pulse laser ablation or chemical vapour deposition (CVD) be the epitaxial loayer depositing the thick YSZ of 10-75nm under the underlayer temperature of 300 DEG C-850 DEG C subsequently in scope.By electron beam evaporation, sputtering, pulse laser ablation or chemical vapour deposition (CVD) be the epitaxial loayer depositing the thick MgO of 10-75nm under the underlayer temperature of 300 DEG C-850 DEG C subsequently in scope.By electron beam evaporation, sputtering, pulse laser ablation or chemical vapour deposition (CVD) be deposit the thick γ-Al of 10-75nm under the underlayer temperature of 300 DEG C-850 DEG C subsequently in scope 2o 3epitaxial loayer.Use chemical vapour deposition (CVD) at the Si layer of the temperature range deposit epitaxial of 300 DEG C-900 DEG C subsequently.Figure 20 D shows the schematic diagram according to the present invention and the present embodiment.Figure 20 D shows metal or alloy substrate that is flexible, crystalline, that crystallography has texture; The crystallography of types of flexure has the Y of texture 2o 3resilient coating; At Y 2o 3the crystallography of layer top there is the YSZ resilient coating of texture; Crystallography above YSZ layer there is the MgO resilient coating of texture; Crystallography above MgO layer there is the γ-Al of texture 2o 3resilient coating; And the Si of extension or other semiconductor device or template layer.Figure 21 shows the configuration similar to Figure 20, replaces γ-Al unlike using any other cubic oxide thing 2o 3resilient coating.This cubic oxide nitride layer also can be graduate oxide skin(coating), to provide better Lattice Matching to the semiconductor layer of extension.
Embodiment 11: start with the experimental arrangement of embodiment 1-10, is deposited on germanium (Ge) or Si on top buffer layer or selectable semiconductor module flaggy.Subsequently by the GaAs layer of chemical vapour deposition (CVD) deposit epitaxial.The InGaP layer of deposit epitaxial subsequently.Then depositing transparent conductors, deposits antireflection coating and metal grid lines subsequently.Manufacture the device that Figure 22 schematically shows now.In Fig. 3 B, 4,5 and 6, discussed the object manufacturing such multijunction device above, and the larger part that target is spectrum by catching the sun improves photoelectric conversion efficiency.Resilient coating and the selectable substrate having the semiconductor module flaggy of texture can be had according to the instruction preparation in embodiment 1-10.During the manufacture of the device shown in the present embodiment, can be formed in the interface of top buffer layer untextured or have the conversion zone of texture, to form nitride or oxide together with semiconductor, such as silicon nitride or silicon dioxide layer.
Embodiment 12: starting (or the surface of clean substrate can be come by electropolishing and make that it is more level and smooth by chemical etching and/or planarization, reactive ion etching, mechanical polishing) with that have the polycrystalline on level and smooth and clean surface, flexible Ni alloy substrate, using inclination substrate deposition (ISD) by electron-beam evaporation crystallography there being the MgO layer of texture.By before inclination substrate deposition deposition techniques MgO layer, can deposit selectable amorphous or polycrystalline layer.During ISD, substrate tilts towards MgO steam with the angle of 25 °-30 ° between depositional stage.Use the high deposition rate of > 3nm/s.Growth that use is covered (shadowing) carries out selects to cause only MgO crystal grain to have the surface inclination of arrangement good face in and about 20 °.Use sputters at depositing TiN layer on this MgO layer.The silicon layer of deposit epitaxial subsequently.Further resilient coating is combined, is suitable for the instruction in embodiment 1-11.
Embodiment 13: start with the experimental arrangement of embodiment 10, deposit Germanium (Ge) layer on the Si layer of extension.Subsequently by the GaAs layer of chemical vapour deposition (CVD) deposit epitaxial.The InGaP layer of deposit epitaxial subsequently.Then depositing transparent conductors, deposits antireflection coating and metal grid lines subsequently.
Embodiment 14: starting (or the surface of clean substrate can be come by electropolishing and make that it is more level and smooth by chemical etching and/or planarization, reactive ion etching, mechanical polishing) with that have the polycrystalline on level and smooth and clean surface, flexible Ni alloy substrate, using inclination substrate deposition (ISD) by electron-beam evaporation crystallography there being the MgO layer of texture.By before inclination substrate deposition deposition techniques MgO layer, can deposit selectable amorphous or polycrystalline layer.During ISD, substrate tilts towards MgO steam with the angle of 25 °-30 ° between depositional stage.Use the high deposition rate of > 3nm/s.Use and cover the growth carried out and select to cause only MgO crystal grain to have the surface inclination of arrangement good face in and about 20 °.Be under the underlayer temperature of 700 DEG C-850 DEG C, make deposited by electron beam evaporation on this MgO layer, deposit the thick γ-Al of 50nm in scope 2o 3epitaxial loayer.The silicon layer of deposit epitaxial subsequently.
Embodiment 15: start with the experimental arrangement of embodiment 14, deposit Germanium (Ge) layer on the Si layer of extension.Subsequently by the GaAs layer of chemical vapour deposition (CVD) deposit epitaxial.The InGaP layer of deposit epitaxial subsequently.Then depositing transparent conductors, deposits antireflection coating and metal grid lines subsequently.
Embodiment 16: start (and/or the planarization of the deposition of amorphous layer, reactive ion etching, mechanical polishing can be used or come the surface of clean substrate by electropolishing and make that it is more level and smooth by chemical etching) with that have the polycrystalline on level and smooth and clean surface, flexible Ni alloy substrate, use the technique that United States Patent (USP) 6190752 is instructed, use ion beam assisted depositing (IBAD), by electron beam evaporation or sputtering sedimentation crystallography there being the MgO layer of texture.By before IBAD deposition techniques MgO layer, can deposit selectable amorphous or polycrystalline layer.Then sputtering, evaporation or chemical vapour deposition (CVD) Direct precipitation TiN layer on the layer of this ion assisted deposition is used.The silicon layer of deposit epitaxial subsequently.
Embodiment 17: start with the experimental arrangement of embodiment 16, deposit Germanium (Ge) layer on the Si layer of extension.Subsequently by the GaAs layer of chemical vapour deposition (CVD) deposit epitaxial.The InGaP layer of deposit epitaxial subsequently.Then depositing transparent conductors, deposits antireflection coating and metal grid lines subsequently.
Embodiment 18: start (or the surface of clean substrate can be come by electropolishing and make that it is more level and smooth by chemical etching and/or planarization, reactive ion etching, mechanical polishing) with that have the polycrystalline on level and smooth and clean surface, flexible Ni alloy substrate, use R.H ü hne, S. b.Holzapfel, " Thin biaxially textured TiN films on amorphous substratesprepared by ion-beam assisted pulsed laser deposition (being prepared the TiN film of thin biaxial texture by Assisted by Ion Beam pulsed laser deposition on amorphous substrate); " Appl.Phys.Lett., vol.85, pp.2744-2746, the technique of 2004 instructions, use ion beam assisted depositing (IBAD), by electron-beam evaporation crystallography there being the TiN layer of texture.Then ion is not used to assist the selectable deposition of the TiN of homoepitaxy.By before IBAD deposition techniques MgO layer, can deposit selectable amorphous or polycrystalline layer.The silicon layer of deposit epitaxial subsequently.
Embodiment 19: start with the experimental arrangement of embodiment 18, deposit Germanium (Ge) layer on the Si layer of extension.Subsequently by the GaAs layer of chemical vapour deposition (CVD) deposit epitaxial.The InGaP layer of deposit epitaxial subsequently.Then depositing transparent conductors, deposits antireflection coating and metal grid lines subsequently.
Embodiment 20: start with the instruction in embodiment 1, forms the heterostructure of NiW/TiN/Si.Then on Si layer, deposit the graduate semiconductor module flaggy of Si-Ge.The lattice mismatch of 4% is had between silicon and germanium.If directly deposited on Si layer by epitaxial deposition, so this lattice mismatch applies huge stress on Ge film, and can cause occurring many crystal defects.Therefore, when Si-Ge layer growth, the content of germanium is increased to gradually is almost pure germanium.Ge layer is provided for the excellent Lattice Matching of the growth of GaAs.Graduate semiconductor die approach also reduces the thermal expansion mismatch (thermal expansion mismatch) between the semiconductor module flaggy of top and semiconductor device layer.
Embodiment 21: start with the instruction in embodiment 1, forms the heterostructure of NiW/TiN.Then the upper graduate nitride layer of composition is deposited on, to form the good Lattice Matching with silicon in top layer.Then at " graduate resilient coating " upper epitaxial deposition Si.Then on Si layer, deposit the graduate semiconductor module flaggy of Si-Ge.The lattice mismatch of 4% is had between silicon and germanium.If directly deposited on Si layer by epitaxial deposition, so this lattice mismatch applies huge stress on Ge film, and can cause occurring many crystal defects.Therefore, when Si-Ge layer growth, the content of germanium is increased to gradually is almost pure germanium.Ge layer is provided for the excellent Lattice Matching of the growth of GaAs.Graduate semiconductor die approach also reduces the thermal expansion mismatch between the semiconductor module flaggy of top and semiconductor device layer.
Embodiment 22: start with the Ni-3at%W substrate of biaxial texture, makes deposited by electron beam evaporation, sputtering or the chemical vapour deposition (CVD) Y that epitaxial deposition 10-75nm is thick on NiW substrate under scope is the underlayer temperature of 300 DEG C-700 DEG C 2o 3layer.Subsequently according to Jin-Hyo Boo, S.A.Ustin and W.Ho, " Supersonic jet epitaxy of single crystalline cubic SiC thin films on Sisubstrates from t-Butyldimethvlsilane (being carried out the supersonic jet extension of single crystalline cube SiC film on a si substrate by t-butyldimethyl silane); " Thin solid Films, vol.324, pp.124-128, the program of 1998, uses the epitaxial loayer of cube SiC or the β-SiC that chemical vapour deposition (CVD) deposition 10-75nm is thick.Use chemical vapour deposition (CVD) at the Si layer of the temperature range deposit epitaxial of 300 DEG C-900 DEG C subsequently.
Although GaAs layer can combine with large-area, flexible substrate described above, GaAs also can directly at perovskite oxide such as SrTiO 3upper growth (see, such as, K.Eisenbeiser, R.Emrick, R.Droopad, Z.Yu, J.Finder, S.Rockwell, J.Holmes, C.Overgaard, and W.Ooms, " GaAs MESFETs Fabricated on Si SubstratesUsing a SrTiO 3buffer Layer (uses SrTiO on a si substrate 3the GaAs MESFET that resilient coating manufactures), " IEEE Electron Device Letters, Vol.23, No.6, pp.300-302,2002; Droopad R, Yu ZY, Li H, Liang Y, Overgaard C, Demkov A, Zhang XD, MooreK, Eisenbeiser K, Hu M, Curless J, Finder J, " Development of integrated heterostructures on silicon by MBE (by the heterostructure of MBE growth one on silicon), " Journal of Crystal Growth, vol.251 (1-4), pp.638-644,2003).Report the substrate of the epitaxially grown compliance of the compound semiconductor for such as GaAs in this study.First at Si single-crystal wafer Epitaxial growth perovskite type buffer layer, such as SrTiO 3.After being grown, at SrTiO 3the SiO that thickness is about 20 dusts is formed between layer and Si substrate 2thin amorphous layer.This thin amorphous layer as on mechanics with the elastic membrane of Si substrate uncoupling (decoupled).If also keep SrTiO 3layer is as thin as about 50 dusts, and the final mismatch ratio 4% so between GaAs layer and Si is much lower, if GaAs directly grows on Si.This obtains the GaAs layer of the better quality of less defect certainly.
Embodiment 23: start with the Ni-3at%W substrate of biaxial texture, makes deposited by electron beam evaporation, sputtering or the chemical vapour deposition (CVD) Y that epitaxial deposition 10-75nm is thick on NiW substrate under scope is the underlayer temperature of 300 DEG C-700 DEG C 2o 3layer.Under the substrate deposition temperature of 300 DEG C-700 DEG C, use radio frequency sputtering (rf-sputtering) at Y subsequently 2o 3the SrTiO that on layer, epitaxial deposition 100nm is thick 3layer.Then K.Eisenbeiser is used in, R.Emrick, R.Droopad, Z.Yu, J.Finder, S.Rockwell, J.Holmes, C.Overgaard and W.Ooms, " GaAs MESFETs Fabricated on SiSubstrates Using a SrTiO 3buffer Layer, " IEEE Electron Device Letters, Vol.23, No.6, pp.300-302, 2002 and Droopad R, Yu ZY, Li H, Liang Y, OvergaardC, Demkov A, Zhang XD, Moore K, Eisenbeiser K, Hu M, Curless J, Finder J, " Development of integrated hetero structures on silicon by MBE, " Journal ofCrystal Growth, vol.251 (1-4), pp.638-644, the program of general introduction in 2003, use molecular beam epitaxy (MBE) at SrTiO 3heteroepitaxial deposition GaAs layer on layer.
Embodiment 24: start (or the surface of clean substrate can be come by electropolishing and make that it is more level and smooth by chemical etching and/or planarization, reactive ion etching, mechanical polishing) with that have the polycrystalline on level and smooth and clean surface, flexible Ni alloy substrate, use in room temperature the SiO that magnetron sputtering deposition 50nm is thick 2layer.Then the gold thin film of one-axial texture is deposited in high vacuum conditions.Before deposited gold film, bombard with 1keVAr+ and carry out clean SiO in 1 minute 2the surface of layer, obtains strong (111) fibrous texture in golden film.Then use 1.0-3.5MeV N+, Ne+ and Ar+ ion, irradiate gold thin film with the ion beam direction of the angle becoming 35.24 with surface normal.Use 10 17ion/cm 2ion current density (ionfluence) and target current in the scope of 10-100nA scope, depend on ionic species.Between the light period, temperature is remained on liquid nitrogen temperature.After the procedure, golden film all shows texture in all directions.Program for the manufacture of the golden film of near single summarizes (OlligesS in the prior art in more detail, Gruber P, Bardill A, Ehrler D, Carstanj en HD and Spolenak R, " Convertingpolycrystals into single crystals-Selective grain growth by high-energy ionbombardment (polycrystal is converted into monocrystalline--use the selectivity grain growth of high-energy ion bombardment); " Acta Meterialia, vol.54, pp.5393-5399).Then reactive sputtering extension depositing TiN layer on this golden film is used, subsequently by CVD epitaxial deposition Si layer.This obtains the semiconductor layer crystallography on polycrystalline substrates having texture.
Another kind of the multilayer that comprises resilient coating and semiconductor device layer of epitaxial deposition thereon can be one-axial texture but the substrate with large mean grain size to obtain high performance suitable substrate.Such as, know, simply by single shaft extruding, very sharp keen one-axial texture can be obtained in a lot of metal and alloy.One-axial texture makes the axis perpendicular to substrate of all crystal grains all arrange.If improve mean grain size by annealing and/or abnormal grain growth now, so mean grain size can become very large and diametrically more than 100 microns.As long as grain size is larger than the recombination length of semiconductor, so semiconductor layer will not be subject to the impact spreading the crystal boundary semiconductor layer from substrate substantially.When substrate itself be non-oriented and polycrystalline or amorphous time, also can give the strong one-axial texture of megacryst granularity in resilient coating.This can by abnormal grain growth (such as, with reference to prior art J.M.E.Harper, J.Gupta, D.A.Smith, J.W.Chang, K.L.Holloway, D.P.Tracey and D.B.Knorr, " Crystallographic texture change during abnormal grain growth inCu-Co thin films (crystallographic texture during the abnormal grain growth in Cu-Co film changes), " Appl.Phys.Lett, vol.65, pp.177-179, 1994) or by the grain growth of Ions Bombardment (such as, with reference to prior art T.Ohmi, T.Saito, M.Otsuki, T.Shibuta and T.Nitta, " Formation of copper thin films by a low kinetic energy particle process (forming Copper thin film by low kinetic energy particle technique), " J.of Electrochemical Soc, vol.138, pp.1089-1097, 1991) come.In all these situations, in fact device has " local " the three axle texture having megacryst granularity.This biaxial texture being greater than the local of the recombination length of semiconductor for the manufacture of polycrystalline device layer in length dimension will cause having the photovoltaic cell of the efficiency similar to the efficiency of the photovoltaic cell being substantially monocrystalline, because crystal boundary will not affect performance.
A lot of technology can be used to carry out the deposition of semiconductor layer.Many in these technology obtained recently summary (see, such as, Michelle J.McCann, Kylie R.Catchpole, Klaus J.Weber, Andrew W.Blakers, " A review of thin-film crystalline silicon for solarcell applications.Part 1:Native substrates, " Solar Energy Materials and SolarCells, 68th volume, 2nd phase, May calendar year 2001,135-171 page; Kylie R.Catchpole, Michelle J.McCann, Klaus J.Weber and Andrew W. Blakers, " A review ofthin-film crystalline silicon for solar cell applications.Part 2:Foreignsubstrates ", Solar Energy Materials and Solar Cells, the 68th volume, the 2nd phase, May calendar year 2001,173-215 page).In addition, any preparation technology in low temperature also all receives publicity, because it will reduce the phase counterdiffusion of element from metal/alloy substrate to semiconductor device layer further.Explored many preparation technology in low temperature for Si (see, such as, Lars Oberbeck, Jan Schmidt, Thomas A.Wagner and RaIf B.Bergman, " High rate deposition of epitaxiallayers for efficient low-temperature thin film epitaxial silicon solar cells (high rate deposition of the epitaxial loayer of high efficient cryogenic thin film epitaxy silicon solar cell), " Progress inPhotovoltaics: Research and Applications, vol.9, pp.333-340, 2001, J.Carabe and J.J.Gandia, " Thin-film-silicon Solar Cells (thin film silicon solar cell), " OPTO-Electronics Review, vol.12, pp.1-6,2004, S Summers, H S Reehal and G H Shirkoohi, " The effects of varying plasma parameters on silicon thin filmgrowth by ECR plasma CVD (different plasma parameters is on the impact using the silicon thin film of ECR plasma CVD to grow), " J.Phys.D:Appl.Phys.Vol.34, pp.2782-2791,2001, Thomas A.Wagner, Ph.D thesis, " Low temperature silicon epitaxy:Defects and electronic properties (Low-temperature Si epitaxy: defect and electronic property), " Institut furPhysikalische Elektronik der Universit at Stuttgart (Universitaet Stuttgart physical electronic institute journal), 2003, Hattangady, S.V., Posthill, J.B., Fountain, G.G, Rudder R.A., Mantini and M.J., Markunas, R.J., " Epitaxial silicon deposition at 300 DEG C of withremote plasma processing using SiH 4/ H 2mixtures (uses SiH at 300 DEG C 4/ H 2the mixture epitaxial silicon deposition of remote plasma process), " Appl.Phys.Lett., vol.59 (3), pp.339-341,1991, Wagner, T.A., Oberbeck, L., and Bergmann, R.B., " Lowtemperature epitaxial silicon films deposited by ion-assisted deposition (the low-temperature epitaxy silicon thin film deposited by ion assisted deposition), " Materials Science & EngineeringB-Solid State Materials for Advanced Technology, vol.89, pp.1-3,2002, Overbeck, L., Schmidt, J., Wagner, T.A., and Bergmann R.B., " High-ratedeposition of epitaxial layers for efficient low-temperature thin film epitaxialsilicon solar cells (high rate deposition of the epitaxial loayer of high efficient cryogenic thin film epitaxy silicon solar cell), " Progress in Photovoltaics, vol.9 (5), pp.333-340,2001, Thiesen, J., Iwaniczko, E., Jones, K.M., Mahan, A., and Crandall, R., " Growth of epitaxialsilicon at low temperatures using hot-wire chemical vapor deposition (using hot line chemical vapor deposition growth epitaxial silicon under low temperature), " Appl.Phys.Lett., vol.75 (7), pp.992-994,1999, Ohmi, T., Hashimoto, K., Morita, M., Shibata, T., " Study onfurther reducing the epitaxial silicon temperature down to 250 DEG C of in low-energybias sputtering (and about in low energy bias sputtering by the research of further for epitaxial silicon temperature descending system 250 DEG C), " Journal of Appl.Phys., vol.69 (4), pp.2062-2071,1991).
About low temperature chemical vapor deposition (CVD) technique of the deposition for semiconductor layer, hot line CVD (Qi Wang, Charles W.Teplin, Paul Stradins, Bobby To, Kim M.Jones and Howard M.Branz, " Significant improvement in silicon chemical vapordeposition epitaxy above the surface dehydrogenation temperature (chemistry of silicones vapour deposition extension higher than remarkable improvement during surperficial desorption temperature), " J.of Appl.Phys., 100, 093520, 2006 and Charles W.Teplin, Qi Wang, Eugene Iwaniczko, Kim M.Jones, Mowafak Al-Jassim, Robert C.Reedy, Howard M.Branz, " Low-temperature silicon homoepitaxy by hot-wire chemical vapor depositionwith a Ta filament (the low temperature silicon homoepitaxy by using the hot wire chemical vapour deposition (CVD) of Ta silk to carry out), " Journal of Crystal Growth 287 (2006) 414-418), plasma asistance CVD (" Very Low Temperature Epitaxial Growth of Silicon Films for SolarCells (the pole low-temperature epitaxy growth of the silicon fiml of solar cell), " Jap.J.of Appl.Phys.46, 12, 7612-7618, 2007), ECR plasma CVD, middle plasma CVD (mesoplasma CVD) (Jose Mario A.Diaz, Munetaka Sawayanagi, Makoto Kambara, andToyonobu Yoshida, " Electrical Properties of Thick Epitaxial Silicon FilmsDeposited at High Rates and Low Temperatures by Mesoplasma ChemicalVapor Deposition (the thick epitaxial silicon film deposited by middle PCVD with two-forty and low temperature), " Japanese Journal of Applied Physics, Vol.46, No.8A, 2007, and gas jet plasma CVD (R.G.Sharafutdinoov pp.5315-5317), V.M.Karsten, S.Ya.Khmel, A.G.Cherkov, A.K.Gutakovskii, L.D.Pokrovsky and O.I.Semenova, " Epitaxial silicon films deposited at high rates by gas-jet electronbeam plasma CVD (by gas jet electron beam plasma CVD with the epitaxial silicon film of high rate deposition), " Surface and Coatings Technology, 174-175 rolls up, in September, 2003-October, 1178-1181 page), plasma CVD (the Yagi of electron-beam excitation, Y., Motegi, H., Ohshita, Y., Kojima, N., Yamaguchi, M., " High-speed growth of silicon thinfilms by EBEP-CVD using Si 2h 6(by using Si 2h 6eBEP-CVD high-speed rapid growth silicon thin film), " the 3rd photovoltaic energy conversion international conference, the 2003,2nd volume, 12-16 phase, in May, 2003,1667-1670 page Vol.2) receive publicity.
Also ex situ process deposits semiconductor layer can be used.In the process, first the precursor film of depositing semiconductor layers, make subsequently semiconductor layer epitaxial crystallization (see, such as, title is No. 2004/033769A1, the international patent application WO of " Fabricationmethod for crystalilne semiconductor on foreign substrates (for manufacturing crystalline method for semiconductor in foreign substrate) "; Ngo Duong Sinh, Gudrun Andra, Fritz Falk, Ekkehart Ose, Joachim Bergmann, " Optimization of Layered Laser Crystallization for Thin-Film CrystallineSilicon Solar Cells (optimization for the layering laser crystallization of film crystal silicon solar cell), " Solar Energy Materials & Solar Cells 74 (2002), 295-303; Nickel, N.H.; Brendel, K.; Saleh, R., " Laser crystallization of hydrogenated amorphoussilicon (laser crystallization of amorphous silicon hydride); " Physica status solidi.C.Conferences andcritical reviews, vol.1, no5, pp.1154-1168,2004; J.B.Boyce, J.P.Lu,, J.Ho, R.A.Street, K.van Schuylenbergh and Y.Wang, " Pulsed laser crystallizationof amorphous silicon for polysilicon flat panelimagers (the pulse laser crystallization for the amorphous silicon of polysilicon slab imager), " Journal of Non-Crystalline Solids, Vol.299-302, pp.731-735,2002; Lulli, G.; Merli, P.G.; Antisari, M.Vittori, " Solid-phase epitaxy of amorphous silicon induced by electron irradiation atroom temperature (solid phase epitaxy of the amorphous silicon of at room temperature being induced by electron radiation); " Physical Review B (Condensed Matter), 36th volume, 15th phase, on November 15th, 1987, pp.8038-8042; Mohadjeri, B.; Linnros, J.; Svensson, B.G.; Ostling, M., " Nickel-enhanced solid-phase epitaxial regrowth of amorphous silicon (solid phase epitaxial regrowth strengthened with nickel of amorphous silicon); " Physical Review Letters, 68th volume, 12nd phase, on March 23rd, 1992, pp.1872-1875; Yann Civale, Lis K.Nanver, PeterHadley, Egbert J.G.Goudena, and Hugo Schellevis, " Sub-500 DEG C of Solid-PhaseEpitaxy of Ultra-Abrupt p+-Silicon Elevated Contacts and Diodes (solid phase epitaxy below 500 DEG C of super sudden change silicon top layer contactor and diode), " IEEE Electron DeviceLetters, Vol.27,2006; Cline H.E., " A single crystal silicon thin-film formed bysecondary recrystallization (monocrystalline silicon thin film formed by secondary recrystallization); " Journal ofAppl.Phys., vol.55 (12), pp.4392-4397,1984; Santos, P.V.; Trampert, A.; Dondeo, F.; Comedi, D.; Zhu, H.J.; Ploog, K.H.; Zanatta, A.R.; Chambouleyron, I. " Epitaxial pulsed laser crystallization of amorphousgermanium on GaAs (the extension pulsed-laser crystallization of amorphous germanium on GaAs); " Journal ofApplied Physics, Vol.90, pp.2575-2581,2001; T.Sameshima, H.Watakabe, H.Kanno, T.Sadoh and M.Miyao, " Pulsed laser crystallization ofsilicon-germanium films (pulsed-laser crystallization of silicon-germanium film); " Thin Solid Films Vol.487pp.67-71,2005; R.D.Ott, P.Kadolkar, C.A.Blue, A.C.Cole and G.B.Thompson, " The Pulse Thermal Processing of Nanocrystalline SiliconThin-Films (the pulse heat process of Nano silicon-crystal thin film), " JOM, vol.56, pp.45-47, Oct., 2004).
Based on Cu (In, the Ga) Se of polycrystalline 2(CIGS) solar cell of film is also subject to greatly paying close attention to, and has confirmed the record efficiency of laboratory scale 19.2%.The expansion scale of this technique on the substrate of flexibility continues to carry out in the industry, but the efficiency obtained in process of production is much lower.Even if the high efficiency solar cell using CIGS thin film manufacture is also polycrystalline, the mean grain size of 2 μm of having an appointment.Up to the present, the definite effect of crystal boundary in CIGS solar cell or impact not yet obtain a lot of confirmations.Propose, oxygen can passivation originally by be harmful crystal boundary (see, such as, D.Cahen and R.Noufi, " Defect chemical explanation for theeffect of air anneal on CdS/CuInSe 2solar cell performance is (for air anneal to CdS/CuInSe 2the defect chemistry of the impact of solar cell properties is explained), " Appl.Phys.Lett., vol.54, pp.558-560,1989).Also propose, this useful oxidation of diffusing catalyst from sodium (Na) to crystal boundary (see, such as, L.Kronik, D.Cahen, and H.W.Schock, " Effects of Sodium on Polycrystalline Cu (In, Ga) Se 2(sodium is to polycrystalline Cu (In, Ga) Se for and Its Solar Cell Performance 2with the impact of its solar cell properties), " Advanced Materials, vol.10, pp.31-36,1999).Also propose, the compound electric charge carrier of grain boundaries different with the compound electric charge carrier of block (see, such as, M.J.Romero, K.Ramanathan, M.A.Contreras, M.M.Al-Jassim, R. Noufi, and P.Sheldon, " Cathodoluminescence ofCu (In, Ga) Se 2thin films used in high-efficiency solar cells is (for Cu (In, the Ga) Se in high efficiency solar cell 2the cathodoluminescence of film), " Appl.Phys.Lett., vol.83, pp.4770-4772,2003).Propose, due to the wider breach at grain boundaries, grain boundaries generation intrinsic passivation (intrinsic passivation) (see, such as Persson C, Zunger A., " Anomalous grain boundary physics in polycrystalline CuInSe 2: the existenceof a hole barrier (polycrystalline CuInSe 2in the crystal boundary physics of exception: the existence of hole barrier), " Phys.Rev.Lett.vol.91, pp.266401-266406,2003).Propose, the useful local built-in potential (built-in potential) of grain boundaries depend on Ga content (see, such as, C.-S.Jiang, R.Noufi, K.Ramanathan, J.A.AbuShama, H.R.Moutinho and M.M.Al-Jassim, " Local Built-in Potential on Grain Boundary of Cu (In, Ga) Se 2thin Films (Cu (In, Ga) Se 2local built-in potential on the crystal boundary of film), " meeting paper, NREL/CP-520-36981,2005).Report, grain boundaries have the minimizing of Cu content and this cause crystal boundary less adverse effect (see, such as, M.J.Hetzer, Y.M.Strzhemechny, M.Gao, M.A.Contreras, A.Zunger and L.J.Brillson, " Direct observation ofcopper depletion and potential changes at copper indium gallium diselenidegrain boundaries (for direct observation that is most at the copper loss of copper indium callium diselenide (CIGS) compound grain boundaries and potential change), " Appl.Phys.Lett.vol.86, pp.162105-162107, 2005).Also propose, crystallographic texture is also important for the solar cell based on CIGS of greater efficiency, (see, such as, S.Chaisitsak, A.Yamada and M.Konagai, " Preferred Orientation Controlof Cu (In 1-xga x) Se 2(x ≈ 0.28) Thin Films and Its Influence on Solar CellCharacteristics is (to Cu (In 1-xga x) Se 2the preferred orientation of (x ≈ 0.28) film control and its on the impact of characteristic of solar cell), " Jpn.J.Appl.Phys.vol.41, pp.507-513,2002).Gather, above these are researched and proposed, although crystal boundary may usually not be harmful in based on the solar cell of CIGS very much, importantly which kind of composition crystal boundary is, to control its electronically active.This needs for the very good control of grain boundary structure, and this is impossible in the CIGS film of random textures or bad one-axial texture.If have the battery of texture to control the orientation of all CIGS crystal grain by manufacturing in crystallography, then aborning (in run after run), the composition of CIGS film crystal boundary will be identical.This large-area battery based on CIGS that will people allowed in industrial setting to manufacture very high efficiency, and this is impossible at present.
Figure 23 shows the version that may be used for metal or alloy substrate of the present invention.Figure 23 A show compound substrate with the Utopian schematic diagram of cross-sectional form, described compound substrate containing with or without crystallographic texture or the bottom that do not arrange, and there is top surface that is that crystallography has texture or that arrange, all crystal grains in this layer is arranged in all directions in 10 degree.Figure 23 B show compound substrate with the Utopian schematic diagram of cross-sectional form, described compound substrate containing with or without crystallographic texture or the center that do not arrange, and there are top surface that is that crystallography has texture or that arrange and basal surface, all crystal grains in this layer is arranged in all directions in 10 degree.
The electronic instrument of the flexibility that the present invention relates to or other application of circuit limit in the various application of the applicability of rigid circuit board or manual wiring as attachment in flexibility, space saving or production constraint.Another general application of flexible circuit is in computer keyboard manufactures; Most of keyboards of current manufacture use flexible circuit as switch matrix.
Usually carry out device layer or film in the electronics industry with the manufacture of the mode of extension on substrate, for many application, such as, relate to those application of superconductor, semiconductor, magnetic material and electrooptical material.In in such applications many, by the oldered array of combining nano point, nanometer rods or nano particle second-phase material, can improve significantly or the performance of enhance device layer.In other cases, the combination of the oldered array of nano dot, nanometer rods or nano particle second-phase material can not be made in this way just can not getable newly with the character of novelty.In addition, in such applications many, large-area and long device layer is needed.This can be realized by the epitaxial growth of device layer on the substrate of biaxial texture of the oldered array containing nano dot, nanometer rods or nano particle second-phase material.Such as, in high-temperature superconductor field, sheet metal strip can be used, to be formed the extension superconducting layer with long (km) length by the epitaxial growth on the substrate of made biaxial texture, for the application of such as low-loss power line.Thermomechanical texturing can be used, by ion beam assisted depositing or the crystallography by the manufacture of inclination substrate deposition manufacture of intraocular there being the substrate (patent is incorporated to way of reference, as illustrated about in the instruction content of the mode of the substrate manufacturing above) of texture.
In a preferred embodiment of the present invention, at the growing period of device layer in conjunction with the self-assembled nanometer point of second-phase material.This can use the in-situ deposition technology that high temperature carries out that is deposited on of many wherein films to carry out.Original position film deposition technique comprises pulse laser ablation (PLD), chemical vapour deposition (CVD) (CVD), molecular chemistry vapour deposition (MOCVD), direct current (DC) or radio frequency (rf) sputtering, electron beam coevaporation, hot coevaporation and pulsed electron deposition (PED).
Due to the unbecoming strain (misfit strain) between second-phase and base film (matrix film), define self-assembled nanometer point and/or the nanometer rods of second-phase material.When the lattice parameter of the epitaxial film grown is different from the lattice parameter of second-phase material, there is lattice mismatch, obtain unbecoming strain.Nano dot and/or nanometer rods self self assembly, to minimize strain and therefore to minimize the energy of composite membrane.The specific sedimentary condition used at film growing period and the composition of second-phase combined or volume fraction control the size of nano dot and/or nanometer rods, shape and orientation.The lattice mismatch being greater than 3% had between film matrix and the material forming nano dot and/or nanometer rods is preferred.When being equal to or higher than this lattice mismatch, strained significantly, and obtained the clear and definite ordered arrangement of nano dot and nanometer rods.
In addition, be of the present invention another important benefit in conjunction with such self-assembled nanometer point of second-phase material and/or the ability of nanometer rods when carrying out independent or simultaneously deposition in device layer.This dramatically reduces the complexity of the device layer manufacturing such novelty.Specific implementation of the present invention is consisting of YBa 2cu 3o x(YBCO) obtain confirmation in high temperature superconducting film, in described high temperature superconducting film, consist of BaZrO 3(BZO) PLD is used to combine from the single target of the mixture of the nanometer powder containing YBCO and BZO between second-phase nano dot and nanometer rods depositional stage at the same time.
Embodiment 23: by carrying out laser ablation from the single target of mixture of the nano particle comprising YBCO powder and selected nonsuperconducting phase in conjunction with the self-assembled nanometer point of nonsuperconducting phase and nanometer rods.Material is BZO, CaZrO such as 3(CZO), YSZ, Ba xsr 1-xtiO 3etc. (BST) nano particle can be commercially available from supplier such as Sigma-Aldrich.There is scope to be mixed well with YBCO powder by mechanical mixture at the nano particle of the sharp keen particle size distribution of 10-100nm these, then cold pressing to form initial target.Then in the oxygen of flowing, targets are sintered at 950 DEG C.Then target is arranged on the target holder in pulsed laser deposition (PLD) experimental facilities.Important technically have Ni-5at%W (50 μm)/Y 2o 3(75nm)/YSZ (75nm)/CeO 2(75nm) rolling of formation is assisted on biaxial texture substrate (RABiTS) substrate and is deposited.Use XeCl (308nm) excimer laser LPX 305, with the repetition rate of 10Hz, the substrate deposition temperature of 790 DEG C and the partial pressure of oxygen of 120 mTorr, carry out PLD deposition.
By the preformed YBCO micron powder of mechanical mixture and commodity BZO nanometer powder, cold pressing subsequently and sinter to form target to prepare PLD target.By thermomechanical processing and manufacturing and by the Grown film of biaxial texture of near single forming Ni-3at%W or Ni-5at%W.Before the growth of multiple device layer, alloy substrate deposits Y 2o 3, yttria-stabilized zirconia (yttria stabilized zirconia) (YSZ) and CeO 2the multi-buffering-layer of extension.Substrate is arranged on heater block, and handle component is heated to presetting depositing temperature.The Optimal Temperature of film growth is measured by normal experiment.The optimal distance between target and the substrate of deposited film being used for PLD is also measured by normal experiment.Also be determined at depositional stage chien shih in order to form the background gas pressure that wherein YBCO and BZO is stable region (regime) by normal experiment.Figure 24 shows the thick YBa of 0.2 μm of the self-assembled nanometer point of the BZO of the substrate Epitaxial growth of the biaxial texture in the buffering having extension 2cu 3o x(YBCO) Cross-section transmission electron microscopic (TEM) image of layer.BaZrO can be seen in YBCO layer 3(BZO) post of self-assembled nanometer point.Post perpendicular to the ab face represented by the parallel lattice fringe in YBCO layer of YBCO, and is parallel to the c-axis of YBCO.Black arrow in figure shows the position of some in the post of the self-assembled nanometer point of BZO.Figure 25 shows the schematic diagram of the cross section of the structure of this expectation in the mode more summarized.There is shown the epitaxial device film had in the crystallography of the self-assembled nanometer point containing second-phase material on the substrate of texture.In this case, all posts of self-assembled nanometer point all arrange well in the direction perpendicular to substrate.Figure 26 shows the schematic diagram having the epitaxial device film on the substrate of texture in the crystallography of the self-assembled nanometer point containing second-phase material, and wherein the post of self-assembled nanometer point tilts well relative to the direction perpendicular to substrate.Figure 27 shows the schematic diagram having the epitaxial device film on the substrate of texture in the crystallography of the self-assembled nanometer point containing second-phase material, and wherein self-assembled nanometer point is not smooth but bends.Also the combination of the effect shown in Figure 25,26 and 27 can be there is at film growing period.
Because device that is that the present invention obtains crystallography has texture or near single, so their performance is excellent.But the present invention also obtains lower-cost device.Such as, in the typical production cost of crystal silicon solar energy battery module is analyzed, the cut-out of Si substrate, Battery disposal and module assembled account for 70% of the total cost of module.Use the present invention to manufacture solar cell, do not need to cut off and module assembled.Module assembled relates to much processed Si wafer is assembled into module, and it accounts for too individually. sun can battery module total cost 35%.In the present invention, the very large-area solar cell having texture of the process manufacture of continuous print or static state can be used.Then be suitably to device layout pattern, to divide various battery in a large-area module.
Electronic device according to the present invention may be used for being selected from the application of the group comprising photovoltaic device, flat-panel monitor, thermo-photovoltaic device, ferro-electric device, LED device, computer hard disc driver device, the device based on magnetic resistance, the device based on luminescence generated by light, nonvolatile memory device, dielectric devices, thermoelectric device and quantum dot laser device.In preferred embodiments, electronic device has the area being greater than 50 square inches.Again further in preferred embodiment, electronic device has the area being greater than 113 square inches.At least one can be comprised according to electronic device of the present invention and be selected from the device comprising following group: Double-end device, such as diode; Three termination devices, such as transistor, thyristor or rectifier; And multiterminal head device, such as microprocessor, random access memory, read-only memory or charge coupled device.
Be to be understood that, embodiment described herein and embodiment are only for illustrative object, and the various amendment carried out according to these embodiments and embodiment or change will be proposed by those skilled in the art and be included in the spirit and scope of the application.The present invention can take other particular forms, and does not depart from spirit of the present invention or this qualitative attribution.

Claims (63)

1. a polycrystalline electronic device, comprising:
A. metal or alloy substrate that is flexible, polycrystalline, it has [100] or the macroscopic view of [110], the recrystallization texture of single, outside face, single shaft, inlaying or sharpness of the texture that the half width (FWHM) be less than with 10 degree is feature, and the FWHM to be also less than with 10 degree to be feature single, texture in face, described substrate has surface;
B. on described substrate surface, there is at least one epitaxial buffer layer, at least one epitaxial buffer layer described is selected from and comprises metal, alloy, nitride, boride, oxide, fluoride, carbide, silicide, with intermetallic alloy or its group combined of germanium, described epitaxial buffer layer has the macroscopic view of [100] or [110], single, outside face, one-axial texture, inlaying or sharpness of the texture that the half width (FWHM) be less than with 10 degree is feature, and the FWHM to be also less than with 10 degree to be feature single, texture in face, described resilient coating has surface,
C. have on described buffer-layer surface at least one polycrystalline, the epitaxial loayer of semi-conducting material, described epitaxial loayer has the macroscopic view of [100] or [110], outside face, single, one-axial texture, inlaying or sharpness of the texture that the half width (FWHM) be less than with 10 degree is feature, described epitaxial loayer also has to be less than the FWHM of 10 degree to be feature single, texture in face;
D. described semiconductor is selected from and comprises indirect gap semiconductor, direct gap semiconductor, multiband semiconductor or its group combined.
2. electronic device according to claim 1, wherein, described indirect gap semiconductor is Si, Ge or GaP.
3. electronic device according to claim 1, wherein, described direct gap semiconductor is CdTe, CuInGaSe 2(CIGS), GaAs, AlGaAs, GaInP or AlInP.
4. electronic device according to claim 1, wherein, described multiband semiconductor is II-O-VI material or III-N-V material.
5. electronic device according to claim 4, wherein, described II-O-VI material is Zn 1-ymn yo xte 1-x.
6. electronic device according to claim 4, wherein, described III-N-V material is GaN xas 1-x-yp y.
7. the electronic device according to any one of claim 1-6, wherein, the epitaxial loayer of at least one semi-conducting material described comprises trace doped dose of N-shaped for obtaining or p-type semiconductor character.
8. electronic device according to claim 1, wherein, the epitaxial loayer of at least one semi-conducting material described is the compound semiconductor formed primarily of two or more elements not of the same clan from the periodic table of elements, comprise the compound of III-th family and V race, and the compound of II race and VI race.
9. electronic device according to claim 8, wherein, described III-th family compound is selected from B, Al, Ga and In, and described V compounds of group is selected from N, P, As, Sb and Bi, described II compounds of group is selected from Zn, Cd and Hg, and described VI compounds of group is selected from O, S, Se and Te.
10. electronic device according to claim 8 or claim 9, wherein, described compound semiconductor is binary and comprises the compound from described III-th family and V race.
11. electronic devices according to claim 10, wherein, described compound semiconductor is AlN, AlP, AlAs, GaN, GaP, GaAs, InP, InAs or InSb.
12. electronic devices according to claim 8 or claim 9, wherein, described compound semiconductor is binary and comprises the compound from described II race and VI race.
13. electronic devices according to claim 12, wherein, described compound semiconductor is ZnS, ZnSe, ZnTe, CdTe or HgTe.
14. electronic devices according to claim 8 or claim 9, wherein, described compound semiconductor is ternary.
15. electronic devices according to claim 14, wherein, described compound semiconductor is InGaAs, AlGaAs, InGaN or CdHgTe.
16. electronic devices according to claim 8 or claim 9, wherein, described compound semiconductor is quaternary.
17. electronic devices according to claim 16, wherein, described compound semiconductor is InGaAsP or AlInGaP.
18. electronic devices according to claim 1, wherein, the epitaxial loayer of at least one semi-conducting material described corresponding to the elemental semiconductor of the element in identical race or alloy, or comprises the compound semiconductor of element of the IB race of the periodic table of elements, group III A and VIA race.
19. electronic devices according to claim 18, wherein, elemental semiconductor or the alloy of the element in described identical race are SiC or SiGe.
20. electronic devices according to claim 18, wherein, described in comprise the IB race of the periodic table of elements, alloy that the compound semiconductor of element of group III A and VIA race is copper, indium, gallium, aluminium, selenium and sulphur.
21. electronic devices according to claim 1, wherein, described substrate has the mean grain size being greater than 100 microns.
22. electronic devices according to claim 1, wherein, at least one resilient coating described has the crystal structure being selected from and comprising following group: the rock salt crystal structure of formula AN or AO, wherein A be metal and N and O corresponding to nitrogen and oxygen; Formula ABO 3perovskite crystal structure, wherein A and B is metal and O is oxygen; Formula A 2b 2o 7pyrochlore crystal structure, wherein A and B is metal and O is oxygen; And formula A 2o 3bixbyite crystal structure, wherein A is metal and O is oxygen.
23. electronic devices according to claim 1, wherein, at least one resilient coating described has the chemical formula being selected from and comprising following group: have formula A xb 1-xo and A xb 1-xthe rock salt crystal structure of the mixing of N, wherein A and B is different metals; There is formula A xb 1-xn yo 1-ythe oxynitride of mixing, wherein A and B is different metals; There is formula (A xb 1-x) 2o 3the bixbyite structure of mixing, wherein A and B is different metals; There is formula (A xa' 1-x) BO 3, (A xa' 1-x) (B yb' 1-y) O 3the perovskite of mixing, wherein A, A', B and B' are different metals; And there is formula (A xa' 1-x) 2b 2o 7, (A xa' 1-x) 2(B yb' 1-y) 2o 7the pyrochlore of mixing, wherein A, A', B and B' are different metals.
24. electronic devices according to claim 1, wherein, at least one resilient coating described is oxide buffer layer, and described oxide buffer layer is selected from and comprises following group: γ-Al 2o 3(Al 2o 3cube form); Perovskite; Adulterated with Ca and Ti ore; Layered perovskites; Pyrochlore; Fluorite; Rock salt oxide and spinelle.
25. electronic devices according to claim 24, wherein, described perovskite is SrTiO 3, (Sr, Nb) TiO 3, BaTiO 3, (Ba, Ca) TiO 3, LaMnO 3or LaAlO 3.
26. electronic devices according to claim 24, wherein, described adulterated with Ca and Ti ore is (La, Sr) MnO 3or (La, Ca) MnO 3.
27. electronic devices according to claim 24, wherein, described layered perovskites is Bi 4ti 3o 12.
28. electronic devices according to claim 24, wherein, described pyrochlore is La 2zr 2o 7, Ca 2zr 2o 7or Gd 2zr 2o 7.
29. electronic devices according to claim 24, wherein, described fluorite is Y 2o 3or YSZ.
30. electronic devices according to claim 24, wherein, described rock salt oxide is MgO.
31. electronic devices according to claim 24, wherein, described spinelle is MgAl 2o 4.
32. electronic devices according to claim 1, wherein, at least one resilient coating described is silicide resilient coating or the intermetallic alloy with germanium, described silicide resilient coating or with the intermetallic alloy of germanium corresponding to having chemical formula MSi or MSi 2, MSi 3, MGe or MGe 2, MGe 3layer, wherein M is metal.
33. electronic devices according to claim 32, wherein, described metal is Ni, Cu, Fe, Ir or Co.
34. electronic devices according to claim 1, wherein, at least one resilient coating described is carbide resilient coating, and described carbide resilient coating is corresponding to cube form of SiC.
35. electronic devices according to claim 1, wherein, at least one resilient coating described is " on composition graduate resilient coating ", comprises the multi-buffer layer with different lattice parameters, to provide good Lattice Matching to the epitaxial loayer of at least one semi-conducting material described.
36. electronic devices according to claim 1, also be included in the semiconductor module flaggy above last resilient coating, to provide good Lattice Matching to the epitaxial loayer of at least one semi-conducting material described, wherein, at least one resilient coating described is " on composition graduate resilient coating ", comprise the multi-buffer layer with different lattice parameters, to provide good Lattice Matching to described semiconductor module flaggy.
37. electronic devices according to claim 1, wherein, at least one resilient coating described is conduction.
38. electronic devices according to claim 1, are also included in the semiconductor module flaggy above last resilient coating, to provide good Lattice Matching to the epitaxial loayer of at least one semi-conducting material described.
39. according to electronic device according to claim 38, wherein, described semiconductor module flaggy is " on composition graduate semiconductor die " layer of the multilayer with different lattice parameters, to provide good Lattice Matching to the epitaxial loayer of at least one semi-conducting material described.
40. electronic devices according to claim 1, wherein, described substrate is selected from the group comprising Cu, Ni, Al, Mo, Nb and Fe and alloy thereof.
41. electronic devices according to claim 1, wherein, at least one resilient coating described is buffer stack.
42. electronic devices according to claim 41, wherein, described buffer stack is selected from the multilayer, the Y that comprise a cube nitride layer, MgO/ cube nitride 2o 3the multilayer of/YSZ/ cube of nitride, Y 2o 3multilayer, the Y of the multilayer of/YSZ/MgO/ cube of nitride, cubic oxide nitride layer, MgO/ cubic oxide thing 2o 3the multilayer of/YSZ/ cubic oxide thing and Y 2o 3the resilient coating structure of the multilayer of/YSZ/MgO/ cubic oxide thing.
43. electronic devices according to claim 42, wherein, described cube of nitride layer is TiN.
44. electronic devices according to claim 42, wherein, described cubic oxide nitride layer is γ-Al 2o 3.
45. electronic devices according to claim 42, wherein, described cube of nitride is graduate nitride layer on composition, provides good Lattice Matching with the epitaxial loayer at least one semi-conducting material described or the semiconductor module flaggy above last resilient coating.
46. electronic devices according to claim 42, wherein, described cubic oxide thing is graduate oxide skin(coating) on composition, provides good Lattice Matching with the epitaxial loayer at least one semi-conducting material described or the semiconductor module flaggy above last resilient coating.
47. electronic devices according to claim 1, wherein, at least one resilient coating described be polycrystalline with crystallography on do not arrange, and be the result of the reaction in device stack between two adjacent layers.
48. electronic devices according to claim 1, wherein, described metal or alloy substrate is MULTILAYER COMPOSITE substrate, and wherein only top layer has the arrangement of crystallography, and all three crystallographic axis of all crystal grains in this top layer relative to each other arrange in all directions in 10 degree.
49. electronic devices according to claim 1, wherein, described metal or alloy substrate is MULTILAYER COMPOSITE substrate, wherein only top layer and bottom have the arrangement of crystallography, and all three crystallographic axis of all crystal grains in described top layer and described bottom relative to each other arrange in all directions in 10 degree.
50. electronic devices according to claim 1, wherein, have the Ni base alloy of the W content of 3-9 atomic percentage comprising at least partially in described substrate.
51. electronic devices according to claim 1, wherein, described electronic device is selected from the group comprising photovoltaic device, flat-panel monitor, thermo-photovoltaic device, ferro-electric device, LED device, computer hard disc driver device, the device based on magnetic resistance, the device based on luminescence generated by light, nonvolatile memory device, dielectric devices, thermoelectric device and quantum dot laser device.
52. electronic devices according to claim 1, wherein, described electronic device comprises at least one and is selected from the device comprising following group: Double-end device; Three termination devices and multiterminal head device.
53. electronic devices according to claim 52, wherein, described Double-end device is diode.
54. electronic devices according to claim 52, wherein, described three termination devices are transistor, thyristor or rectifier.
55. electronic devices according to claim 52, wherein, described multiterminal head device is microprocessor, random access memory, read-only memory or charge coupled device.
56. electronic devices according to claim 1, wherein, described electronic device forms the parts of dull and stereotyped active matrix liquid crystal display (AMLCD) or dull and stereotyped active-matrix Organic Light Emitting Diode (AMOLED) display.
57. electronic devices according to claim 1, wherein, described electronic device is the photovoltaic device comprising the pn knot that at least one is parallel to substrate surface.
58. electronic devices according to claim 57, wherein, described photovoltaic device comprises the multijunction cell having at least two pn being parallel to described substrate surface and tie.
59. electronic devices according to claim 58, wherein, described photovoltaic device comprises the multijunction cell having three pn being parallel to described substrate surface and tie.
60. electronic devices according to claim 57, wherein, the conversion efficiency of described photovoltaic device is greater than 13%.
61. electronic devices according to claim 57, wherein, the conversion efficiency of described photovoltaic device is greater than 15%.
62. electronic devices according to claim 1, wherein, the nano dot of the arrangement that electronic device layer is made up of another crystallization different from described device layer forms, and wherein the diameter of nano dot is in the scope of 2-100 nanometer.
63. electronic devices according to claim 62, wherein, 80% of described nano dot arranges in 60 degree with the normal of described device layer.
CN200880128188.0A 2008-01-28 2008-09-09 [100] or [110] aligned, semiconductor-based, large-area, flexible, electronic devices Expired - Fee Related CN101981685B (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109449223A (en) * 2018-10-26 2019-03-08 超晶科技（北京）有限公司 The laser and detector and preparation method of indium gallium nitrogen bismuth material and the use material

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8961687B2 (en) 2009-08-31 2015-02-24 Alliance For Sustainable Energy, Llc Lattice matched crystalline substrates for cubic nitride semiconductor growth
US8575471B2 (en) 2009-08-31 2013-11-05 Alliance For Sustainable Energy, Llc Lattice matched semiconductor growth on crystalline metallic substrates
US9947829B2 (en) 2010-06-24 2018-04-17 Glo Ab Substrate with buffer layer for oriented nanowire growth
JP5817327B2 (en) 2010-09-29 2015-11-18 東ソー株式会社 Oxide sintered body, method for producing the same, oxide transparent conductive film obtained using the same, and solar cell
WO2012074523A1 (en) 2010-12-01 2012-06-07 Alliance For Sustainable Energy, Llc Methods of producing free-standing semiconductors using sacrificial buffer layers and recyclable substrates
WO2012074524A1 (en) 2010-12-01 2012-06-07 Alliance For Sustainable Energy, Llc Coincident site lattice-matched growth of semiconductors on substrates using compliant buffer layers
TWI602315B (en) * 2013-03-08 2017-10-11 索泰克公司 Photoactive devices having low bandgap active layers configured for improved efficiency and related methods
EP3164889B1 (en) * 2014-07-02 2023-06-07 University of Copenhagen A semiconductor josephson junction comprising a semiconductor nanowire and superconductor layers thereon
US20160247886A1 (en) * 2015-02-19 2016-08-25 Hermes-Epitek Corp. Semiconductor template and manufacturing method thereof
WO2018080033A1 (en) * 2016-10-25 2018-05-03 삼성에스디아이 주식회사 Battery module having fixing structure for temperature sensor
CN109103230B (en) * 2018-08-27 2022-02-08 武汉天马微电子有限公司 OLED display panel, manufacturing method of OLED display panel and display device
CN109285919A (en) * 2018-09-28 2019-01-29 王敏 A kind of preparation method of copper indium gallium selenium solar cell film damper layer material
CN110911510B (en) * 2019-11-20 2021-02-26 电子科技大学中山学院 Silicon-based nitride five-junction solar cell containing superlattice structure
CN112510122B (en) * 2021-02-07 2021-07-06 中山德华芯片技术有限公司 Cutting-free flexible gallium arsenide solar cell and manufacturing method thereof

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5304342A (en) * 1992-06-11 1994-04-19 Hall Jr H Tracy Carbide/metal composite material and a process therefor
US5872080A (en) * 1995-04-19 1999-02-16 The Regents Of The University Of California High temperature superconducting thick films
US5994156A (en) * 1997-09-12 1999-11-30 Sharp Laboratories Of America, Inc. Method of making gate and source lines in TFT LCD panels using pure aluminum metal
KR100352976B1 (en) * 1999-12-24 2002-09-18 한국기계연구원 Electrical Plating Process and Device for Ni Plate Layer Having Biaxial Texture
US6455166B1 (en) * 2000-05-11 2002-09-24 The University Of Chicago Metallic substrates for high temperature superconductors
US6784139B1 (en) * 2000-07-10 2004-08-31 Applied Thin Films, Inc. Conductive and robust nitride buffer layers on biaxially textured substrates
US6617283B2 (en) * 2001-06-22 2003-09-09 Ut-Battelle, Llc Method of depositing an electrically conductive oxide buffer layer on a textured substrate and articles formed therefrom
CN102738259A (en) * 2003-12-01 2012-10-17 加利福尼亚大学董事会 Multiband semiconductor compositions for photovoltaic devices
US6872988B1 (en) * 2004-03-23 2005-03-29 Ut-Battelle, Llc Semiconductor films on flexible iridium substrates
US20060208257A1 (en) * 2005-03-15 2006-09-21 Branz Howard M Method for low-temperature, hetero-epitaxial growth of thin film cSi on amorphous and multi-crystalline substrates and c-Si devices on amorphous, multi-crystalline, and crystalline substrates
WO2007025062A2 (en) * 2005-08-25 2007-03-01 Wakonda Technologies, Inc. Photovoltaic template
US7879161B2 (en) * 2007-08-08 2011-02-01 Ut-Battelle, Llc Strong, non-magnetic, cube textured alloy substrates
CA2742128C (en) * 2008-01-28 2016-11-29 Amit Goyal Semiconductor-based large-area flexible electronic devices

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109449223A (en) * 2018-10-26 2019-03-08 超晶科技（北京）有限公司 The laser and detector and preparation method of indium gallium nitrogen bismuth material and the use material

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