CN116516474B - Structure and method for growing CdTe epitaxial layer on GaAs substrate - Google Patents
Structure and method for growing CdTe epitaxial layer on GaAs substrate Download PDFInfo
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- 229910004613 CdTe Inorganic materials 0.000 title claims abstract description 138
- 229910001218 Gallium arsenide Inorganic materials 0.000 title claims abstract description 130
- 239000000758 substrate Substances 0.000 title claims abstract description 97
- 238000000034 method Methods 0.000 title claims abstract description 17
- 229910004611 CdZnTe Inorganic materials 0.000 claims description 79
- 229910007709 ZnTe Inorganic materials 0.000 claims description 37
- 230000007704 transition Effects 0.000 claims description 10
- 238000004519 manufacturing process Methods 0.000 claims description 2
- 239000000725 suspension Substances 0.000 claims description 2
- 239000000463 material Substances 0.000 abstract description 10
- 239000010410 layer Substances 0.000 description 484
- 230000007547 defect Effects 0.000 description 31
- 239000000203 mixture Substances 0.000 description 12
- 230000009286 beneficial effect Effects 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000008030 elimination Effects 0.000 description 2
- 238000003379 elimination reaction Methods 0.000 description 2
- 125000005842 heteroatom Chemical group 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 230000005251 gamma ray Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 230000007847 structural defect Effects 0.000 description 1
- 229910002058 ternary alloy Inorganic materials 0.000 description 1
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- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
- C30B25/02—Epitaxial-layer growth
- C30B25/18—Epitaxial-layer growth characterised by the substrate
- C30B25/183—Epitaxial-layer growth characterised by the substrate being provided with a buffer layer, e.g. a lattice matching layer
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- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
- C30B29/10—Inorganic compounds or compositions
- C30B29/46—Sulfur-, selenium- or tellurium-containing compounds
- C30B29/48—AIIBVI compounds wherein A is Zn, Cd or Hg, and B is S, Se or Te
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02387—Group 13/15 materials
- H01L21/02395—Arsenides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02494—Structure
- H01L21/02496—Layer structure
- H01L21/02505—Layer structure consisting of more than two layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02551—Group 12/16 materials
- H01L21/02562—Tellurides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
- H01L31/0352—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1828—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof the active layers comprising only AIIBVI compounds, e.g. CdS, ZnS, CdTe
- H01L31/1836—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof the active layers comprising only AIIBVI compounds, e.g. CdS, ZnS, CdTe comprising a growth substrate not being an AIIBVI compound
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
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- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The invention relates to the technical field of solar cell materials, and provides a structure and a method for growing a CdTe epitaxial layer on a GaAs substrate. The invention adopts a step lattice constant gradual change mode to grow at least two buffer layers, and the lattice constant transits from the GaAs substrate to the CdTe epitaxial layer by layer, so that the probability of lattice mismatch of adjacent layers is greatly reduced. The thickness of the buffer layer can be basically controlled within 2 mu m, thereby ensuring that a high-quality CdTe epitaxial layer is obtained on the GaAs substrate.
Description
Technical Field
The invention relates to the technical field of solar cell materials, in particular to a structure and a method for growing a CdTe epitaxial layer on a GaAs substrate.
Background
CdTe is a direct band gap semiconductor with a cubic structure, and the band gap width at room temperature is 1.47eV, so that the CdTe is an ideal solar cell material. Meanwhile, the average atomic number is large, the electron density is large, and the detection sensitivity to high-energy rays and particles is high. Therefore, cdTe can be used for preparing light-emitting devices, multiple solar cells, X-ray and gamma-ray detectors and the like.
The above devices need to be obtained by epitaxial CdTe on a substrate. But the homogenous CdTe substrate is expensive and the process is not mature enough. Mature GaAs substrates are cheaper and simpler to surface treat. But GaAs has a lattice mismatch with CdTe of more than 14%, which makes it difficult to obtain a high quality CdTe epitaxial layer on GaAs, thereby affecting the performance of CdTe devices and even making it possible to grow CdTe epitaxial layers having a different crystal orientation from GaAs. To obtain a high quality CdTe epitaxial layer, common practices include: growing a very thick CdTe homogeneous buffer layer, so that defects are gradually eliminated in the buffer layer; or a ZnTe buffer layer with lattice constant in between is grown between GaAs and CdTe. The two modes can be combined. Although the thinner buffer layer can eliminate most defects, a certain number of penetration defects still exist into the subsequent important epitaxial layers, which can reduce the quality of materials and affect the performance of the device. Whereas if one were to obtain CdTe epitaxial layers with very low defect densities, the overall thickness of the buffer layer would typically be up to several microns. In practical production, this consumes a lot of time and raw materials, and cannot achieve the effect of rapidly eliminating defects in a small thickness. Accordingly, the prior art is subject to further development.
Disclosure of Invention
The invention aims to overcome the technical defects and provide a structure and a method for growing a CdTe epitaxial layer on a GaAs substrate, so as to solve the technical problem that the defect can not be quickly eliminated in a small thickness in the related art.
In order to achieve the technical purpose, the invention adopts the following technical scheme: the structure comprises a GaAs substrate and a CdTe epitaxial layer, wherein a buffer layer is grown on the GaAs substrate, the CdTe epitaxial layer is grown on the buffer layer, the buffer layer is composed of at least two layers, the lattice constants of the at least two layers of buffer layers are located between the lattice constants of the GaAs substrate and the CdTe epitaxial layer, and the layer-by-layer transition of the lattice constants from the GaAs substrate to the CdTe epitaxial layer is realized through the at least two layers of buffer layers.
Further, the buffer layer is three-layer, including GaAs homogeneous buffer layer, heterogeneous buffer layer and component alternate layer, gaAs homogeneous buffer layer, heterogeneous buffer layer and component alternate layer are grown between GaAs substrate and CdTe epitaxial layer in proper order layer by layer, wherein, heterogeneous buffer layer includes at least two-layer, and this at least two-layer heterogeneous buffer layer is at least two kinds in ZnTe layer, znSeTe layer and the CdZnTe layer, and this at least two-layer heterogeneous buffer layer is grown on GaAs homogeneous buffer layer in proper order layer by layer according to lattice constant from GaAs substrate to CdTe epitaxial layer transition, component alternate layer comprises a set of component alternate unit at least, component alternate unit comprises CdTe layer and CdZnTe layer, this CdZnTe layer is grown on the CdTe layer.
Further, the heterogeneous buffer layer consists of a ZnTe layer, a ZnSeTe layer and a CdZnTe layer, and the ZnTe layer, the ZnSeTe layer and the CdZnTe layer sequentially grow between the GaAs substrate and the CdTe epitaxial layer by layer; in the heterogeneous buffer layer, the thickness of the ZnTe layer is 100-300A, the growth thickness of the ZnSeTe layer is 600-3000A, and the growth thickness of the CdZnTe layer is 600-3000A.
Further, the composition alternating units are 1-4 groups, in the composition alternating units, the thickness of the CdTe layer is 2000-3000A, the thickness of the CdZnTe layer is 1000-2000A, and the Zn composition of the CdZnTe layer is 8.5-14%.
Further, the composition alternating units are 20-50 groups, in the composition alternating units, the thickness of the CdTe layer is 30-60A, the thickness of the CdZnTe layer is 10-30A, and the Zn composition of the CdZnTe layer is 8-14%.
Further, the GaAs homogeneous buffer layer has a thickness of 500-2500A.
In addition, the invention also provides a method for growing the CdTe epitaxial layer on the GaAs substrate, at least two buffer layers are grown between the GaAs substrate and the CdTe epitaxial layer, the at least two buffer layers are sequentially grown on the GaAs substrate layer by layer, and the CdTe epitaxial layer is grown on the uppermost buffer layer.
The at least two buffer layers are at least two of a GaAs homogeneous buffer layer, a GaAs heterogeneous buffer layer and a component alternating layer, and the at least two buffer layers are transited layer by layer from the GaAs substrate to the CdTe epitaxial layer according to lattice constants;
the heterogeneous buffer layer comprises at least two layers, wherein the at least two layers of heterogeneous buffer layers are at least two of a ZnTe layer, a ZnSeTe layer and a CdZnTe layer, and the at least two layers of heterogeneous buffer layers sequentially grow layer by layer according to the sequence of transition of lattice constants from a GaAs substrate to a CdTe epitaxial layer;
the component alternating layers are composed of a plurality of groups of component alternating units, each component alternating unit is composed of a CdTe layer and a CdZnTe layer, and the CdZnTe layer grows on the CdTe layer.
The growth temperature of the GaAs homogeneous buffer layer is 580-600 ℃, and the beam current ratio of As/Ga is 15-40;
the growth condition of the ZnTe layer in the heterogeneous buffer layer is that the growth temperature is 310-330 ℃, and the Te/Zn beam ratio is 4-6;
the growth condition of the ZnSeTe layer in the heterogeneous buffer layer is that the Se component is 40-70%, the growth temperature is 340-360 ℃, and the Te/Zn beam ratio is 5-6;
the growth condition of the CdZnTe layer in the heterogeneous buffer layer is that the Zn component is 40-60%, the growth temperature is 340-380 ℃, and the Te/(Cd+Zn) beam ratio is 8-10;
the multiple groups of component alternating units grow layer by layer in sequence, wherein after the growth of each group of component alternating units is finished, the next component alternating unit grows after 2-15s of suspension;
the growth condition of the component alternating units is that the growth temperature is 340-360 ℃, and the beam current ratio of Te/Cd is 10-11.
The buffer layer is three layers, comprising a GaAs homogeneous buffer layer, a heterogeneous buffer layer and a component alternating layer, wherein the GaAs homogeneous buffer layer grows on the GaAs substrate, the heterogeneous buffer layer grows on the GaAs homogeneous buffer layer in a step lattice constant gradual change mode, and finally the component alternating layer grows on the heterogeneous buffer layer;
the heterogeneous buffer layer consists of a ZnTe layer, a ZnSeTe layer and a CdZnTe layer, and the ZnTe layer, the ZnSeTe layer and the CdZnTe layer are sequentially grown on the GaAs substrate layer by layer;
the amount of Zn component in the CdZnTe layer of the component alternating layer is smaller than the amount of Zn component in the CdZnTe layer of the heterogeneous buffer layer.
The beneficial effects are that:
1. the invention adopts a step lattice constant gradual change mode to grow at least two buffer layers, and the lattice constant is transited from the GaAs substrate to the CdTe epitaxial layer by layer, so that the lattice mismatch rate of the adjacent layers is greatly reduced, and meanwhile, the invention utilizes the characteristic property of an interface to promote the defect to be eliminated at a higher speed.
2. In the preferred embodiment of the invention, the GaAs homogeneous buffer layer, the heterogeneous buffer layer and the component alternating layer cooperate to eliminate defects and reduce the thickness of the whole buffer layer, the thickness of the buffer layer can be basically controlled within 2 mu m, and the defect density can be controlled at a very low level to reach 5E8/cm 2 The following ensures that a high quality CdTe epitaxial layer is obtained on GaAs substrates.
3. In the preferred embodiment of the invention, the ZnSeTe layer and the CdZnTe layer are made of two materials with opposite single polarities, so that the buffer layer can not be obviously n-type or p-type, the insulation property is better, and the leakage caused by the buffer layer can be reduced when a device is manufactured on the buffer layer.
Drawings
FIG. 1 is a schematic diagram of the structure of a GaAs substrate of example 1 with a CdTe epitaxial layer grown thereon;
FIG. 2 is a schematic diagram of the structure of a GaAs substrate of example 2 with a CdTe epitaxial layer grown thereon;
wherein the above figures include the following reference numerals:
1. a GaAs substrate; 2. GaAs homogeneous buffer layer; 3. a ZnTe layer; 4. a ZnSeTe layer; 5. a CdZnTe layer of the heterogeneous buffer layer; 6a,6b, alternating layers of components; 7a,7b, cdTe layer; 8a,8b, cdZnTe layers of alternating layers of composition; 9. CdTe epitaxial layer.
Detailed Description
The technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the embodiments of the present invention, and it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
According to the embodiment of the invention, the structure with the CdTe epitaxial layer grown on the GaAs substrate comprises the GaAs substrate and the CdTe epitaxial layer, the GaAs substrate is grown with the buffer layer, the CdTe epitaxial layer is grown on the buffer layer, the buffer layer consists of at least two layers, the lattice constants of the at least two layers of the buffer layer are positioned between the lattice constants of the GaAs substrate and the CdTe epitaxial layer, and the layer-by-layer transition of the lattice constants from the GaAs substrate to the CdTe epitaxial layer is realized through the at least two layers of the buffer layer. The invention is provided with at least two buffer layers, the buffer layers of the at least two buffer layers are equivalent to steps between the GaAs substrate and the CdTe epitaxial layer, and the lattice constant layer-by-layer transition from the GaAs substrate to the CdTe epitaxial layer is realized, so that the lattice mismatch rate between the buffer layers and the GaAs substrate and the CdTe epitaxial layer is changed from more than 14% to less than 5%, and finally, the effect of growing the high-quality CdTe epitaxial layer on the GaAs substrate is achieved.
In the structure of the GaAs substrate with the CdTe epitaxial layer grown thereon in the specific embodiment, the buffer layer may be two layers, specifically at least two layers of GaAs homogeneous buffer layer, heterogeneous buffer layer, and composition alternating layer. When the buffer layer is a GaAs homogeneous buffer layer and a heterogeneous buffer layer, the GaAs homogeneous buffer layer and the heterogeneous buffer layer sequentially grow between the GaAs substrate and the CdTe epitaxial layer by layer; when the buffer layer is a GaAs homogeneous buffer layer and a component alternating layer, the GaAs homogeneous buffer layer and the component alternating layer sequentially grow between the GaAs substrate and the CdTe epitaxial layer by layer; when the buffer layer is a heterogeneous buffer layer and a component alternating layer, the heterogeneous buffer layer and the component alternating layer are sequentially grown between the GaAs substrate and the CdTe epitaxial layer by layer.
Of course, in the structure in which the CdTe epitaxial layer grows on the GaAs substrate in the specific embodiment, the buffer layer may also be three layers, including a GaAs homogeneous buffer layer, a heterogeneous buffer layer, and a component alternating layer, which sequentially grow between the GaAs substrate and the CdTe epitaxial layer by layer. The buffer layer simultaneously comprises a GaAs homogeneous buffer layer, a heterogeneous buffer layer and a component alternating layer, and grows according to a certain sequence.
The transition of lattice constants of at least two buffer layers is completed, defects are eliminated at a faster speed, the growth sequence between the buffer layers is controlled to realize gradual lattice constant gradient, and the defect can not be completely eliminated by only growing a thick CdTe buffer layer in the prior art.
In the structure of the specific embodiment, which is formed by growing the CdTe epitaxial layer on the GaAs substrate, the heterogeneous buffer layer comprises at least two layers, wherein the at least two layers of heterogeneous buffer layers are at least two of a ZnTe layer, a ZnSeTe layer and a CdZnTe layer, and the at least two layers of heterogeneous buffer layers are sequentially grown on the GaAs homogeneous buffer layer by layer according to the sequence of transition of lattice constants from the GaAs substrate to the CdTe epitaxial layer.
In the structure of the specific embodiment, in which the CdTe epitaxial layer grows on the GaAs substrate, when the heterogeneous buffer layer is two layers, the heterogeneous buffer layer can be composed of a ZnTe layer and a ZnSeTe layer, and the ZnTe layer and the ZnSeTe layer sequentially grow between the GaAs substrate and the CdTe epitaxial layer by layer. The heterogeneous buffer layer may be composed of a ZnSeTe layer and a CdZnTe layer grown sequentially layer by layer between the GaAs substrate and the CdTe epitaxial layer. The heterogeneous buffer layer is also composed of a ZnTe layer and a CdZnTe layer which sequentially grow between the GaAs substrate and the CdTe epitaxial layer by layer.
Of course, in the structure of the specific embodiment of the GaAs substrate with the CdTe epitaxial layer grown thereon, when the hetero buffer layer is three layers, the hetero buffer layer is composed of a ZnTe layer, a ZnSeTe layer and a CdZnTe layer, and the ZnTe layer, the ZnSeTe layer and the CdZnTe layer are sequentially grown between the GaAs substrate and the CdTe epitaxial layer by layer.
In the structure of the specific embodiment, which is formed by growing the CdTe epitaxial layer on the GaAs substrate, the heterogeneous buffer layer adopts at least two of a ZnTe layer, a ZnSeTe layer and a CdZnTe layer, and lattice parameters of the ZnTe layer, the ZnSeTe layer and the CdZnTe layer are positioned between the GaAs substrate and the CdTe epitaxial layer, so that the probability of lattice mismatch of the adjacent layers is greatly reduced. The selection of the heterogeneous buffer layer is crucial, the ZnTe layer of the heterogeneous buffer layer is beneficial to improving the crystal quality of an upper material, the ZnSeTe layer and the CdZnTe layer can be converted from initial three-dimensional growth to stable two-dimensional growth, the formation of three-dimensional islands is avoided, and meanwhile, a defect network can be relaxed. After the two layers are grown, most of lattice constant transition can be completed, and defects generated by partial lattice constant difference can be eliminated. The selection of ZnSeTe and CdZnTe materials is also selected by comprehensively considering the specific unipolar characteristics of a (Zn, cd) (Se, te) material system. Each ternary alloy is composed of two materials with opposite single polarities, so that the buffer layer can not be obviously n-type or p-type, the insulation property is better, and the leakage caused by the buffer layer can be reduced when a device is manufactured on the buffer layer.
In the structure of the particular embodiment in which the CdTe epitaxial layer is grown on the GaAs substrate, the alternating component layers are composed of at least one group of alternating component units composed of a CdTe layer and a CdZnTe layer grown on the CdTe layer. The CdTe layer and the CdZnTe layer are also specific according to the CdTe epitaxial layer, each group of component alternating units consists of the CdTe layer and the CdZnTe layer, and the CdTe lattice constant of the component alternating layers is consistent with that of the CdTe epitaxial layer, so that the epitaxial layer with higher quality can be grown on the component alternating layers.
In the structure of the GaAs substrate with the CdTe epitaxial layer grown thereon in the specific embodiment, in the heterogeneous buffer layer, the thickness of the ZnTe layer is 100-300A, the thickness of the ZnTe layer is preferably 150-280A, the growth thickness of the ZnSeTe layer is 600-3000A, the growth thickness of the ZnSeTe layer is preferably 1500-2500A, further, the growth thickness of the ZnSeTe layer is preferably 1800-2200A, the growth thickness of the CdZnTe layer is 600-3000A, the growth thickness of the CdZnTe layer is preferably 1500-2500A, and further, the growth thickness of the CdZnTe layer is 1800-2200A. The thickness of the ZnTe layer is smaller than that of the ZnSeTe layer and the dZnTe layer, because the ZnTe layer grows on the GaAs substrate or the GaAs homogeneous buffer layer, and the defects are fewer; the ZnSeTe layer and the dZnTe layer need to eliminate more defects, so that the defects are gradually eliminated in the buffer layer, and the thickness of the ZnTe layer, the ZnSeTe layer and the CdZnTe layer has an important influence on the growth of the CdTe epitaxial layer on the GaAs substrate. The thickness is set for high quality growth of CdTe epitaxial layers on GaAs substrates.
In the structure of the GaAs substrate with the CdTe epitaxial layer grown thereon in the specific embodiment, for the component alternating layers, the component alternating units are 1-4 groups, in the component alternating units, the thickness of the CdTe layer is 2000-3000A, the thickness of the CdTe layer is preferably 2300-2500A, the thickness of the CdZnTe layer is 1000-2000A, the thickness of the CdZnTe layer is preferably 1500-1700A, and the Zn component of the CdZnTe layer is 8.5-14%. The components of the alternating units are 1-4 groups, the thickness of the CdTe layer is 2000-3000A, the thickness of the CdZnTe layer is 1000-2000A, at the moment, the thickness of the CdTe layer and the thickness of the CdZnTe layer are respectively larger than the critical thickness of the CdTe layer and the CdZnTe layer, the critical thickness is elastic strain when the thicknesses of the CdTe layer and the CdZnTe layer do not exceed a certain critical value, dislocation defects are generated to release stress due to overlarge stress after the thickness exceeds a certain critical value, and the critical value is the critical thickness. For the thickness of the CdTe layer and the thickness of the CdZnTe layer are respectively larger than the critical thickness of the CdTe layer and the CdZnTe layer, if the thickness of each group of component alternating units is insufficient, defects generated at the interface are insufficient to react, a new interface is introduced, and the reduction of the overall defect density is not facilitated. While continuing to increase the monolayer thickness over the optimized thickness may further eliminate the defect, the elimination efficiency has been significantly reduced. At this point, a new interface needs to be introduced to further facilitate the removal of the hard-to-remove defects by turning and movement, interacting with the newly created defects at the interface.
In the structure of the GaAs substrate with the CdTe epitaxial layer grown thereon in the specific embodiment, for the component alternating layers, the component alternating units are 20-50 groups, in the component alternating units, the thickness of the CdTe layer is 30-60A, the thickness of the CdTe layer is preferably 45-55A, the thickness of the CdZnTe layer is 10-30A, the thickness of the CdZnTe layer is preferably 22-28A, and the Zn component of the CdZnTe layer is 8% -14%. The components of the alternating units are 20-50 groups, the thickness of the CdTe layer is 30-60A, the thickness of the CdZnTe layer is 10-30A, the thickness of the CdTe layer and the thickness of the CdZnTe layer are respectively smaller than the critical thickness of the CdTe layer and the CdZnTe layer, the critical thickness is elastic strain when the thicknesses of the CdTe layer and the CdZnTe layer do not exceed a certain critical value, dislocation defects are generated to release stress due to overlarge stress after the thickness exceeds a certain critical value, and the critical value is the critical thickness. For alternating units of components in which both the thickness of the CdTe layer and the thickness of the CdZnTe layer are less than the critical thickness, a large amount of interfacial disturbances can also promote the turning, movement, reaction, and annihilation of defects. However, when the number of groups of alternate layers exceeds a certain number, dislocation elimination efficiency is lowered, and excessive interfaces may also cause uneven surfaces.
The invention also provides a method for growing the CdTe epitaxial layer on the GaAs substrate, which comprises the following steps: at least two buffer layers are grown between the GaAs substrate and the CdTe epitaxial layer, the at least two buffer layers are sequentially grown on the GaAs substrate layer by layer, and the CdTe epitaxial layer is grown on the uppermost buffer layer. The growth method can grow various structures with CdTe epitaxial layers grown on the GaAs substrate. The growth sequence of the buffer layer and the type of the buffer layer are selected, and the buffer layer can serve as a template of the epitaxial layer which is grown subsequently to accommodate defects caused by lattice mismatch between the epitaxial layer and the substrate. When at least two buffer layers are grown between the GaAs substrate and the CdTe epitaxial layer, the at least two buffer layers are at least two of a GaAs homogeneous buffer layer, a GaAs heterogeneous buffer layer and a component alternating layer, and the at least two buffer layers are transited layer by layer from the GaAs substrate to the CdTe epitaxial layer according to lattice constants.
In the method for growing the CdTe epitaxial layer on the GaAs substrate in the specific embodiment, the growth temperature of the GaAs homogeneous buffer layer is 580-600 ℃, the beam current ratio of As/Ga is 15-40, and preferably, the beam current ratio of As/Ga is 25-35. Through regulation and control, the beam current ratio of As/Ga enables the reconstruction of the surface of the GaAs homogeneous buffer layer to be the same As the reconstruction of the surface of the GaAs substrate, and the GaAs homogeneous buffer layer is used for eliminating the defects of the surface of the substrate.
In the method for growing the CdTe epitaxial layer on the GaAs substrate in the specific embodiment, the heterogeneous buffer layer comprises at least two layers, wherein the at least two layers of heterogeneous buffer layers are at least two of a ZnTe layer, a ZnSeTe layer and a CdZnTe layer, and the at least two layers of heterogeneous buffer layers are sequentially grown layer by layer according to the sequence of transition of lattice constants from the GaAs substrate to the CdTe epitaxial layer.
In the method for growing the CdTe epitaxial layer on the GaAs substrate in the specific embodiment, the growth condition of the ZnTe layer in the heterogeneous buffer layer is that the growth temperature is 310-330 ℃, the growth temperature is preferably 315-325 ℃, and the Te/Zn beam ratio is 4-6. The growth temperature of the ZnTe layer is 310-330 ℃, and the ZnTe layer grown at low temperature is beneficial to improving the crystal quality of the upper layer material. The growth condition of ZnSeTe layer in heterogeneous buffer layer is that Se component is 40-70%, growth temperature is 340-360 deg.C, growth temperature is 345-355 deg.C, te/Zn beam ratio is 5-6. The growth condition of the CdZnTe layer in the heterogeneous buffer layer is that the Zn component is 40-60%, the growth temperature is 340-380 ℃, and the Te/(Cd+Zn) beam current ratio is 8-10. For Te/Zn beam ratios, it can be seen that the Te/Zn beam ratio of the ZnTe layer and the Te/Zn beam ratio of the ZnSeTe layer are respectively smaller than the Te/Zn beam ratio of the CdZnTe layer, that is, the usage of Zn components is gradually reduced, and in order to ensure that lattice constants cannot be changed by cliffs, the lower mismatch rate is ensured by gradually reducing Zn content, so that each layer can be successfully obtained by epitaxy, and defects are reduced.
In a particular embodiment of a method of growing a CdTe epitaxial layer on a GaAs substrate, the alternating component layers are comprised of at least one set of alternating component units comprised of a CdTe layer and a CdZnTe layer grown on the CdTe layer.
In the method for growing the CdTe epitaxial layer on the GaAs substrate in the specific embodiment, the Zn component amount in the CdZnTe layer of the component alternating layer is smaller than the Zn component amount in the CdZnTe layer of the heterogeneous buffer layer. In order to prevent the cliff type change of the lattice constant, the lower mismatch rate is ensured through the gradual reduction of Zn content, so that each layer can be obtained smoothly and epitaxially, and defects are reduced.
In the method for growing the CdTe epitaxial layer on the GaAs substrate in the specific embodiment, the sub-alternating layers are composed of a plurality of groups of component alternating units, and the groups of component alternating units grow layer by layer in sequence, wherein after the growth of each group of component alternating units is completed, the next component alternating unit grows after 2-15s of pause. Each group of alternating units is suspended for a period of time after growth is completed in order to planarize the surface. The pause time may be 2-15s, preferably 5-10s.
In the method for growing the CdTe epitaxial layer on the GaAs substrate in the specific embodiment, the growth condition of the component alternating unit is 340-360 ℃, the growth temperature is preferably 350-360 ℃, and the beam current ratio of Te/Cd is 10-11.
Next, specific descriptions will be made by specific examples 1 and 2.
Example 1:
as shown in fig. 1, a structure having a CdTe epitaxial layer grown on a GaAs substrate was prepared in the following manner.
A GaAs homogeneous buffer layer 2 of 1000 a thick is first grown on a GaAs substrate 1. The growth temperature was 580℃and the As/Ga beam ratio was 30.
A ZnTe layer 3 is subsequently grown. The growth thickness was 250 a, the growth temperature was 320 c and the Zn/Te beam ratio was 5.5.
The ZnSeTe layer 4 is grown again. The Se component was 55%. The growth thickness is 2000 a. The growth temperature was 350 ℃. The Te/Zn beam ratio was 5.5 and the Se/Zn beam ratio was 2.6.
Then a CdZnTe layer 5 of the heterogeneous buffer layer is grown. The Zn composition was 55%. The growth thickness is 2000 a. The growth temperature was 340 ℃. Te/(Cd+Zn) beam ratio was 8.5, cd/Zn beam ratio was 1.35.
Finally 2 groups of alternating layers 6a of composition are grown. Wherein the alternating layers 6a of composition comprise: firstly, growing a CdTe layer 7a, wherein the growth thickness of the CdTe layer is 2400A; suspending for 5s after the growth is finished; and continuing to grow the CdZnTe layers 8a with the alternate components, wherein the Zn component is 11%, the growth thickness is 1600 a, and the growth is stopped for 5s after the growth is finished. The growth temperature of the alternate component layers 6a was 350 ℃, the Te/Cd beam ratio was 10.5, and the Cd/Zn beam ratio in the alternate component layers 8a was 13.5.
Finally, the CdTe epitaxial layer 9 is grown under optimized growth conditions. The total thickness of the buffer layer in this structure is only 1.3 μm.
Example 2:
as shown in fig. 2, the structure with the CdTe epitaxial layer grown on the GaAs substrate was prepared in the following manner.
A 1000 a GaAs homogeneous buffer layer 2 is grown on a GaAs substrate 1. The growth temperature was 580℃and the As/Ga beam ratio was 30.
A ZnTe layer 3 is subsequently grown. The growth thickness is 150A, the growth temperature is 320 ℃, and the Zn/Te beam current ratio is 5.5.
The ZnSeTe layer 4 is grown again. The Se component was 55%. The growth thickness is 2000 a. The growth temperature was 350 ℃. The Te/Zn beam ratio was 5.5 and the Se/Zn beam ratio was 2.6.
Then a CdZnTe layer 5 of the heterogeneous buffer layer is grown. The Zn composition was 55%. The growth thickness is 2000 a. The growth temperature was 340 ℃. Te/(Cd+Zn) beam ratio was 8.5, cd/Zn beam ratio was 1.35.
Finally, 30 component alternating layers 6b are grown. Wherein the alternating layers 6b of components comprise: firstly, growing a CdTe layer 7b, wherein the thickness of the CdTe layer is 50A; suspending for 5s after the growth is finished; continuing to grow a CdZnTe layer 8b with a component of 10% and a growth thickness of 25A; pause for 5s after growth is completed. The growth temperature of the alternate component layers 6b was 350 ℃, the Te/Cd beam ratio was 10.5, and the Cd/Zn beam ratio in the alternate component layers 8b was 15.
Finally, the CdTe epitaxial layer 9 is grown under optimized growth conditions. The total thickness of the buffer layer in this structure is only 0.725 μm.
Compared with the prior art, the invention adopts a step-type lattice constant gradual change mode to grow at least two buffer layers, the lattice constant is transited from the GaAs substrate to the CdTe epitaxial layer by layer, the growth sequence of the buffer layers and the types of the buffer layers are reasonably selected, and the buffer layers can be used as a template of the epitaxial layers which are grown subsequently to accommodate defects caused by lattice mismatch between the epitaxial layers and the substrate. The prepared GaAs substrate has little structural defect of growing a CdTe epitaxial layer and low thickness of the whole buffer layer. The thickness of the buffer layer of the invention can be basically controlled within 2 mu m, and the defect density can be controlled at a very low level, which can reach 5E8/cm 2 The following is given.
Furthermore, it should be understood that although the present disclosure describes embodiments, not every embodiment is provided with a separate embodiment, and that this description is provided for clarity only, and that the disclosure is not limited to the embodiments described in detail below, and that the embodiments described in the examples may be combined as appropriate to form other embodiments that will be apparent to those skilled in the art.
Claims (3)
1. The structure of the CdTe epitaxial layer grows on the GaAs substrate, comprising the GaAs substrate and the CdTe epitaxial layer, and is characterized in that a buffer layer grows on the GaAs substrate, the CdTe epitaxial layer grows on the buffer layer, the buffer layer is three layers and comprises a GaAs homogeneous buffer layer, a heterogeneous buffer layer and a component alternating layer, the GaAs homogeneous buffer layer, the heterogeneous buffer layer and the component alternating layer sequentially grow between the GaAs substrate and the CdTe epitaxial layer by layer, the lattice constants of the three buffer layers are positioned between the lattice constants of the GaAs substrate and the CdTe epitaxial layer, and the layer-by-layer transition of the lattice constants from the GaAs substrate to the CdTe epitaxial layer is realized through the three buffer layers;
the heterogeneous buffer layer consists of a ZnTe layer, a ZnSeTe layer and a CdZnTe layer, and the ZnTe layer, the ZnSeTe layer and the CdZnTe layer sequentially grow between the GaAs substrate and the CdTe epitaxial layer by layer; in the heterogeneous buffer layer, the thickness of the ZnTe layer is 100-300A, the growth thickness of the ZnSeTe layer is 600-3000A, and the growth thickness of the CdZnTe layer is 600-3000A;
the component alternating layers consist of 1-4 groups or 20-50 groups of component alternating units, the component alternating units consist of CdTe layers and CdZnTe layers, and the CdZnTe layers grow on the CdTe layers;
when the component alternating units are 1-4 groups, the thickness of the CdTe layer is 2000-3000A, the thickness of the CdZnTe layer is 1000-2000A, and the Zn component of the CdZnTe layer is 8.5-14%;
and when the component alternating units are 20-50 groups, the thickness of the CdTe layer is 30-60A, the thickness of the CdZnTe layer is 10-30A, and the Zn component of the CdZnTe layer is 8-14%.
2. The structure of claim 1 wherein the GaAs homogeneous buffer layer has a thickness of 500-2500 a.
3. The method for manufacturing a structure with a CdTe epitaxial layer grown on a GaAs substrate according to claim 1 or 2, characterized in that a three-layer buffer layer is grown between the GaAs substrate and the CdTe epitaxial layer, the three buffer layers are sequentially grown on the GaAs substrate layer by layer, and the CdTe epitaxial layer is grown on the uppermost buffer layer; the three-layer buffer layer comprises a GaAs homogeneous buffer layer, a heterogeneous buffer layer and a component alternating layer, the GaAs homogeneous buffer layer grows on the GaAs substrate, the heterogeneous buffer layer grows on the GaAs homogeneous buffer layer in a step lattice constant gradual change mode, and finally the component alternating layer grows on the heterogeneous buffer layer;
the heterogeneous buffer layer consists of a ZnTe layer, a ZnSeTe layer and a CdZnTe layer, and the ZnTe layer, the ZnSeTe layer and the CdZnTe layer are sequentially grown on the GaAs substrate layer by layer;
the Zn component amount in the CdZnTe layers of the component alternating layers is smaller than that in the CdZnTe layers of the heterogeneous buffer layers;
the component alternating layers are composed of a plurality of groups of component alternating units, the component alternating units are composed of CdTe layers and CdZnTe layers, and the CdZnTe layers grow on the CdTe layers; the growth temperature of the GaAs homogeneous buffer layer is 580-600 ℃, and the beam current ratio of As/Ga is 15-40;
the growth condition of the ZnTe layer in the heterogeneous buffer layer is that the growth temperature is 310-330 ℃, and the Te/Zn beam ratio is 4-6;
the growth condition of the ZnSeTe layer in the heterogeneous buffer layer is that the Se component is 40-70%, the growth temperature is 340-360 ℃, and the Te/Zn beam ratio is 5-6;
the growth condition of the CdZnTe layer in the heterogeneous buffer layer is that the Zn component is 40-60%, the growth temperature is 340-380 ℃, and the Te/(Cd+Zn) beam ratio is 8-10;
the multiple groups of component alternating units grow layer by layer in sequence, wherein after the growth of each group of component alternating units is finished, the next component alternating unit grows after 2-15s of suspension;
the growth condition of the component alternating units is that the growth temperature is 340-360 ℃, and the beam current ratio of Te/Cd is 10-11.
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02181937A (en) * | 1989-01-07 | 1990-07-16 | Fujitsu Ltd | Manufacture of compound semiconductor crystal |
| JPH04276632A (en) * | 1991-03-05 | 1992-10-01 | Fujitsu Ltd | Substrate for semiconductor epitaxial growth use |
| US5454902A (en) * | 1991-11-12 | 1995-10-03 | Hughes Aircraft Company | Production of clean, well-ordered CdTe surfaces using laser ablation |
| CN101981699A (en) * | 2008-01-28 | 2011-02-23 | 阿米特·戈亚尔 | Semiconductor-based large-area flexible electronic devices |
| CN107429423A (en) * | 2015-03-20 | 2017-12-01 | 弗赖贝格化合物原料有限公司 | The growth of A B crystal without lattice curvature |
| CN110914712A (en) * | 2017-07-26 | 2020-03-24 | 深圳帧观德芯科技有限公司 | Radiation detector with built-in depolarizing means |
| CN113097054A (en) * | 2021-04-01 | 2021-07-09 | 上海科技大学 | Semiconductor material and preparation method and application thereof |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9722113B2 (en) * | 2014-07-23 | 2017-08-01 | The Regents Of The University Of Michigan | Tetradymite layer assisted heteroepitaxial growth and applications |
-
2023
- 2023-06-25 CN CN202310744353.1A patent/CN116516474B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02181937A (en) * | 1989-01-07 | 1990-07-16 | Fujitsu Ltd | Manufacture of compound semiconductor crystal |
| JPH04276632A (en) * | 1991-03-05 | 1992-10-01 | Fujitsu Ltd | Substrate for semiconductor epitaxial growth use |
| US5454902A (en) * | 1991-11-12 | 1995-10-03 | Hughes Aircraft Company | Production of clean, well-ordered CdTe surfaces using laser ablation |
| CN101981699A (en) * | 2008-01-28 | 2011-02-23 | 阿米特·戈亚尔 | Semiconductor-based large-area flexible electronic devices |
| CN107429423A (en) * | 2015-03-20 | 2017-12-01 | 弗赖贝格化合物原料有限公司 | The growth of A B crystal without lattice curvature |
| CN110914712A (en) * | 2017-07-26 | 2020-03-24 | 深圳帧观德芯科技有限公司 | Radiation detector with built-in depolarizing means |
| CN113097054A (en) * | 2021-04-01 | 2021-07-09 | 上海科技大学 | Semiconductor material and preparation method and application thereof |
Non-Patent Citations (3)
| Title |
|---|
| GaAs（001）衬底上经双缓冲层生长的Hg1-xCdxTe-HgTe超晶格结构;刘义族;天津师范大学学报（自然科学版）;第21卷(第3期);4-7 * |
| Recent Progress in MBE Growth of CdTe and HgCdTe on (211)B GaAs Substrates;M. CARMODY;Journal of ELECTRONIC MATERIALS;第41卷(第10期);2719-2724 * |
| 在Si和GaAs衬底上分子束外延CdTe的晶格应变;王元樟;人工晶体学报;第34卷(第4期);729-733 * |
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