CN101958398B - 热保护相变随机存取存储器及其制造方法 - Google Patents
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Abstract
在此描述一种存储单元,其包括导电性接触部和包含覆盖在导电性接触部上的可程序化电阻存储器材料的存储器元件。绝缘元件从导电性接触部延伸至到存储器元件内,绝缘元件有近端、远程和用以定义内部的内表面。近端邻近导电性接触部。底电极与导电性接触部接触并且从近端于内部中向上延伸。存储器元件是位于内部,从远程向下延伸,以在第一接触表面与底电极的上表面接触。顶端电极由存储器元件而与绝缘元件的远程分开,并且与存储器元件接触于第二接触表面,第二接触表面的表面积大于第一接触表面的表面积。
Description
技术领域
本发明是关于基于相变存储器材料的存储器装置以及其制造方法,相变存储器材料包括硫属化合物类材料,或者是其它可程序化电阻材料。
背景技术
相变(phase change)类存储器材料,如硫属化合物类材料及其类似材料,可由以适合集成电路实施的准位,施加电流,导致非结晶态与结晶态之间的相态改变。一般非结晶状态的特征是具有比一般结晶状态更高的电阻率,其可以容易地被感测到而指示资料。在使用可程序化电阻材料来形成非挥发性存储器电路(可随机地读取与写入)上,这些特性令人产生兴趣。
从非结晶到结晶状态的改变,在此一般为一较低电流操作,其中电流会加热相变材料,使之达到转态温度以上,以造成主动区从非结晶到结晶相的转态。在此所称的从结晶到非结晶的改变,一般为一较高电流操作,其包括一短且高电流密度脉冲,以融化或破坏结晶结构,之后相变材料很快地冷却,抑制相变过程且让至少一部分相变材料的主动区稳定于非结晶相。技术是要让主动区变小,使得诱发相变所需的电流量得以降低。
由减少相变材料元件的大小及/或与相变材料元件接触的电极的大小,可以降低所需的电流大小,使得能以小的绝对电流值,达到主动区中的较高的电流密度。
控制主动区大小的一个方式是,设计非常小的电极,用以将电流传送到相变材料的本体。此小电极结构是在接触的位置将电流集中在像磨菇头的小区域中。参考美国专利号No.6,429,064,公告于2002年8月6日,授予Wicker的“侧壁导体的缩减接触面积(Reduced Contact Areas ofSidewall Conductor)”;美国专利号No.6,462,353,公告于2002年10月8日,授予Gilgen的“制造电极间接触的小面积的方法(Method forfabricating a Small Area of Contact Between Electrodes)”;美国专利号No.6,501,111,公告于2002年12月31日,授予Lowery的“三维可程序化装置(Three-Dimensional(3D)Programmable Device)”;美国专利号No.6,563,156,公告于2003年1月1日,授予Harshfield的“存储器元件及其制造方法(Memory Elements and Methods for MakingSame)”。
控制主动区大小的另一种方式包括将电极隔开,使得流过其间的电流得以被集中在相变材料的薄层的厚度。参考美国专利申请公开号No.2007/0048945,Czubatyj等人提出的“存储器装置及其制造方法(MemoryDevice and Method of Making Same)”。另,参考下面本申请案的共同申请人的的申请和专利,美国专利申请号No.11/864,273,2007年9月28日提出申请,Lung所提出的“具有侧电极接触的存储器胞(Memory CellHaving A Side Electrode Contact)”;美国专利号No.7,463,512,2008年12月9日公告,Lung所提出的“具有缩减电流相变元件的存储器元件(Memory Element with Reduced-Current Phase Change Element)”;美国专利申请号No.12/023,978,2008年8月7日申请,Lung所提出的“具有共平面电极表面的存储单元装置及其方法(Memory Cell Device withCoplanar Electrode Surface and Method)”。
由已知相变存储单元结构引起的特定议题是与相变材料接触的电极的散热(heat sink)效应。因为相态改变是因为加热而发生的结果,电极的热导率会将热带离主动区,造成需要较高的电流来诱发相变。
较高的电流准位会造成对存储单元的电性和机械可靠度的问题。这些问题包括在相变材料/电极界面的孔洞的形成,此乃因为在操作期间热膨胀与材料密度改变所造成机械应力。
此外,较高的电流准位会导致像局部受热的问题,此足以引起电极和相变材料的扩散/反应,且/或造成主动区内相变材料的组成改变,这导致电阻性切换效能衰减以及存储单元的故障可能。
因此,不同技术被运用来尝试将主动区进行热隔离,使得诱发相变所需的电阻性加热被局限在主主动区。
改进热隔离的一个方式包括使用邻近于相变材料的空隙或孔洞。参考美国专利号No.6,815,704,公告于2004年11月9日,Chen所提出的“运用热绝缘孔洞的相变存储器装置(Phase Change Memory Device EmployingThermally Insulating Voids)”。
也有人提出使用热绝缘材料,以改进对主动区的加热束缚。例如,参考美国专利申请号No.11/940,164,2007年11月14日申请,Chen提出的“包括热保护底电极的相变存储单元及其制造方法(Phase ChangeMemory Cell Including Thermal Protect Bottom Electrode andManufacturing Method)”。
改进热隔离的另一方式是包括以将主动区与电极隔开的方式来形成相变材料和电极。参考下面本申请案的受让人所共有的申请案,美国专利申请案No.11/348,848,2006年9月7日申请,Chen等人提出的“I型相变存储单元(I-Shaped Memory Cell)”;美国专利申请案No.11/952,646,2007年12月7日申请,Lung提出的“具基本上相同热阻抗的界面结构的相变存储单元及其制造方法(Phase Change Memory CellHaving Interface Structures with Essentially Equal thermalImpedances and Manufacturing Methods)”;美国专利申请案No.12/026,342,2005年2月5日申请,Chen提出的“加热中心PC存储器结构和制造方法(Heating Center PCRAM Structure and Method forMaking)”。
因此,有机会来设计相变存储单元结构,其需要一小量电流来诱发主动区中的相变。此外,也需要提供制造此装置的方法。
发明内容
在此描述具有操作电流的相变存储单元。此处描述的存储单元降低从存储器元件的主动区抽离的热量,有效地增加主动区内每单位电流值所产生的热量,并且降低诱发相变所需的电流量。
在此描述一种存储单元,其包括导电性接触部和包含覆盖在导电性接触部上的可程序化电阻存储器材料的存储器元件。绝缘元件从导电性接触部延伸至到存储器元件内,绝缘元件有近端、远程和用以定义内部的内表面。近端邻近导电性接触部。底电极与导电性接触部接触并且从近端于内部中向上延伸。存储器元件是位于内部,自远程向下延伸,以在第一接触表面与底电极的上表面接触。顶端电极由存储器元件而与绝缘元件的远程分开,并且与存储器元件接触于第二接触表面,第二接触表面的表面积大于第一接触表面的表面积。
主动区是在内部的存储器元件的区域,其中存储器材料在至少两个固相之间被诱发改变。如可知悉,主动区可以被制成极小,因而降低诱发相变所需的电流大小。内部的宽度低于存储器元件和底电极的宽度,内部的宽度较佳是小于工艺的最小特征尺寸,典型而言该工艺为光刻工艺,其用来形成存储单元。宽度的不同将电流集中在位于内部的上部中的存储器元件部分,由此降低在主动区诱发相变所需的电流大小。
此外,在一些特定实施例中,因为高电阻率,底电极可以做为加热器,相较于其它原因产生的,对于一给定的电流,在主动区引起较大的温度改变,因此改进主动区中相变的效率。
再者,底电极的小宽度提供经过底电极的高热阻路径,因此限制热量经底电极而从存储器元件的主动区流失。
因为绝缘元件延伸至存储器元件内并且在一些实施例中具有位在底电极的上表面下的下表面,主动区是位在存储器元件的存储器材料的空间内。存储器元件的剩下部分可以因而对主动区提供热隔离,降低诱发相变所需的电流量。此外,使主动区位于内部的上部分并且因而与存储器元件的外表面分离,防止对于主动区的蚀刻损害问题。
绝缘元件也可以对主动区提供一些热隔离。此外,可以使用薄膜沉积技术,将绝缘元件形成在侧壁上,故而该元件的厚度可以非常小。小的厚度增加侧壁绝缘元件的热阻,其由侧壁绝缘元件限制热流流出主动区,并且由此有助于将热流集中于存储器元件材料内。
附图说明
本发明的其它观点和优点可以参考所附附图、详细说明以及申请专利范围,其中:
图1绘示已知技术的“磨菇状”存储单元的剖面图。
图2绘示已知技术的“柱状”存储单元的剖面图。
图3A、图3B分别绘示此处描述的存储单元的实施例的剖面图和上视图。
图4到9绘示适于制造图3A-图3B的存储单元的工艺步骤。
图10是集成电路的简图,其可实施此处描述的存储单元。
图11是图10的集成电路的存储器阵列的部分实施例的示意图。
具体实施方式
参考图1至11详细说明本发明的实施例。
图1绘示一种已知技术的“磨菇状(mushroom-type)”存储单元100的横剖面图,其具有底电极120,经由介电层110而延伸;相变存储器元件130,包含底电极120上的一相变材料层;以及顶电极140,于相变存储器元件130。介电层160环绕相变存储器元件130。如可从图1看出,底电极120的宽度125小于顶电极140和相变存储器元件130的宽度145。
操作时,顶和底电极140、120上的电压会诱发一电流,从顶电极140,经相变存储器元件130,流至底电极120,或循反方向。
主动区150是指相变存储器元件130的区域,其至少在两个固态相之间被诱发而改变。由于不同宽度125和145,从底电极120到顶电极140的电流路径180会被集中在与底电极120相邻的相变存储器元件130的区域,这造成主动区150具有如图1所示的“磨菇状”。
故有必要将底电极120的宽度125缩小,以达成具有经存储器元件130的小的绝对电流值的较高电流密度。然而,企图减少底电极120的宽度125会造成底电极120和存储器元件130间的接口128的电性和机械可靠度的问题,这是因为彼此之间接触面积小。
操作时,由于宽度125、145的不同,电流集中于底电极120和相变存储器元件130之间的接触表面128。此外,如路径180的箭头所指示,电流从接触表面128侧向扩散并且在相变存储器元件130中垂直扩散。结果,在侧向与垂直方向上,相变存储器元件130中的电流密度随着远离接触表面128的距离而减少。电流在相变存储器元件130中扩散所导致的电流密度减少,造成需要更高的电流,以在主动区中诱发出所要的相变。
电流密度以及在主动区150的中心152产生的热远大于位在主动区150的边缘154的密度与热。结果,当主动区150的边缘154被加热至足够的温度以诱发出所需的相变,中心152可以感受局部受热,其足以造成对于存储单元100的电性和机械可靠度的问题。
这些问题可包含在相变存储器元件130和底电极120间的接口128的孔洞形成,其肇始于操作期间热膨胀与材料密度改变所造成的机械应力。此外,中心152会受到局部受热,其足以诱发底电极120材料和相变材料130的扩散/反应,以及/或可以导致在中心154处相变材料130中的组成改变。这些问题会造成电阻性切换效能恶化以及存储单元100的故障可能性。
此外,因为主动区150中相变的发生为受热的结果,底电极120和介电110的热传导率会将热从主动区150抽离,并且导致大量的热损失。高的热损失造成需要更高的电流,以在主动区150中诱发所需的改变。
图2绘示一种已知“柱状”存储单元200的剖面图。存储单元200包括介电层210中的底电极220、底电极220上的相变材料柱230以及相变材料柱230上的顶电极240。介电层260环绕相变材料柱230。如可从图式看出,顶和底电极240、220具有和相变材料柱230相同的宽度275。因此,主动区250可以和顶与底电极240、220隔开,而减少顶和底电极240、220所造成的散热(heat sink)效应。然而,由于主动区250邻近介电层260,会有相变材料230的侧壁到介电层260的热损失。
相变材料柱230的宽度275期望缩小,以达成具有经相变材料的小的绝对电流值的较高的电流密度。存储器材料柱230和顶电极240的形成可以由沉积相变材料层和顶电极材料层,然后再蚀刻。然而,因为底切蚀刻及/或过度蚀刻,制造具有小宽度275与过大(aggressive)高宽比的元件已经有产生问题。这会造成对存储器材料柱230的侧壁232的蚀刻损害,也会引起存储器材料柱230和底电极220之间的对准容忍度问题。
图3A绘示存储单元300的实施例的剖面图,在此所述具有小操作电流并且和处理上述各种问题。
存储单元300包括导电性接触部305,以及覆盖在导电性接触部305上的可程序化电阻性存储器元件330。导电性接触305耦接存储单元300至底下的如晶体管或二极管的存取电路(未绘示)。导电性接触部305包含耐热金属,例如实施例所示的钨。其它可使用的金属包含Ti、Mo、Al、Ta、Cu、Pt、Ir、La、Ni和Ru。其它接触结构和材料可以被使用做为阱。举例来说,导电性接触部305可以是硅,或可包含掺杂半导体材料,其为一存取晶体管或二极管的漏极或源极区。
存储器元件330包括可程序化电阻性存储器材料,并且可包含如选自于Zn、To、Tl、Ge、Sb、Te、Se、In、Ti、Ga、Bi、Sn、Cu、Pd、Pb、Ag、S、Si、O、P、As、N和Au所构成群组之一或多个材料。
存储单元300也包含一个管状绝缘元件350,其自导电性接触部305延伸到存储器元件330。绝缘元件350有一近端256和远程351,近端256邻近导电性接触部305。绝缘元件350也有一用以界定出内部360的内表面354。绝缘元件350包含介电材料,而在例示实施例中包含Al2O3。另外,绝缘元件350也可包含其它像SiO2或SiN的介电材料。
底电极320接触导电性接触部305,并且从近端356在内部360的下部分362向上延伸。绝缘元件350的内表面354延伸超过底电极320的上表面324,以定义内部360的上部分364。在例示实施例中,上与上部分364、362有大致相同的宽度366。在此处使用,“大致上”是倾向提供在形成绝缘元件350期间的工艺容忍度。
底电极320有一外表面322,其绝缘元件350的内表面354所围绕。底电极320可包含如TiN或TaN。在存储器元件包含GST(底下会讨论)的实施例中,TiN较佳,因为它可与GST有较好的接触,GST是半导体制造中所使用的一般材料,且在较高温度下提供一个好的扩散阻障,在此典型的GST转换是在600-700℃的范围。另外,底电极320可能是W、WN、TiAlN或TaAlN,或者包含一或多个元素选自于如由掺杂Si、Si、Ge、C、Ge、Cr、Ti、W、Mo、Al、Ta、Cu、Pt、Ir、La、Ni、N、O、Ru及其组合所构成群组的元素。
如图3B上视图所示,在例示实施例中底电极320和绝缘元件320和绝缘元件350每个均有圆形剖面。然而,在实施例底电极320和绝缘元件350可以分别有截面圆形、椭圆、方形、矩形或稍微不规则形的剖面,端视形成形成底电极320和绝缘元件350所用的工艺技术而定。
回到图3A的剖面图,存储器元件330包含在内部360的上部分364内的一部分,其自远程351向下延伸,以在第一接触表面333与底电极320的上表面324接触。
存储器元件330也延伸到绝缘元件350上表面下方,以连接绝缘元件的外表面352,并且具有一下表面331,其位在底电极320的上表面324下方。因此,存储器元件330环绕绝缘元件和底电极320的一部分。
存储器元件330是在介电层310上。例如,介电层310可包括SiO2。另外,介电层310可包括其它材料。
存储单元300也包含顶电极340,其由存储器元件330的存储器材,与绝缘元件350的远程351分开。顶电极340与存储器元件330在第二接触表面342彼此接触。第二接触表面342的表面积大于第一接触表面333的表面积。
例如,顶电极340可包括上面讨论到关于底电极320的各种材料。在一些实施例中,顶电极340可包括一层以上。举例来说,顶电极340可包括第一材料,其与存储器元件330接触,并且选择与存储器元件330材料相同的材料;以及第二材料,在第一材料上,并选择如低阻性等其它优点的材料。在一些实施例中,顶电极340可包括位线的一部分。顶电极340和存储器元件330被介电层370所围绕,该介电层370包括如SiO2。另外,介电层370可包括其它材料。
在操作时,顶电极340和底电极320上的电压会诱发一电流,该电流沿着自顶电极340、流经存储器元件330并经过接触表面333、342而到底电极320的路径或反方向流动。
主动区是在内部360的上部分364中存储器元件330的一部分,在此存储器材料会在至少两个固态相之间被诱发改变。如所知悉,在绘示的结构中,主动区可以被形成相当小,以减低引发相变所需的电流大小。内部360的宽度366小于存储器元件330和顶电极340的宽度332,而对于用来形成存储单元300的一般光刻蚀刻工艺,宽度366较佳是小于该工艺的最小特征尺寸。宽度332和366之间的差异,将限制在内部360的上部分364存储器储器元件330的一部分中的电流,由此减少在主动区引发相变所需的电流大小。
此外,在某些实施例中,因为底电极320的高电阻性,底电极320可当做一个加热器,相较于其它原因产生的,对于一给定的电流,可在主动区引起较大的温度改变,由此改善主动区中的相变效率。
再者,底电极320的小宽度366提供经过底电极320的高热阻抗路径,因此限制了经由底电极320从存储器元件330的主动区流出的热流量。
因为存储器元件330围绕绝缘元件350的外表面352且向下延伸到底电极320的上表面324,主动区是在存储器元件330的存储器材料的区域内。存储器元件330的剩下部分可因此提供对主动区的热隔离,其减少引发相变所需的电流量。在实施例中,存储器元件330的存储器材料可以具有最高热导率状态的热导率(k),此热导率小于介电材料310、350和370的热导率。因此,由让主动区在存储器材料内,在实施例中,比起介电材料所提供的,存储器元件330可以提供给主动区更大热隔离,因此降低诱发相变所需要的电流量。
此外,使主动区在内部360的上部分364内并且因此与存储器元件330的外表面分离,防止对主动区的蚀刻损伤的问题。
绝缘元件350也可以对主动区提供一些热隔离。此外,在实施例中,可以使用薄膜沉积技术,将绝缘元件350形成于侧壁上,也因此绝缘元件350的厚度352可以非常小。小的厚度352增加绝缘元件350的热阻,其限制热由绝缘元件350流出主动区,并且由此有助于将热集中流到存储器元件330的材料内。
图4到图9绘示适于制造图3A-图3B的存储单元300的制造程序的步骤。
图4说明形成介电层310于导电性接触部305的第一步,其形成牺牲材料层400于介电层300上,并且在材料层400和介电层310中形成介层窗410,介层窗410具有侧壁表面414。材料层400包括的材料是可相对于介电层310的材料和后续形成的侧壁绝缘元件350而被选择性处理(例如选择性蚀刻)的。材料层400可包括如SiO2,而介电层和后续形成的侧壁绝缘元件350每一个均可以包括SiN。
可形成具有次光刻蚀刻宽度(sublithographic width)412的介层窗410,例如,由在该层400上形成隔离层,并且在该隔离层上形成牺牲层。接着,具有接近于或等于工艺(用于产生掩膜)的最小特征尺寸的开口的掩膜形成在牺牲层上,开口重叠于介层窗410上。隔离层和牺牲层接着使用掩膜进行选择性蚀刻,由此在隔离层和牺牲层形成介层窗,并且暴露层400的上表面。移除掩膜后,对介层窗进行选择性底切蚀刻,使得隔离层被蚀刻,而牺牲层和层400保留完整。填入材料接着形成在介层窗内,其因为选择性底切蚀刻工艺导致在形成于介层窗内的填入材料中的自我对准孔洞。接下来,对填入材料进行非等向性蚀刻工艺以打开介层窗孔,且持续蚀刻直到层400被暴露于介层窗下的区域,由此形成侧壁间隙壁,此侧壁间隙壁包含介层窗内的填入材料。侧壁间隙壁具有一开口维度(dimension),此维度大致上由孔洞的维度决定,并因而可以小于光刻工艺的最小特征尺寸。接下来,使用侧壁间隙壁做为蚀刻掩膜,对层400和介电层310进行蚀刻,由此形成介层窗410,其宽度412小于最小光刻工艺尺寸。隔离层和牺牲层可以由如化学机械研磨法(CMP)的平坦化工艺来移除。
接着,绝缘材料的层500形成于图4所示的结构上,也包含于在介层窗410内,这产生图5的剖面图所示的结构。如可从图4看出,层400和介层窗410是共形,而且是在侧壁414上。层500可以由例如化学气相沉积(CVD)或原子层沉积(ALD)来形成。
接着,图5的结构的绝缘材料的层500被非等向蚀刻,以在介层窗410的侧壁414上形成绝缘元件350,这产生图6的剖面图所绘示的结构。绝缘元件350有一内表面354,用以定义一内部360。
接下来,底电极320形成在图6所示的结构的绝缘元件350的内部360内,这产生图7的剖面图所示的结构。底电极320的形成,例如可以在图6所示的结构上沉积一层底电极材料,借着利用如化学机械抛光(CMP)等的平坦化工艺,以暴露出材料曾400的上表面。
接下来,底电极320的一部分由图7所示的结构开始蚀刻,如图8剖面图所示,形成具有上表面324的底电极320,此上表面324低于绝缘元件350的上表面351。底电极320一部分的蚀刻造成内部360的上面部分364自行对准于下面部分362中底电极320的剩余部分。因此,后续形成于内部中的存储器材料便自行对准于底电极320。
接下来,材料层400从图8所示的结构起被选择性地蚀刻,以暴露绝缘元件350的外表面352,并且底电极320的上表面被清理,形成图9剖面图所示的结构。在例示的实施例中,材料层400是SiO2,绝缘元件350和层310为SiN,选择性蚀刻是使用如HF等来进行。
接下来,相变材料沉积在图9所示的结构上,顶电极材料沉积在相变材料上,并将相变材料和顶电极材料图案化以分别形成存储器元件330和顶电极340,产生图3A-图3B的存储单元300。
图10是集成电路1000的简化方块图,其包括具有多数个存储单元的存储器阵列1005,此处描述的存储单元具有小操作电流,存储单元包括相变存储器元件,可以程序化到多种电阻状态,此电阻状态包括低电阻状态和高电阻状态。具有读取、重置、重置验证、设定验证和设定模式的字符线解码器1010耦接到多条字符线1015,并且与所述字符线1015电性通讯,其中所述字符线1015是沿着存储器组11005的列而排列。位线(行)解码器1020与多条位线进行电性通讯,而所述位线1025沿着阵列1005的行而排列,用以对阵列1005中的存储单元禁行读取和程序化。
地址提供到总线,再到字符线解码器和驱动器1010以及位解码器1020。方块1030中的感测电路(感测放大器)和资料输入结构于区块1030,包括用于读取和程序化模式的电压及/或电流源,并经由数据总线1035耦接到位线解码器。资料是从集成电路1000的输入/输出端口并且经由资料输入线1040而提供,或者是从集成电路1000的内部或外部的其它资料源提供到方块1030的资料输入结构。其它电路1065也可以包括在集成电路1000中,例如一般用途处理器或特殊目的应用电路,或者是提供阵列1005所支持的***芯片功能的模块的组合。资料经由资料输出线1045,从方块1030中的感测放大器,提供到集成电路1000的输入/输出埠,或者是集成电路1000的内部或外部的其它资料目的地。
集成电路1000包括控制器1050,用于阵列1005的存储单元的读取、重置、重置验证、设定验证和设定模式。控制器1050在此例中使用偏压配置状态机器来实现,并且控制偏压电路电压与电流源1055的施加,这些是用来对字符线1015、位线1025和某些实施例中的源极线施加包括读取、设定与重置的偏压配置。控制器1050可以使用本领域所的的特殊目的逻辑电路来实现。在其它实施例中,控制器1050包括一般用途处理器,其可在相同的集成电路中实施,以执行计算机程序,来控制元件的操作。在另外其它实施例中,可以利用特殊目的逻辑电路与一般用途处理器的组合,来实施制器1050。
如图11所示,阵列1005的每个存储单元包括存取晶体管(或其它存取元件,如二极管)以及相变存储器件。图11绘示四个存储单元1130、1132、1134、1136,各自具有存储器件11140、1142、1144、1146,其代表可包括数百万存储单元的阵列的一小部分。存储器件可被程序化到多数个电阻状态,此电阻状态包括低和高电阻状态。
存储单元1130、1132、1134、1136的各个存取晶体管的源极共同地连接到源极线1154,此源极线终止于源极线终端电路1155,例如接地端。在其它实施例中,存取元件的源极线并没有电性连接,但可独立控制。源极线终端电路1155包括偏压电路,例如在一些实施例中像用以施加接地以外的偏压配置给源极线1154的电压源与电流源、以及译码电路。
包含字符线1156、1158的多条字符线在第一方向上平行延伸。字符线1156、1158与字符线解码器1010电性通讯。存储单元1130、1134的存取晶体管的栅极连接到字符线1156,而存储单元1132、1136的存取晶体管的栅极共同地连接到字符线1158。
包括位线1160、1162的多条位线在第二方向上平行延伸,并且与位线解码器1020于电性通讯。在例示实施例中,每个存储器件被排列在对应存取元件的漏极与对应位线之间。另外,存储器件也可位于对应存取元件的源极侧。
可理解的是存储器组11005不局限在图11所绘示的阵列结构,也可以使用其它的阵列结构。此外,除了MOS晶体管,在某些实施例中双载子晶体管或二极管可以当作存取元件。
在操作中,阵列1005中的每个存储单元储存与对应季存储元件的电阻有关的资料。例如,资料值的决定可以由感测电路1030的感测放大器,对被选择的存储单元的位线上的电流以及一合适的参考电流进行比较。参考电流可以建立成电流的一预定范围是对应到逻辑“0”,而电流的一相异范围是对应到逻辑“1”。在具有三或更多状态的存储单元中,参考电流可以建立成位线电流的不同范围对应到该三或更多状态的每一个状态。
读取或写入一阵列1005的存储单元可由施加一合适的电压给字符线1156、1158其中之一并且将位线1160、1162其中之一耦接到一电压来达成,使得电流流过选择的存储单元。例如,经一选择的存储单元(在此例中存储单元1132与对应的存储元件1148)的电流路径1180,可由施加电压给位线1160、字符线1158与源极线1154来建立,这些电压足以将存储单元1132的存取晶体管导通,并且在路径1180诱发电流,使之从位线1160流到源极线1154,或者反方向。所施加的电压的准位与期间由所执行的操作来决定。
在存储单元1132的重置(擦除)操作,字符线解码器1010提供字符线1158一合适的电压,以导通存储单元1132的存取晶体管。位线解码器1020提供具有合适振幅(大小)与期间之一或多个电压脉冲到位线1160,以诱发电流流经存储器件11148,由此将主动区的至少一部分的温度提高到相变材料的转态温度以上并且也高于融化温度,以使主动区的至少一部分处于液态。电流之后终止,例如由终止位线1160上的电压脉冲以及字符线1158上的电压,造成相当快的猝冷时间,让主动区快速冷却以稳定到非晶相。
在存储单元1132的读取(或感测)操作时,字符线解码器1010提供字符线1158一合适的电压来导通存储单元1132的存取晶体管。位线解码器1120提供具有合适振幅(大小)与期间的一电压到位线1160,以诱发电流流动,该电流不会造成存储器件11148经历电阻状态的改变。位线1160上和经过存储器件11148的电流是与存储单元1132的存储元件1148的电阻有关,也因此与存储单元1132的存储元件1148相关的资料状态有关。因此,存储单元1132资料状态的决定,可例如由感测放大器对位线1160上的电流与合适的参考电流进行比较。
在存储单元1132的设定(或程序化)操作,字符线解码器1010提供字符线1158一合适的电压,以导通存储单元1132的存取晶体管。位线解码器1020供应具有合适振幅(大小)与期间的一电压到位线1160,以诱发流经存储元件1148的电流,由此将主动区的至少一部分的温度提高到相变材料的转态温度以上,造成主动区至少一部分从非结晶相到结晶相的转态,此转态降低存储器件11148电阻且将存储单元1132设定到所要状态。
此处描述的存储器件的存储器材材料的实施例包括相变存储器材料,其包括硫属化合物材料和其它材料。硫属元素包含氧(O)、硫(S)、硒(Se)和碲(Te)四种元素的任一个,形成周期表VI A族的一部分。硫属化合物包括硫族元素和较电正性元素或自由基的化合物。硫属化合物合金包括硫属元素和其它像过度金属的材料的组合。硫属化合物合金通常包含一个或多个来自元素周期表的IV A族的元素,如锗(Ge)和锡(Sn)。通常,硫属化合物合金包括含一或多个锑(Sb)、镓(Ga)、铟(In)和银(Ag)的组合。很多相变存储器材已经描述在技术文献中,包括Ga/Sb、In/Sb、In/Se、Sb/Te、Ge/Te、Ge/Sb/Te、In/Sb/Te、Ga/Se/Te、Sn/Sb/Te、In/Sb/Ge、Ag/In/Sb/Te、Ge/Sn/Sb/Te、Ge/Sb/Se/Te和Te/Ge/Sb/S。在Ge/Sb/Te合金族中,一大范围的合金的组成是可行的。此组成可被特征化为TeaGebSb100-(a+b)。研究人员已经描述最有用的合金是在沉积材料中Te的平均浓度为正好70%以下,典型是低于60%,且范围一般从最低大约23%至58%的Te,较佳是约48%到58%的Te。Ge的浓度在大约5%以上,并且在材料中的范围平均是自最低8%到大约30%,剩下的一般在50%以下。较佳来说,Ge浓度范围自大约8%到大约40%。在此组成中主要构成元素的剩余部分是Sb。这些百分比是原子百分比,总构成元素的原子是100%。(Ovshinsky,112专利,col.10-11)。其它研究员所评估的特定合金包括Ge2Sb2Te2、GeSb2Te4和GeSb4Te7(Noboru Yamada,“Potential of Ge-Sb-Te-Phase-Change Optical Disksfor High-Data-Rate Recording”,SPIE v.3109,pp.28-37(1997))。更一般地,如铬(Cr)、铁(Fe)、镍(Ni)、铌(Nb)、钯(Pd)、铂(Pt)和混合物或其合金的过渡金属,可以和Ge/Sb/Te结合以形成具有可程序化电阻特性的相变合金。在栏11-13,Ovshinsky‘112给出了可能有用的存储器材料的特定例子。
在一些实施例中,硫属化合物和其它相变材料以杂质进行掺杂,以修正导电率、转移温度、融化温度以及使用掺杂硫属化合物的存储器件的其它特性。用来掺杂硫属化合物的代表性杂质包含氮、硅、氧、二氧化硅、氮化硅、铜、银、金、铝、氧化铝、钽、氧化钽、氮化钽、钛和氧化钛。例如,参考美国专利号No.6,800,504和美国专利申请公开号No.2005/0029502,在此一并列入参考。
相变合金能够在存储单元的主动信道区中以其局部秩序,在第一结构状态与第二结构状态之间切换,其中在第一状态下材料是一般非结晶固态相,而在第二状态下材料是一般结晶固态相。这些合金至少是双稳态。非结晶一词在此是代表相对较少秩序的结构,比单晶更失序(disorder),其所具有可侦测特性是例如比结晶相更高的电阻率。结晶一词在此是代表相对更有秩序的结构,比非结晶结构更有秩序,其所具有可侦测特性是例如比非结晶相更低的电阻率。典型地,在横跨完全非结晶态与完全结晶态间的频谱,相变材料可于局部秩序的相异可侦测状态之间被电性切换。受非结晶和结晶相间改变影响的其它材料特性包括原子秩序、自由电子密度和活化能。材料可在不同的固相之间切换,或者是切换成二或更多固相的混合物,以提供完全非结晶和完全结晶状态之间的灰阶。材料的电性特性可因此改变。
相变合金可由施加电脉冲,而从一相态改变到另一相态。观察到的是较短、较高振幅的脉冲会将相变材料改变到一般非结晶状态,而较长、较低振幅的脉冲会将相变材料改变至一般结晶状态。较短、较高振福的能量是足够高以让结晶结构的键结被破坏,并且足够短以防止原子重新排列成结晶状态。适当的脉冲轮廓(profile)不需要过度实验便可以被决定,特别适用于特殊相变合金。在接下来揭露中,相变材料被称为GST,且可理解的是其它类型的相变材料也可以使用。在此描述的对于PCRAM实施有用的材料是Ge2Sb2Te5。
其它可程序化电阻性存储器料可以使用在本发明的其它实施例,其包括使用不同结晶相变以决定电阻的材料,或其它用电脉冲来改变电阻状态的其它存储器材料。例子包括使用于电阻随机存取存储器的材料,如包含氧化钨(WOx)、NiO、Nb2O5、CuO2、Ta2O5、Al2O3、CoO、Fe2O3、HfO2、TiO2、SrTiO3、(BaSr)TiO3等的金属氧化物。其它例子包括用于磁阻随机存取存储器(MRAM)的材料,如自旋力矩转移(spin-torque-transfer)MRAM,材料例如是CoFeB、Fe、Co、Ni、Gd、Dy、CoFe、NiFe、MnAs、MnBi、MnSb、CrO2、MnFe2O3、FeOFe2O5、NiOFe2O3、MgOFe2、EuO和Y3Fe5O12的至少其中之一。又例如,美国专利公开号No.2008/0176251,其发明名称“磁性存储器元件及其制造方法(Magnetuc Memory Device and Method ofFabricating the Same)”,在此一并提出作为参考。其它例子包括使用在可程序化金属化存储单元(programmable-metallization-cell,PMC)存储器,或奈米离子存储器(nanoionic memory)的固态电解质材料,如掺杂银的硫化锗电解质和掺杂铜的硫化锗电解质。又,例如,N.E.Gilbert等人在Solid-State Electonic 49(2005)1813-1819中所发表的“A macromodel of programmable metallization cell devices”,在此也一并列入参考。
一个形成硫属化合物材料的范例方法是,在1mTorr-100mTorr压力下,以Ar、N2及/或He的气体源,使用PVD渐镀或磁控溅镀方法。沉积通常在室温下完成。可以使用具有高宽比1-5的准直器来改善填充效能(fill-inperformance)。为了改善填充效能,通常也使用数10伏特到数百伏特的直流偏压。另一方面,直流偏压和准直器可以同时使用。
一个形成硫属化合物材料的范例方法是使用化学气相沉积法(CVD),如美国专利公开号No.2006/0172067,发明名称为“硫属化合物材料的化学气相沉积(Chemical Vapor Deposition of ChalcogenideMaterials)”,在此一并列入参考。
在真空或N2环境下之后沉积回火处理是选择性执行,以改进硫属化合物材料的结晶状态。回火时间少于30分时,回火温度一般范围是100℃到400℃。
Claims (9)
1.一种制造存储器装置的方法,包括:
形成一导电性接触部;
形成一绝缘元件,其中该绝缘元件具有一近端、一远程和一内表面,该内表面用以定义一内部,而该近端邻近该导电性接触部;
形成一底电极,该底电极与该导电性接触部接触,并且在该内部中从该近端向上延伸,该底电极具有一上表面;以及
在该绝缘元件上,形成一存储器元件,该存储器元件包括可程序化电阻存储器材料,其中该存储器元件围绕该绝缘元件的一外表面,并且在从该远程向下延伸的该内部中,以在一第一接触表面,与该底电极的该上表面接触;
其中,形成一绝缘元件包括:
形成一第一材料层,并且在该第一材料层上形成一第二材料层;
在该第一和该第二材料层中,形成一介层窗,以暴露该导电性接触部,其中该介层窗具有一侧壁;以及
在该介层窗中并包含在该介层窗的该侧壁上,沉积一绝缘材料的一层,非等向性蚀刻该绝缘材料,在该介层窗的该侧壁上形成该绝缘元件。
2.如权利要求1所述的制造存储器装置的方法,其中该存储器元件具有一下表面,该下表面位于该底电极的该上表面下。
3.如权利要求1所述的制造存储器装置的方法,其中形成该底电极包括:
在由该绝缘元件的该内表面所定义的该内部中,填入一底电极材料;以及
从该内部的一上部分,移除该底电极材料,以形成该底电极。
4.如权利要求1所述的制造存储器装置的方法,其中该内部具有一宽度,该宽度小于一最小特征尺寸,该最小特征尺寸用于形成该存储器装置的一光刻工艺。
5.如权利要求1所述的制造存储器装置的方法,还包括:
形成一顶电极,由该存储器元件,与该绝缘元件的该远程分离,并且与该存储器元件接触于一第二接触表面,其中该第二接触表面的表面积大于该第一接触表面的表面积。
6.如权利要求1所述的制造存储器装置的方法,其中该存储器元件包括一材料,该材料的热导率低于该绝缘元件的材料的热导率。
7.如权利要求1所述的制造存储器装置的方法,其中该内部在该近端与该远程具有相同的宽度。
8.如权利要求1所述的制造存储器装置的方法,其中形成该底电极和形成该存储器元件包括:
在由该绝缘元件的该内表面所定义的该内部中,填入一底电极材料;
从该内部的一上部分,移除该底电极材料,以从剩下的底电极材料形成该底电极;
移除该第二材料层,以暴露该绝缘元件的该外表面;以及
在该内部的该上部分上与在该绝缘元件的该暴露外表面上,沉积一存储器材料。
9.一种制造存储器装置的方法,包括:
形成一导电性接触部;
形成一绝缘元件,其中该绝缘元件具有一近端、一远程和一内表面,该内表面用以定义一内部,而该近端邻近该导电性接触部;
形成一底电极,该底电极与该导电性接触部接触,并且在该内部中从该近端向上延伸,该底电极具有一上表面;以及
在该绝缘元件上,形成一存储器元件,该存储器元件包括可程序化电阻存储器材料,其中该存储器元件围绕该绝缘元件的一外表面,并且在从该远程向下延伸的该内部中,以在一第一接触表面,与该底电极的该上表面接触;
其中,形成一绝缘元件包括:形成一第一材料层,并且在该第一材料层上形成一第二材料层;在该第一和该第二材料层中,形成一介层窗,以暴露该导电性接触部,其中该介层窗具有一侧壁;以及在该介层窗中并包含在该介层窗的该侧壁上,沉积一绝缘材料的一层,非等向性蚀刻该绝缘材料,在该介层窗的该侧壁上形成该绝缘元件;
形成一底电极,包括:在由该绝缘元件的该内表面所定义的该内部,填入一底电极材料;以及从该内部的一上部分,移除该底电极材料,以从剩余底电极材料,形成该底电极。
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