CN101888243B - 数字锁相环电路及其方法 - Google Patents
数字锁相环电路及其方法 Download PDFInfo
- Publication number
- CN101888243B CN101888243B CN200910177110.4A CN200910177110A CN101888243B CN 101888243 B CN101888243 B CN 101888243B CN 200910177110 A CN200910177110 A CN 200910177110A CN 101888243 B CN101888243 B CN 101888243B
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- delay
- phase
- reference clock
- digital
- signal
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- 238000000034 method Methods 0.000 title claims abstract description 22
- 239000000872 buffer Substances 0.000 claims description 9
- 238000001914 filtration Methods 0.000 claims description 7
- 238000011002 quantification Methods 0.000 claims description 7
- 239000013078 crystal Substances 0.000 claims description 5
- 238000005070 sampling Methods 0.000 claims description 5
- 230000008901 benefit Effects 0.000 abstract description 12
- 238000005516 engineering process Methods 0.000 abstract description 12
- 238000004088 simulation Methods 0.000 abstract description 12
- 230000008569 process Effects 0.000 abstract description 10
- 230000010355 oscillation Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000007423 decrease Effects 0.000 description 2
- 230000001934 delay Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 125000002015 acyclic group Chemical group 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
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- 230000000630 rising effect Effects 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/0802—Details of the phase-locked loop the loop being adapted for reducing power consumption
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
- H03L2207/50—All digital phase-locked loop
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
Description
Claims (12)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201510522469.6A CN105119598A (zh) | 2009-05-13 | 2009-09-25 | 数字锁相环电路及其方法 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/465,547 | 2009-05-13 | ||
US12/465,547 US8102195B2 (en) | 2009-05-13 | 2009-05-13 | Digital phase-locked loop circuit including a phase delay quantizer and method of use |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201510522469.6A Division CN105119598A (zh) | 2009-05-13 | 2009-09-25 | 数字锁相环电路及其方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN101888243A CN101888243A (zh) | 2010-11-17 |
CN101888243B true CN101888243B (zh) | 2015-09-30 |
Family
ID=43068008
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN200910177110.4A Expired - Fee Related CN101888243B (zh) | 2009-05-13 | 2009-09-25 | 数字锁相环电路及其方法 |
CN201510522469.6A Pending CN105119598A (zh) | 2009-05-13 | 2009-09-25 | 数字锁相环电路及其方法 |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201510522469.6A Pending CN105119598A (zh) | 2009-05-13 | 2009-09-25 | 数字锁相环电路及其方法 |
Country Status (3)
Country | Link |
---|---|
US (2) | US8102195B2 (zh) |
CN (2) | CN101888243B (zh) |
TW (1) | TW201041313A (zh) |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2009125580A1 (ja) * | 2008-04-11 | 2009-10-15 | 株式会社アドバンテスト | ループ型クロック調整回路および試験装置 |
US7973578B2 (en) * | 2008-12-01 | 2011-07-05 | Samsung Electronics Co., Ltd. | Time-to-digital converter and all-digital phase-locked loop |
TWI364169B (en) * | 2008-12-09 | 2012-05-11 | Sunplus Technology Co Ltd | All digital phase locked loop circuit |
GB2469473A (en) * | 2009-04-14 | 2010-10-20 | Cambridge Silicon Radio Ltd | Digital phase locked loop |
KR101024243B1 (ko) * | 2009-06-02 | 2011-03-29 | 주식회사 하이닉스반도체 | 버스트 트래킹 지연고정루프 |
TWI447997B (zh) * | 2010-12-16 | 2014-08-01 | Nat Applied Res Laboratories | 衰減器 |
US8207770B1 (en) * | 2010-12-23 | 2012-06-26 | Intel Corporation | Digital phase lock loop |
TW201230733A (en) * | 2011-01-12 | 2012-07-16 | Tsung-Hsien Lin | Receiver |
US8570107B2 (en) * | 2011-04-01 | 2013-10-29 | Mediatek Singapore Pte. Ltd. | Clock generating apparatus and frequency calibrating method of the clock generating apparatus |
TWI475353B (zh) * | 2011-05-05 | 2015-03-01 | Faraday Tech Corp | 時脈產生方法、無參考頻率接收器、以及無晶體振盪器系統 |
US8791732B2 (en) * | 2011-05-09 | 2014-07-29 | Mediatek Inc. | Phase locked loop |
WO2013048390A1 (en) * | 2011-09-28 | 2013-04-04 | Intel Corporation | Apparatus, system, and method for controlling temperature and power supply voltage drift in a digital phase locked loop |
US8797075B2 (en) | 2012-06-25 | 2014-08-05 | Intel Corporation | Low power oversampling with reduced-architecture delay locked loop |
CN103684428B (zh) * | 2012-09-08 | 2016-09-07 | 复旦大学 | 一种用于全数字锁相环的动态器件匹配的方法 |
US9438254B1 (en) * | 2015-05-21 | 2016-09-06 | Stmicroelectronics International N.V. | Charge pump circuit for a phase locked loop |
CN106209093B (zh) * | 2016-03-02 | 2019-05-07 | 北京大学 | 一种全数字小数分频锁相环结构 |
US10659061B2 (en) | 2016-12-27 | 2020-05-19 | Intel Corporation | Divider-less fractional PLL architecture |
US10749535B2 (en) | 2017-06-28 | 2020-08-18 | Analog Devices, Inc. | Apparatus and methods for distributed timing using digital time stamps from a time-to-digital converter |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1398455A (zh) * | 2000-05-09 | 2003-02-19 | 印芬龙科技股份有限公司 | 数字锁相环 |
CN1898871A (zh) * | 2003-12-24 | 2007-01-17 | 英特尔公司 | 可编程序直接***式延迟锁定环路 |
CN101335522A (zh) * | 2007-06-25 | 2008-12-31 | 三星电子株式会社 | 数字频率检测器和使用该数字频率检测器的数字锁相环 |
Family Cites Families (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
SE517602C2 (sv) * | 1995-10-20 | 2002-06-25 | Ericsson Telefon Ab L M | Fastlåst loop |
JPH1188125A (ja) * | 1997-09-03 | 1999-03-30 | Sony Corp | ディジタル制御発振回路およびpll回路 |
TW583837B (en) * | 2003-05-06 | 2004-04-11 | Realtek Semiconductor Corp | Phase frequency detector applied in digital PLL system |
US7415092B2 (en) * | 2003-12-15 | 2008-08-19 | Aktino, Inc. | Low wander timing generation and recovery |
DE102004006995B4 (de) * | 2004-02-12 | 2007-05-31 | Infineon Technologies Ag | Digitaler Phasenregelkreis für Sub-µ-Technologien |
US7068110B2 (en) * | 2004-06-28 | 2006-06-27 | Silicon Laboratories Inc. | Phase error cancellation |
DE102004037162A1 (de) * | 2004-07-30 | 2006-03-23 | Infineon Technologies Ag | Verfahren und Vorrichtung zur Erzeugung eines Taktsignals |
CN1741389B (zh) * | 2004-08-26 | 2014-06-11 | 瑞昱半导体股份有限公司 | 具有非线性相位误差反应特性的锁相环 |
US7271664B2 (en) * | 2005-10-18 | 2007-09-18 | Credence Systems Corporation | Phase locked loop circuit |
CN1761157A (zh) * | 2005-11-10 | 2006-04-19 | 复旦大学 | 适用各种环振锁相环的动态电压模相位内插电路 |
CN1968019A (zh) * | 2005-11-16 | 2007-05-23 | 弥亚微电子(上海)有限公司 | 一种用于市电精确检测的全数字锁相环路 |
WO2008022226A2 (en) * | 2006-08-15 | 2008-02-21 | Ess Technology, Inc. | Asynchronous sample rate converter |
GB0622948D0 (en) * | 2006-11-17 | 2006-12-27 | Zarlink Semiconductor Inc | A digital phase locked loop |
GB0622941D0 (en) * | 2006-11-17 | 2006-12-27 | Zarlink Semiconductor Inc | An asynchronous phase acquisition unit with dithering |
US7656323B2 (en) * | 2007-05-31 | 2010-02-02 | Altera Corporation | Apparatus for all-digital serializer-de-serializer and associated methods |
KR101493777B1 (ko) * | 2008-06-11 | 2015-02-17 | 삼성전자주식회사 | 주파수 검출기 및 이를 포함하는 위상 동기 루프 |
US7733149B2 (en) * | 2008-06-11 | 2010-06-08 | Pmc-Sierra, Inc. | Variable-length digitally-controlled delay chain with interpolation-based tuning |
US7772900B2 (en) * | 2008-07-15 | 2010-08-10 | International Business Machines Corporation | Phase-locked loop circuits and methods implementing pulsewidth modulation for fine tuning control of digitally controlled oscillators |
US7750701B2 (en) * | 2008-07-15 | 2010-07-06 | International Business Machines Corporation | Phase-locked loop circuits and methods implementing multiplexer circuit for fine tuning control of digitally controlled oscillators |
US8212610B2 (en) * | 2008-09-19 | 2012-07-03 | Altera Corporation | Techniques for digital loop filters |
US7864915B2 (en) * | 2008-10-08 | 2011-01-04 | Qualcomm Incorporated | Low-power asynchronous counter and method |
US7847643B2 (en) * | 2008-11-07 | 2010-12-07 | Infineon Technologies Ag | Circuit with multiphase oscillator |
US7733151B1 (en) * | 2008-12-08 | 2010-06-08 | Texas Instruments Incorporated | Operating clock generation system and method for audio applications |
US20100182049A1 (en) * | 2009-01-22 | 2010-07-22 | Henrik Sjoland | Digital Phase Detection |
-
2009
- 2009-05-13 US US12/465,547 patent/US8102195B2/en not_active Expired - Fee Related
- 2009-09-18 TW TW098131474A patent/TW201041313A/zh unknown
- 2009-09-25 CN CN200910177110.4A patent/CN101888243B/zh not_active Expired - Fee Related
- 2009-09-25 CN CN201510522469.6A patent/CN105119598A/zh active Pending
-
2011
- 2011-12-12 US US13/323,448 patent/US8373467B2/en active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1398455A (zh) * | 2000-05-09 | 2003-02-19 | 印芬龙科技股份有限公司 | 数字锁相环 |
CN1898871A (zh) * | 2003-12-24 | 2007-01-17 | 英特尔公司 | 可编程序直接***式延迟锁定环路 |
CN101335522A (zh) * | 2007-06-25 | 2008-12-31 | 三星电子株式会社 | 数字频率检测器和使用该数字频率检测器的数字锁相环 |
Also Published As
Publication number | Publication date |
---|---|
US8373467B2 (en) | 2013-02-12 |
US20120081159A1 (en) | 2012-04-05 |
CN105119598A (zh) | 2015-12-02 |
TW201041313A (en) | 2010-11-16 |
US8102195B2 (en) | 2012-01-24 |
CN101888243A (zh) | 2010-11-17 |
US20100289541A1 (en) | 2010-11-18 |
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Owner name: LIANFA SCIENCE AND TECHNOLOGY CO., LTD. Free format text: FORMER OWNER: RALINK TECHNOLOGY (SINGAPORE) CORPORATION PTE. LTD. Effective date: 20111207 |
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Effective date of registration: 20111207 Address after: Hsinchu City, Taiwan, China Applicant after: MediaTek.Inc Address before: Singapore Maxwell Rd Applicant before: Ralink Technology Singapore Corp. |
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Granted publication date: 20150930 Termination date: 20160925 |