CN105789334A - Schottky barrier semiconductor rectifier and manufacturing method therefor - Google Patents
Schottky barrier semiconductor rectifier and manufacturing method therefor Download PDFInfo
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- CN105789334A CN105789334A CN201610148515.5A CN201610148515A CN105789334A CN 105789334 A CN105789334 A CN 105789334A CN 201610148515 A CN201610148515 A CN 201610148515A CN 105789334 A CN105789334 A CN 105789334A
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- 230000004888 barrier function Effects 0.000 title claims abstract description 51
- 239000004065 semiconductor Substances 0.000 title claims abstract description 31
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 82
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 48
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 41
- 239000002184 metal Substances 0.000 claims abstract description 30
- 229910052751 metal Inorganic materials 0.000 claims abstract description 30
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 28
- 238000000034 method Methods 0.000 claims abstract description 17
- 238000001259 photo etching Methods 0.000 claims abstract description 8
- 229920005591 polysilicon Polymers 0.000 claims abstract description 8
- 125000006850 spacer group Chemical group 0.000 claims abstract description 8
- 239000012535 impurity Substances 0.000 claims description 42
- 238000009826 distribution Methods 0.000 claims description 21
- 238000007789 sealing Methods 0.000 claims description 21
- 238000001312 dry etching Methods 0.000 claims description 15
- 238000000151 deposition Methods 0.000 claims description 14
- 230000008021 deposition Effects 0.000 claims description 14
- 238000001039 wet etching Methods 0.000 claims description 12
- 239000000758 substrate Substances 0.000 claims description 10
- 230000015572 biosynthetic process Effects 0.000 claims description 9
- 238000010438 heat treatment Methods 0.000 claims description 6
- 238000002513 implantation Methods 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- FRIKWZARTBPWBN-UHFFFAOYSA-N [Si].O=[Si]=O Chemical compound [Si].O=[Si]=O FRIKWZARTBPWBN-UHFFFAOYSA-N 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 238000005516 engineering process Methods 0.000 description 6
- 238000000407 epitaxy Methods 0.000 description 4
- 230000003071 parasitic effect Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 230000005611 electricity Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 238000004458 analytical method Methods 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000005036 potential barrier Methods 0.000 description 2
- 238000011084 recovery Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000024241 parasitism Effects 0.000 description 1
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- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
- H01L29/8725—Schottky diodes of the trench MOS barrier type [TMBS]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66143—Schottky diodes
Abstract
The invention discloses a schottky barrier semiconductor rectifier. The schottky barrier semiconductor rectifier comprises a schottky barrier metal layer, an epitaxial layer and a first trench, wherein an isolating layer and a silicon dioxide gate-oxide layer are arranged in the first trench; the silicon dioxide gate-oxide layer extends upwards to form a dielectric wall; conductive polysilicon side walls are arranged on the two sides of the dielectric wall; a second trench is formed between the upper part of the epitaxial layer and the conductive polysilicon side walls; a transverse uniform doping region and a gradient doping region are arranged at the upper part of the epitaxial layer; a channel is formed between the gradient doping region and the silicon dioxide gate-oxide layer; spacer regions are arranged among the lower part of the epitaxial layer, the transverse uniform doping region, the gradient doping region and the silicon dioxide gate-oxide layer; a third trench is formed in the second trench; and the schottky barrier metal layer is positioned on the inner side surface of the third trench, and in contact with the epitaxial layer to form the schottky barrier. The schottky barrier semiconductor rectifier has good forward conduction characteristic and high device reliability. The invention also discloses a manufacturing method for the schottky barrier semiconductor rectifier; and the manufacturing method is large in process window, easy to control, low in photoetching number of times, and low in manufacturing cost.
Description
Technical field
The present invention relates to semiconductor device processing technology field, especially relate to a kind of Schottky barrier semiconductor commutator and manufacture method thereof.
Background technology
Semiconductor rectifier is as the switching device of electric energy, for the consideration that system effectiveness improves, more and more higher in the requirement reduced in the performance boosts such as forward conduction voltage drop, raising reverse BV, reduction reverse leakage, raising switching speed.
The previous PN junction diode used as semiconductor rectifier, forward conduction voltage drop is high to need to overcome PN junction potential barrier to cause during due to forward conduction, and few sub-injection during forward conduction causes that switching speed is slow, replaced by Schottky-barrier diode in a lot of applications.The metal level that Schottky-barrier diode is generally deposited with end face by the N-type epitaxy layer of low doping concentration contacts and forms Schottky barrier and constitute.For overcoming the voltage required for Schottky barrier lower than PN junction potential barrier during device forward conduction, and Schottky-barrier diode is many electronic conductions device, and switching speed is fast.Nonetheless, due to the existence of Schottky barrier, only small forward conduction electric current also can produce certain forward conduction voltage drop.Can reducing barrier height by selecting different metals thus reducing this forward conduction voltage drop, but reverse leakage can increase therewith, reverse BV is likely to reduction.Simultaneously, Schottky-barrier diode there is also barrier height and reduces effect, namely along with reverse bias voltage raises the phenomenon that barrier height reduces, this phenomenon can increase reverse leakage further, reduces reverse BV and reduce device reliability, thus limiting the application in the devices of low barrier height.For overcoming the problems referred to above, US Patent No. 5365102 discloses a kind of trench schottky barrier diode, its distinguishing feature is the trench gate that there is the arrangement of some cycles in N-type epitaxy layer, and the Schottky barrier that the metal level of N-type epitaxy layer and end face deposition is formed is present between trench gate.Described trench gate, by the groove extended in N-type epitaxy layer, covers the sealing coat of flute surfaces, and fills the conductive material composition that therein and end face deposition metal level is connected.The trench gate structure of cycle arrangement reduces the electric field intensity at Schottky barrier place during device reverse bias, and part inhibits barrier height to reduce effect, makes device can adopt relatively low barrier height.But Schottky barrier still exists, and trench gate structure occupies electrically conducting surface and amasss so that the problem that under device small area analysis, forward conduction voltage drop is bigger than normal still exists.
US Patent No. 5818084 discloses a kind of semiconductor rectifier not adopting Schottky barrier, and the anode of this device is made up of the grid of groove MOSFET device, source electrode and body electrode short circuit, and negative electrode is made up of the drain electrode of groove MOSFET device.The distinguishing feature of this technology is to adopt trench gate structure, channel vertical, in semiconductor wafer surface, utilizes MOSFET element bulk effect to reduce turn-on threshold voltage, makes device anode add positive electricity, namely, during forward bias, the voltage needed for conducting channel is formed lower than PN junction diode forward cut-in voltage.Meanwhile, because this commutator forward conduction passage is MOSFET element raceway groove, so forward conduction process is without few sub-injection phenomenon.This commutator is integrated in groove MOSFET chip, PN junction body diode parasitic for MOSFET can be avoided to open, thus avoiding parasitic diode from forward conduction to the problem of the big reverse recovery current introduced when reversely closing switching and high Reverse recovery due to voltage spikes further.But, based on the device of this technology as independent semiconductor rectifier, forward conduction voltage drop is more than Schottky-barrier diode.US Patent No. 6420225 discloses a kind of semiconductor rectifier based on planar MOSFET, and namely device anode is made up of the grid of planar MOSFET devices, source electrode and body electrode short circuit, and negative electrode is made up of drain electrode.This device forms medium side wall by anisotropic etching, utilizes the ion implanted regions below side wall protection to form raceway groove.US Patent No. 6448160 discloses a kind of semiconductor rectifier based on planar MOSFET, and this device is partially stripped photoresist by the method for oxygen plasma isotropic etching, by ion implanting at the region that photoresist lift off is fallen raceway groove formed below.US Patent No. 6765264 discloses a kind of semiconductor rectifier based on planar MOSFET, this device method by isotropic etching, the sidewall making medium mask is become by vertical silicon crystal column surface and has certain slope, ion implanting is carried out through this gradient sidewall, forming raceway groove, channel dopant concentration has gradient.The distinguishing feature of these technology is to adopt planar gate structure, and raceway groove is parallel to semiconductor wafer surface, and channel length is short.Owing to have employed short channel channel doping Gradient distribution, the threshold voltage forming conducting channel significantly reduces, thus the forward conduction voltage drop reduced under the forward conduction voltage drop of device, particularly small area analysis is substantially less than Schottky-barrier diode.But; owing to forming the method restriction of short channel and channel doping Gradient distribution; this kind of device is typically based on planar gate structure; device inside parasitism has the technotron that body doped region is constituted; parasitic junction field effect transistor increases the series resistance on conductive channel, with the raising of limit conducting channel density；During in order to avoid device reverse bias, short channel is likely to the break-through electric leakage brought, and outer layer doping concentration is also generally relatively low, further increases the series resistance on conductive channel；Above-mentioned 2 forward conduction voltage drops made under the big electric current of device are higher, usually above trench schottky barrier diode.
As can be seen here, prior art is also weak on semiconductor rectifier forward conduction voltage drop, improves device architecture further and manufacture method is significant.
Summary of the invention
The present invention is to solve the problems referred to above existing for the semiconductor rectifier of prior art, provide a kind of based on trench gate structure, there is short channel and Schottky Barrier Contact simultaneously, there is forward conduction characteristic more preferably, the Schottky barrier semiconductor commutator of forward conduction voltage drop performance and better device reliability under big electric current especially more preferably.
Present invention also offers a kind of Schottky barrier semiconductor commutator manufacture method, this manufacturing approach craft window is big, it is easy to control, manufacturing step is few, low cost of manufacture, it is achieved that based on short channel the channel doping Gradient distribution of trench gate structure, the forward conduction performance of device can be effectively improved.
To achieve these goals, the present invention is by the following technical solutions:
nullA kind of Schottky barrier semiconductor commutator of the present invention，Include anode metal layer from top to bottom、Schottky barrier metal layer、The first lightly doped epitaxial layer of conduction type、The first heavily doped monocrystalline substrate of conduction type and cathode metal layer，Described epitaxial layer upper lateral is arranged at intervals with some first grooves，It is filled with conductive polycrystalline silicon in described first groove，It is provided with sealing coat between described conductive polycrystalline silicon and the first groove，Described sealing coat is provided with silicon dioxide grid oxide layer，Described silicon dioxide grid oxide layer thickness is less than sealing coat，Silicon dioxide grid oxide layer top upwardly extends and is higher than epitaxial layer end face and forms medium wall，The both sides of described medium wall are provided with the conductive polycrystalline silicon side wall of the first conduction type，Region between the conductive polycrystalline silicon side wall of epitaxial layer top and medium outer wall forms the second groove，It is positioned at bottom the conductive polycrystalline silicon side wall of medium outer wall and is provided with the first conduction type heavily doped region above the second channel bottom，Described epitaxial layer top is provided with the second groove、The second conduction type non-uniform doping district that first conduction type heavily doped region and epitaxial layer separate，Described second conduction type non-uniform doping district includes laterally homogeneous doped region and grade doping district，Described grade doping district is positioned at the top of laterally homogeneous doped region both sides and contacts formation raceway groove with silicon dioxide grid oxide layer，Described epitaxial layer bottom、Laterally homogeneous doped region、It is provided with spacer between grade doping district and silicon dioxide grid oxide layer，Described laterally homogeneous doped region longitudinally has doping gradient distribution，Described second groove is provided with the 3rd groove，Described 3rd groove penetrates the second conduction type non-uniform doping district and extends into epitaxial layer，Described schottky barrier metal layer is covered in inside the 3rd groove，And formation Schottky barrier is contacted with epitaxial layer.
A kind of Schottky barrier semiconductor commutator manufacture method, comprises the following steps:
(1) in the heavy doping monocrystalline substrate of the first conduction type, grow the first lightly doped epitaxial layer of conduction type.
(2) photoetching and dry etching is adopted to form the first groove in the epitaxial layer.
(3) silicon dioxide layer is grown as sealing coat at total top layer.
(4) in total surface deposited silicon nitride layer as mask layer.
(5) the first groove is made to be filled at total surface deposited silicon dioxide silicon packed layer.
(6) adopt wet etching selective removal part of silica packed layer, expose the first groove top.
(7) mask layer that wet etching selective removal is not protected by silica-filled layer is adopted.
(8) sealing coat do not protected by mask layer of wet etching selective removal and remaining silica-filled layer are adopted.
(9) wet etching is adopted to remove remaining mask layer.
(10) silicon dioxide grid oxide layer is grown at total top layer.
(11), at total top layer deposition conductive polycrystalline silicon, make conductive polycrystalline silicon fill full first groove.
(12) adopt the partially electronically conductive polysilicon of dry etching selective removal, make conductive polycrystalline silicon end face flush with epitaxial layer end face.
(13) adopt dry etching selective removal part of silica grid oxide layer, make the top exposed of epitaxial layer of the first groove both sides out.
(14) adopt the partially electronically conductive polysilicon of dry etching selective removal and epitaxial layer, make silicon dioxide grid oxide layer exceed epitaxial layer end face and form medium wall.
(15) are at total top layer deposition the first conduction type conductive polycrystalline silicon.
(16) adopt heat treatment to make the impurity in the first conduction type conductive polycrystalline silicon diffuse into epitaxial layer top, form the first conduction type heavily doped region.
(17) adopt dry etching to remove part the first conduction type conductive polycrystalline silicon and epitaxial layer, the conductive polycrystalline silicon side wall of the first conduction type is formed in the both sides of medium wall, form the second groove without in the epitaxial layer that side wall stops, and the degree of depth of the second groove is more than the first conduction type heavily doped region thickness.
(18) adopt first time ion implanting to introduce the first laterally uniform impurity range of the second conduction type in the epitaxial layer of the second beneath trenches, at the first Gradient distribution impurity range of first conduction type heavily doped region the second conduction type introduced below.
(19) adopt second time ion implanting to introduce the second laterally uniform impurity range of the second conduction type in the epitaxial layer of the second beneath trenches, at the second Gradient distribution impurity range of first conduction type heavily doped region the second conduction type introduced below.
(20) adopt third time ion implanting to introduce the 3rd laterally uniform impurity range of the second conduction type in the epitaxial layer of the second beneath trenches.
(21) adopt heat treatment to activate the impurity injected, first laterally uniform impurity range, the second laterally uniform impurity range, the 3rd laterally uniform impurity range constitute laterally homogeneous doped region, first Gradient distribution impurity range, the second Gradient distribution impurity range constitute grade doping district, laterally homogeneous doped region and grade doping district constitute the second conduction type non-uniform doping district, to separate the first conduction type heavily doped region, the second groove and epitaxial layer bottom.
(22) adopt photoetching and are dry-etched in formation the 3rd groove in the middle part of the second groove, by etch period control, make the 3rd gash depth more than bottom the second conduction type non-uniform doping district.
(23) are in total end face Schottky barrier metal layer.
(24) are at total end face deposition anode metal level.
(25) to the first heavily doped monocrystalline substrate of conduction type thinning after, at bottom surface deposition cathode metal layer, obtain trench gate structure semiconductor rectifier.
As preferably, the Implantation Energy that in step (20), third time ion implanting adopts is lower than the Implantation Energy that in step (19), ion implanting adopts for the second time.
Therefore, there is advantages that
(1) adopt trench gate structure, eliminate parasitic junction field effect transistor, decrease the series resistance on conductive channel, it is possible to reduce device forward conduction voltage drop；
(2) trench gate structure is adopted, it is easy to improve conducting channel density, it is possible to reduce device forward conduction voltage drop；
(3) the adjacent trench gate in epitaxial layer is extended into; folder can be formed when device reverse bias short in protect raceway groove, reduce raceway groove place electric field intensity, it is suppressed that short channel break-through is leaked electricity; make epitaxial layer can adopt higher doping content, thus reducing device forward conduction voltage drop；
(4) trench gate adopts the structure that thick sealing coat is combined with thin grid oxide layer, and thicker sealing coat is beneficial to shares more reverse bias voltage, reduces raceway groove place electric field intensity, it is suppressed that short channel break-through is leaked electricity；Relatively thin grid oxide layer can effectively reduce threshold voltage；
(5) spacer arranged in device, it is possible to form folder when device reverse bias short in protect raceway groove, suppresses short channel break-through electric leakage so that epitaxial layer can adopt higher doping content, thus reducing device forward conduction voltage drop further；
(6) channel length is short and doping content can gradient modulation, effectively reduce threshold voltage, thus reducing device forward conduction voltage drop, simultaneously can suppression device reverse bias time contingent short channel break-through electric leakage；
(7) channel length and channel dopant concentration can be modulated by side wall pattern, it is possible to by the energy of ion implanting, dosage, the modulation of injection number of times, it is easy to accomplish short channel；
(8) heavily doped region is contacted and thermal diffusion realization with epitaxial layer by conductive polycrystalline silicon, and heavily doped region impurities concentration distribution is uniform, channel length impact is little, it is easy to accomplish short channel；
(9) silicon dioxide grid oxide layer extends epi-layer surface and forms medium wall, will not affect channel length because of factors such as technical process losses, it is easy to accomplish short channel；
(10) spacer width can be modulated by side wall pattern, and the spacer degree of depth can be passed through the energy of the second gash depth and ion implanting, inject number of times modulation, is easily formed folder short；
(11) Schottky barrier area is introduced, along with device forward bias voltage raises, Schottky barrier area participates in conduction, device forward conduction voltage drop under big electric current can be reduced, or when device is in long-time big electric current forward conduction, start forward conduction along with junction temperature raises Schottky barrier, reduce the burden of conducting channel, improve device reliability；
(12) technological process adopts self-registered technology, and process window is big, it is easy to controlling, whole flow process photoetching number of times is few, and manufacturing step is few, and manufacturing process is short, low cost of manufacture.
Accompanying drawing explanation
Fig. 1 is one structure sectional view of the present invention.
Fig. 2 is the structural representation of embodiment 1 step (six).
Fig. 3 is the structural representation of embodiment 1 step (nine).
Fig. 4 is the structural representation of embodiment 1 step (12).
Fig. 5 is the structural representation of embodiment 1 step (16).
Fig. 6 is the structural representation of embodiment 1 step (20).
Fig. 7 is the structural representation of embodiment 1 step (21).
Fig. 8 is the structural representation of embodiment 1 step (23).
In figure: anode metal layer 1, epitaxial layer 2, monocrystalline substrate 3, cathode metal layer 4, first groove 5, conductive polycrystalline silicon 6, sealing coat 7, medium wall 8, conductive polycrystalline silicon side wall 9, second groove 10, first conduction type heavily doped region 11, second conduction type non-uniform doping district 12, laterally homogeneous doped region 13, grade doping district 14, raceway groove 15, spacer 16, first laterally uniform impurity range 17, first Gradient distribution impurity range 18, second laterally uniform impurity range 19, second Gradient distribution impurity range 20, 3rd laterally uniform impurity range 21, mask layer 22, silica-filled layer 23, silicon dioxide grid oxide layer 24, 3rd groove 25, schottky barrier metal layer 26, first conduction type conductive polycrystalline silicon 27.
Detailed description of the invention
Below in conjunction with the drawings and specific embodiments, the present invention will be further described.
nullA kind of Schottky barrier semiconductor commutator as shown in Figure 1，Include anode metal layer 1 from top to bottom、Schottky barrier metal layer 26、The first lightly doped epitaxial layer 2 of conduction type、The first heavily doped monocrystalline substrate 3 of conduction type and cathode metal layer 4，Epitaxial layer upper lateral is arranged at intervals with some first grooves 5，Conductive polycrystalline silicon 6 it is filled with in first groove，Sealing coat 7 it is provided with between conductive polycrystalline silicon and the first groove，Sealing coat is provided with silicon dioxide grid oxide layer 24，Silicon dioxide grid oxide layer thickness is less than sealing coat，Silicon dioxide grid oxide layer top upwardly extends and is higher than epitaxial layer end face and forms medium wall 8，The both sides of medium wall are provided with the conductive polycrystalline silicon side wall 9 of the first conduction type，Region between the conductive polycrystalline silicon side wall of epitaxial layer top and medium outer wall forms the second groove 10，It is positioned at bottom the conductive polycrystalline silicon side wall of medium outer wall and is provided with the first conduction type heavily doped region 11 above the second channel bottom，Epitaxial layer top is provided with the second groove、The second conduction type non-uniform doping district 12 that first conduction type heavily doped region and epitaxial layer separate，Second conduction type non-uniform doping district includes laterally homogeneous doped region 13 and grade doping district 14，Grade doping district is positioned at the top of laterally homogeneous doped region both sides and contacts formation raceway groove 15 with sealing coat，Epitaxial layer bottom、Laterally homogeneous doped region、Spacer 16 it is provided with between grade doping district and sealing coat，Laterally homogeneous doped region longitudinally has doping gradient distribution，Second groove is provided with the 3rd groove 25，3rd groove penetrates the second conduction type non-uniform doping district and extends into epitaxial layer，Schottky barrier metal layer is covered in inside the 3rd groove，And formation Schottky barrier is contacted with epitaxial layer.
This Schottky barrier semiconductor commutator is obtained by following manufacture method:
(1) in the heavy doping monocrystalline substrate 3 of the first conduction type, grow the first lightly doped epitaxial layer 2 of conduction type；
(2) photoetching and dry etching is adopted to form the first groove 5 in the epitaxial layer；
(3) silicon dioxide layer is grown as sealing coat 7 at total top layer；
(4) in total surface deposited silicon nitride layer as mask layer 22；
(5) the first groove is made to be filled at total surface deposited silicon dioxide silicon packed layer 23；
(6) adopt the silica-filled layer of wet etching selective removal, expose the first groove top (see figure 2)；
(7) mask layer that wet etching selective removal is not protected by silica-filled layer is adopted；
(8) sealing coat do not protected by mask layer of wet etching selective removal and remaining silica-filled layer are adopted；
(9) wet etching is adopted to remove remaining mask layer (see figure 3)；
(10) silicon dioxide grid oxide layer 24 is grown at total top layer；
(11), at total top layer deposition conductive polycrystalline silicon 6, make conductive polycrystalline silicon fill full first groove；
(12) adopt the partially electronically conductive polysilicon of dry etching selective removal, make conductive polycrystalline silicon end face flush (see figure 4) with epitaxial layer end face；
(13) adopt dry etching selective removal part of silica grid oxide layer, make the top exposed of epitaxial layer of the first groove both sides out；
(14) adopt the partially electronically conductive polysilicon of dry etching selective removal and epitaxial layer, make silicon dioxide grid oxide layer exceed epitaxial layer end face and form medium wall 8；
(15) are at total top layer deposition the first conduction type conductive polycrystalline silicon 27；
(16) adopt heat treatment to make the impurity in the first conduction type conductive polycrystalline silicon diffuse into epitaxial layer top, form the first conduction type heavily doped region 11(and see Fig. 5)；
(17) adopt dry etching to remove part the first conduction type conductive polycrystalline silicon and epitaxial layer, the conductive polycrystalline silicon side wall 9 of the first conduction type is formed in the both sides of medium wall, form the second groove 10 without in the epitaxial layer that side wall stops, and the degree of depth of the second groove is more than the first conduction type heavily doped region thickness；
18) first time ion implanting is adopted to introduce the first laterally uniform impurity range 17 of the second conduction type in the epitaxial layer of the second beneath trenches, at the first Gradient distribution impurity range 18 of first conduction type heavily doped region the second conduction type introduced below；
(19) adopt second time ion implanting to introduce the second laterally uniform impurity range 19 of the second conduction type in the epitaxial layer of the second beneath trenches, at the second Gradient distribution impurity range 20 of first conduction type heavily doped region the second conduction type introduced below；
(20) adopt third time ion implanting to introduce the 3rd laterally uniform impurity range 21 of the second conduction type, the Implantation Energy (see figure 6) that the Implantation Energy that third time ion implanting adopts adopts lower than second time ion implanting in the epitaxial layer of the second beneath trenches；
(21) adopt heat treatment to activate the impurity injected, first laterally uniform impurity range, the second laterally uniform impurity range, the 3rd laterally uniform impurity range constitute laterally homogeneous doped region 13, first Gradient distribution impurity range, the second Gradient distribution impurity range constitute grade doping district 14, laterally homogeneous doped region and grade doping district constitute the second conduction type non-uniform doping district 12, to separate the first conduction type heavily doped region, the second groove and epitaxial layer bottom (see figure 7)；
(22) adopt photoetching and are dry-etched in formation the 3rd groove 25 in the middle part of the second groove, by etch period control, make the 3rd gash depth more than bottom the second conduction type non-uniform doping district；
(23) see Fig. 8 at total end face Schottky barrier metal layer 26()；
(24) are at total end face deposition anode metal level 1；
(25) to the first heavily doped monocrystalline substrate of conduction type thinning after, at bottom surface deposition cathode metal layer 4, obtain trench gate structure semiconductor rectifier (see figure 1).
Embodiment described above is the one preferably scheme of the present invention, not the present invention is done any pro forma restriction, also has other variant and remodeling under the premise without departing from the technical scheme described in claim.
Claims (3)
- null1. a Schottky barrier semiconductor commutator，Include anode metal layer (1) from top to bottom、Schottky barrier metal layer (26)、The lightly doped epitaxial layer of first conduction type (2)、The heavily doped monocrystalline substrate of first conduction type (3) and cathode metal layer (4)，Described epitaxial layer upper lateral is arranged at intervals with some first grooves (5)，Conductive polycrystalline silicon (6) it is filled with in described first groove，It is characterized in that，Sealing coat (7) it is provided with between described conductive polycrystalline silicon and the first groove，Described sealing coat is provided with silicon dioxide grid oxide layer (24)，Described silicon dioxide grid oxide layer thickness is less than sealing coat，Silicon dioxide grid oxide layer top upwardly extends and is higher than epitaxial layer end face and forms medium wall (8)，The both sides of described medium wall are provided with the conductive polycrystalline silicon side wall (9) of the first conduction type，Region between the conductive polycrystalline silicon side wall of epitaxial layer top and medium outer wall forms the second groove (10)，It is positioned at bottom the conductive polycrystalline silicon side wall of medium outer wall and is provided with the first conduction type heavily doped region (11) above the second channel bottom，Described epitaxial layer top is provided with the second groove、The second conduction type non-uniform doping district (12) that first conduction type heavily doped region and epitaxial layer separate，Described second conduction type non-uniform doping district includes laterally homogeneous doped region (13) and grade doping district (14)，Described grade doping district is positioned at the top of laterally homogeneous doped region both sides and contacts formation raceway groove (15) with silicon dioxide grid oxide layer，Described epitaxial layer bottom、Laterally homogeneous doped region、Spacer (16) it is provided with between grade doping district and silicon dioxide grid oxide layer，Described laterally homogeneous doped region longitudinally has doping gradient distribution，Described second groove is provided with the 3rd groove (25)，Described 3rd groove penetrates the second conduction type non-uniform doping district and extends into epitaxial layer，Described schottky barrier metal layer is covered in inside the 3rd groove，And formation Schottky barrier is contacted with epitaxial layer.
- 2. a Schottky barrier semiconductor commutator manufacture method as claimed in claim 1, it is characterised in that comprise the following steps:(1) in the heavy doping monocrystalline substrate (3) of the first conduction type upper growth lightly doped epitaxial layer of the first conduction type (2)；(2) photoetching and dry etching is adopted to form the first groove (5) in the epitaxial layer；(3) silicon dioxide layer is grown as sealing coat (7) at total top layer；(4) in total surface deposited silicon nitride layer as mask layer (22)；(5) the first groove is made to be filled on total surface deposited silicon dioxide silicon packed layer (23)；(6) adopt wet etching selective removal part of silica packed layer, expose the first groove top；(7) mask layer that wet etching selective removal is not protected by silica-filled layer is adopted；(8) sealing coat do not protected by mask layer of wet etching selective removal and remaining silica-filled layer are adopted；(9) wet etching is adopted to remove remaining mask layer；(10) silicon dioxide grid oxide layer (24) is grown at total top layer；(11), in total top layer deposition conductive polycrystalline silicon (6), make conductive polycrystalline silicon fill full first groove；(12) adopt the partially electronically conductive polysilicon of dry etching selective removal, make conductive polycrystalline silicon end face flush with epitaxial layer end face；(13) adopt dry etching selective removal part of silica grid oxide layer, make the top exposed of epitaxial layer of the first groove both sides out；(14) adopt the partially electronically conductive polysilicon of dry etching selective removal and epitaxial layer, make silicon dioxide grid oxide layer exceed epitaxial layer end face and form medium wall (8)；(15) are in total top layer deposition the first conduction type conductive polycrystalline silicon (27)；(16) adopt heat treatment to make the impurity in the first conduction type conductive polycrystalline silicon diffuse into epitaxial layer top, form the first conduction type heavily doped region (11)；(17) adopt dry etching to remove part the first conduction type conductive polycrystalline silicon and epitaxial layer, the conductive polycrystalline silicon side wall (9) of the first conduction type is formed in the both sides of medium wall, form the second groove (10) without in the epitaxial layer that side wall stops, and the degree of depth of the second groove is more than the first conduction type heavily doped region thickness；(18) adopt first time ion implanting to introduce the first laterally uniform impurity range (17) of the second conduction type in the epitaxial layer of the second beneath trenches, at the first Gradient distribution impurity range (18) of first conduction type heavily doped region the second conduction type introduced below；(19) adopt second time ion implanting to introduce the second laterally uniform impurity range (19) of the second conduction type in the epitaxial layer of the second beneath trenches, at the second Gradient distribution impurity range (20) of first conduction type heavily doped region the second conduction type introduced below；(20) adopt third time ion implanting to introduce the 3rd laterally uniform impurity range (21) of the second conduction type in the epitaxial layer of the second beneath trenches；(21) adopt heat treatment to activate the impurity injected, first laterally uniform impurity range, the second laterally uniform impurity range, the 3rd laterally uniform impurity range constitute laterally homogeneous doped region (13), first Gradient distribution impurity range, the second Gradient distribution impurity range constitute grade doping district (14), laterally homogeneous doped region and grade doping district constitute the second conduction type non-uniform doping district (12), to separate the first conduction type heavily doped region, the second groove and epitaxial layer bottom；(22) adopt photoetching and are dry-etched in formation the 3rd groove (25) in the middle part of the second groove, by etch period control, make the 3rd gash depth more than bottom the second conduction type non-uniform doping district；(23) are in total end face Schottky barrier metal layer (26)；(24) are in total end face deposition anode metal level (1)；(25) to the first heavily doped monocrystalline substrate of conduction type thinning after, in bottom surface deposition cathode metal layer (4), obtain trench gate structure semiconductor rectifier.
- 3. Schottky barrier semiconductor commutator manufacture method according to claim 2, it is characterised in that the Implantation Energy that the Implantation Energy that in step (20), third time ion implanting adopts adopts lower than second time ion implanting in step (19).
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| CN110473915A (en) * | 2019-09-18 | 2019-11-19 | 深圳爱仕特科技有限公司 | A kind of preparation method for the SiC-MOS device integrating low potential barrier JBS |
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| CN111430468A (en) * | 2020-03-06 | 2020-07-17 | 江阴新顺微电子有限公司 | Double-core isolation structure of double-cell packaged Schottky diode chip and manufacturing method |
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| CN112103185B (en) * | 2020-09-22 | 2022-01-11 | 深圳市芯电元科技有限公司 | Manufacturing method and structure of trench MOSFET |
| CN113540256A (en) * | 2021-06-16 | 2021-10-22 | 先之科半导体科技(东莞)有限公司 | Voltage-stabilizing anti-creeping silicon carbide diode |
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