CN101804959A - 半导体封装及其制造方法 - Google Patents

半导体封装及其制造方法 Download PDF

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CN101804959A
CN101804959A CN200910159267A CN200910159267A CN101804959A CN 101804959 A CN101804959 A CN 101804959A CN 200910159267 A CN200910159267 A CN 200910159267A CN 200910159267 A CN200910159267 A CN 200910159267A CN 101804959 A CN101804959 A CN 101804959A
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sensing element
molding compounds
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李硕源
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Advanced Semiconductor Engineering Inc
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Abstract

本发明所提供的是一种半导体封装及其制造方法，此半导体封装包括至少一个感测元件与屏蔽层。配置在模塑化合物上的屏蔽层能够保护半导体封装免受电磁干扰辐射，但半导体封装的感测元件不会被此屏蔽层阻挡，故而能够接收感测信号。

Description

半导体封装及其制造方法
技术领域
本发明涉及一种半导体封装(semiconductor package)，特别是涉及一种具有感测元件(sensing component)的半导体封装。
背景技术
对于大多数电子装置或封装而言，电磁干扰(electro-magneticinterference，EMI)是一种普遍存在却扰人的干扰，它会中断、阻碍、降低或限制电子装置或整个电路的有效性能。尤其是，对于微型机电***(micro-electro-mechanical system，MEMS)封装而言，不同的机械构件或元件与各种电子装置结合在一起，甚至会加重电磁干扰。
此外，由于微型机电***封装的复杂性，就算要求较佳的电磁干扰屏蔽，也必须与其他机械元件或装置的封装需求相平衡。按照惯例，先前技术中可使用额外的屏蔽板(shielding plate)或额外的金属层，这与复杂的封装制程可能不相容，或者造成多余的设计工作。
发明内容
鉴于上述原因，所以本发明是针对一种半导体封装制造方法，这种方法能够简化制造过程，而不会降低电磁干扰屏蔽的有效性。
本发明更是针对一种具有至少一个感测元件的微型机电***封装，它能提供高效的电磁干扰屏蔽并保有有效的感测能力。
本发明提供一种半导体封装，此半导体封装包括：载体；至少一个芯片(chip)以及至少一个感测元件，配置在此载体上；模塑化合物(molding compound)；以及屏蔽层。模塑化合物封装着芯片、感测元件的一部分以及载体的一部分。感测元件的感测表面从模塑化合物的开口中部分暴露出来。屏蔽层是配置在模塑化合物上，但未覆盖模塑化合物的开口。
依照本发明的实施例，其中模塑化合物的开口的尺寸小于或等于感测元件的所述感测表面的尺寸。
本发明也提供一种半导体封装，此半导体封装包括：具有通孔(through-hole)的载体；至少一个芯片，配置在此载体上；至少一个感测元件，配置在此载体上；模塑化合物；以及屏蔽层。感测元件从载体的通孔中部分暴露出来。模塑化合物封装着芯片、感测元件的一部分以及载体的一部分，其中感测元件的感测表面从模塑化合物的空隙中暴露出来。屏蔽层是配置在模塑化合物上，且覆盖模塑化合物。
依照本发明的实施例，模塑化合物的空隙的尺寸大于或等于感测元件的感测表面的尺寸，且感测表面从此空隙中完全暴露出来。
依照本发明的实施例，屏蔽层可用焊接材料(solder materials)或金属材料来制成。
依照本发明的实施例，感测元件是经由多条电线或多个凸块(bumps)来以电性方式连接到载体。芯片是经由多条电线或多个凸块来以电性方式连接到半导体封装的载体。
依照本发明的实施例，感测元件是声波感测元件，载体是叠层基底或引线框架。
依照本发明的实施例，其中屏蔽层电性连接到载体的至少一个接地过孔。
本发明提供一种半导体封装制造方法。提供具有多个载体单元的载体后，在每个载体单元上配置至少一个芯片与至少一个感测元件，其中芯片与感测元件电性连接到载体单元。在载体上形成模塑化合物，以封装每个载体单元中的芯片与感测元件的至少一部分，但是每个载体单元中的感测元件的感测表面的至少一部分则暴露出来。在模塑化合物上形成屏蔽层，但不覆盖每个载体单元中的感测元件的暴露出来的感测表面。
依照本发明的一个实施例，屏蔽层是通过印刷制程(printingprocess)或电镀制程(plating process)形成。
依照本发明的一个实施例，感测元件是通过电线焊接方式电性连接到载体。形成所述模塑化合物步骤包括利用局部模塑制程来形成具有一开口的模塑化合物，以使得感测组件的感测表面的至少一部分暴露出来。
依照本发明的一个实施例，感测元件是通过倒装芯片焊接方式电性连接到载体。形成所述模塑化合物步骤包括形成具有空隙的模塑化合物，以使得倒装的感测元件的感测表面暴露出来。
依照本发明的一个实施例，屏蔽层形成之后，还包括执行单一化制程，切断所述载体，以得到单个的半导体封装。
依照本发明的一个实施例，在屏蔽层形成之前，还包括执行半切割制程，以移除模塑化合物的一部分。
依照本发明的一个实施例，其中屏蔽层形成后覆盖着模塑化合物的表面以及所述载体的至少一个接地过孔。
根据上文所述，配置在模塑化合物上的屏蔽层是用作半导体封装的电磁干扰屏蔽，但是感测元件未被此屏蔽层阻挡。依照本发明，利用载体的通孔，在模塑方面就无需做额外的工作，且感测元件可透过此通孔而暴露出来。因此，本发明所揭露的半导体封装提供有效的电磁干扰屏蔽性与高效的感测性能。
上述说明仅是本发明技术方案的概述，为了能够更清楚了解本发明的技术手段，并可依照说明书的内容予以实施，以下以本发明的较佳实施例并配合附图详细说明如后。
附图说明
图1是根据本发明所提出的较佳实施例中，一种半导体封装的横剖面图；
图2A至图2F是根据本发明所提出的较佳实施例中，用来呈现一种半导体封装制造方法的横剖面示意图；
图3A至图3E是根据本发明所提出的另一较佳实施例中，用来呈现一种半导体封装制造方法的横剖面示意图；
图4是根据本发明所提出的另一实施例中，一种半导体封装的横剖面图。
具体实施方式
图1是根据本发明所提出的较佳实施例中，一种半导体封装的横剖面图。请参照图1，本实施例中的半导体封装100包括载体102、至少一个芯片104、至少一个接点(contact)106、至少一个感测元件108、多条电线120、模塑化合物130以及屏蔽层140。载体102可以是叠层(laminated)半导体基底(substrate)(例如，叠层印刷电路板(Printed Circuit Board，PCB))或引线框架(leadframe)。感测元件108例如是有能力侦测或感测声波的声波感测元件。较佳的是，此声波感测元件可以是微型机电***麦克风。感测元件108可经由电线120来电性连接到芯片104，而芯片104则经由电线120来电性连接到载体102的接点106。例如，屏蔽层140的材料可以是焊接材料或金属材料。模塑化合物130封装着芯片104、接点106、电线120以及载体102的一部分。除此以外，模塑化合物130还具有开口132，且感测元件108的顶面108a的至少一部分从开口132中暴露出来。感测元件108的暴露顶面(感测表面)108a负责侦测或感测目标元件(即，声波或音波)。屏蔽层140配置在模塑化合物130上，覆盖着模塑化合物130的暴露表面130a(即，开口132周围的顶面以及四个侧墙)，但未覆盖开口132。此外，屏蔽层140还覆盖着载体102的接地过孔(ground vias)105，且屏蔽层140电性连接到此接地过孔105，并且接地。
在本实施例所揭露的半导体封装100中，配置在模塑化合物上的屏蔽层是用作电磁干扰屏蔽，特别保护半导体封装免受周围辐射源的电磁干扰辐射。
在本实施例中，屏蔽层的边缘可与载体的边缘对齐。除此以外，本实施例中的半导体封装还可包括位于载体上的用来提供不同功能的被动元件(passive components)。原则上，此半导体封装可以是微型机电***封装，尤其是其内部具有感测元件的微型机电***封装。
图2A至图2F是根据本发明所提出的较佳实施例中，用来呈现一种半导体封装制造方法的横剖面示意图。
请参照图2A，提供一阵列载体10，此阵列载体10具有多个载体单元102与多个接点106。此后所描述的载体单元102可视为图1中的载体102。在载体单元102上配置至少一个芯片104与至少一个感测元件108。此芯片104与感测元件108可通过粘合材料来安装在载体单元102上。例如，此粘合材料可以是环氧胶(epoxy glue)或硅有机树脂胶(silicone glue)。
请参照图2B，形成多条电线120，用来以电性方式连接芯片104与载体单元102的接点106，以及以电性方式来连接芯片104与同一载体单元102内的感测元件108。可选择的是，芯片104也可通过倒装芯片焊接技术(flipchip bonding technology)而不是通过电线焊接技术(wire bondingtechnology)电性连接到载体单元102。
请参照图2C，执行一种局部模塑制程，使用例如橡胶中心销技术(rubbercore pin technology)或薄膜模型技术(film mold technology)，在载体单元102上形成模塑化合物130以封装芯片104、接点106、感测元件108以及载体单元102的至少一部分。在模塑制程中，模型的特定突出部分对应地对准并接触感测元件108，使得所形成的模塑化合物130具有一开口132，此开口132使感测元件108的顶面108a暴露出来。一般而言，开口132的尺寸小于或至多等于相对应暴露的感测元件的尺寸。较佳的是，开口的尺寸较小，使得感测元件被模塑化合物局部保护着。
请参照图2D，执行半切割制程，以移除位于阵列载体10之开放区域内的模塑化合物130的一部分。
请参照图2E，在阵列载体10上以及模塑化合物130的暴露表面上形成屏蔽层140，但不覆盖开口132或感测元件108的顶面108a。屏蔽层140可以电性方式与载体10的接地过孔105相连接。例如，屏蔽层140的材料可以是用丝网印刷法(screen printing method)来形成的焊接材料或是用电镀法(plating method)来形成的金属材料。因为屏蔽层140是通过印刷或电镀形成的，所以屏蔽层140可选择性地形成以覆盖模塑化合物与载体，而不会阻碍感测元件108的侦测感知。
最后，如图2F所示，执行单一化制程(singulation process)，以得到半导体封装100。值得注意的是，成型后，屏蔽层140的边缘与载体单元102的边缘对齐。
形成在模塑化合物上的屏蔽层有利于半导体封装的电磁干扰屏蔽，但屏蔽层不覆盖模塑化合物的开口，这样就不会妨碍感测元件的感测功能。本发明提供一种制造方法，此方法使用简单易懂的方法来在模塑化合物上选择性地形成屏蔽层。此外，此半导体封装提供有效的电磁干扰屏蔽，而不降低此半导体封装所具有的感测元件的感测功能。
图3A至图3E是根据本发明所提出的另一较佳实施例中，用来呈现一种半导体封装制造方法的横剖面示意图。
请参照图3A和图3B，提供一阵列载体10，此阵列载体10具有多个载体单元102与多个接点106。载体单元102包括至少一个通孔103。在载体102上配置至少一个芯片104与至少一个感测元件108。感测元件108是通过多个凸块107以电性方式连接到载体单元102。芯片104可通过粘合材料来安装在载体单元102上。由于感测元件108是以倒装芯片的方式来粘结在载体单元102上，所以感测表面108b(在本说明书中就是底面)朝下，且从通孔103中暴露出来。一般而言，通孔103的尺寸小于或至多等于相对应暴露的感测元件的尺寸。较佳的是，通孔的尺寸较小，使得感测元件从通孔中部分暴露出来。但是，通孔103的尺寸小于凸块107的分布区域的尺寸。例如，凸块107是沿着感测元件108的外部、周边部分来排列，而通孔103则将位于感测元件108之中心部分的感测表面108b暴露出来。
请参照图3B，形成多条电线120，用来电性连接芯片104与载体单元102的接点106。可选择的是，芯片104也可通过倒装芯片焊接技术而不是电线焊接技术电性连接到载体单元102。
请参照图3C，执行模塑制程，在载体单元102上形成模塑化合物130来封装载体单元102上的芯片104、接点106以及感测元件108。但是，此模塑化合物130并不是封装整个感测元件108。由于感测元件108与载体单元102之间有凸块107阻碍着，所以模塑化合物130不会填满感测表面108b、凸块107与包围着通孔103的载体单元的下面部分之间的空间，而具有空隙(void)。因此，感测元件108的感测表面能够暴露出来，以接收声波。
请参照图3D，执行半切割制程，以移除模塑化合物130的一部分。随后，在载体10上以及模塑化合物130的暴露表面上形成屏蔽层140。此屏蔽层140可以电性方式来与载体10的接地过孔105相连接。例如，此屏蔽层140的材料可以是焊接材料或金属材料。屏蔽层140可通过(例如)丝网印刷法、溅射法(sputtering method)或电镀法形成。
最后，如图3E所示，执行单一化制程，完全切断阵列载体10，以得到单个的半导体封装100。值得注意的是，成型后，屏蔽层140的边缘与载体单元102的边缘对齐。
因此，对于本发明所揭露的半导体封装而言，感测元件可通过倒装芯片焊接技术而不是通过先前实施例中所述的电线焊接技术以电性方式连接到载体。如图4所示，主要差别在于，半导体封装400包括感测元件408，此感测元件408是通过介于感测元件408与载体402之间的凸块407电性连接到载体402的接点406。感测元件408从载体402的通孔403中部分暴露出来。配置在模塑化合物430之表面上的屏蔽层440是用作电磁干扰屏蔽。利用介于感测元件与载体之间的凸块，透过感测元件408的感测表面408b及载体402的顶面之间具有的空隙以及通孔403，使得感测元件的感测表面暴露出来，故而能够接收声波。较佳的是，与感测元件的感测表面相比，存在于模塑化合物中的空隙空间具有较大的或相等的尺寸，这使得感测表面408b从空隙中完全暴露出来。
总而言之，位于模塑化合物上的屏蔽层能够有效地保护本发明所揭露的半导体封装免受外界电磁干扰辐射，从而增强电磁干扰屏蔽。依照本发明所揭露的制造过程，感测元件可通过局部模塑制程或利用预先形成的载体通孔来暴露出来。此外，由于电磁干扰屏蔽可选择性地形成在模塑化合物上，而不阻挡感测元件，所以无需为了半导体封装的电磁干扰屏蔽而降低感测元件的感测性能。因此，这种设计与感测元件的封装(尤其是声波感测元件的微型机电***封装)是相容的。
最后应说明的是：以上实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的精神和范围。

Claims (15)

1.一种半导体封装，其特征在于所述半导体封装包括：
载体；
至少一个芯片，配置在所述载体上，且以电性方式连接到所述载体；
至少一个感测元件，配置在所述载体上；
模塑化合物，至少封装着所述芯片、所述感测元件的一部分以及所述载体的一部分，其中所述模塑化合物具有一开口，所述开口使所述感测元件的感测表面的至少一部分暴露出来；以及
屏蔽层，配置在所述模塑化合物上，且覆盖着所述模塑化合物，但不覆盖所述模塑化合物的所述开口。
2.根据权利要求1所述的半导体封装，其中所述模塑化合物的所述开口的尺寸小于或等于所述感测元件的所述感测表面的尺寸。
3.根据权利要求1所述的半导体封装，其中所述屏蔽层以电性方式连接到所述载体的至少一个接地过孔。
4.一种半导体封装制造方法，其特征在于所述半导体封装制造方法包括：
提供具有多个载体单元的载体；
在所述载体单元上配置至少一个芯片与至少一个感测元件，其中所述芯片电性连接到所述载体单元，且所述感测元件电性连接到所述载体单元；
在所述载体上形成模塑化合物，以封装每个载体单元中的所述芯片与所述感测元件的至少一部分，但是每个载体单元中的所述感测元件的感测表面的至少一部分则暴露出来；以及
在所述模塑化合物上形成屏蔽层，但不覆盖每个载体单元中的所述感测元件的暴露着的感测表面。
5.根据权利要求4所述的半导体封装制造方法，其中所述感测元件是通过电线焊接方式电性连接到所述载体。
6.根据权利要求5所述的半导体封装制造方法，其中在所述载体上形成所述模塑化合物包括：利用局部模塑制程来形成具有一开口的所述模塑化合物，以使得所述感测元件的所述感测表面的至少一部分暴露出来。
7.根据权利要求4所述的半导体封装制造方法，其中所述感测元件是通过倒装芯片焊接方式电性连接到所述载体。
8.根据权利要求7所述的半导体封装制造方法，其中在所述载体上形成所述模塑化合物包括：形成具有空隙的所述模塑化合物，以使得倒装的所述感测元件的所述感测表面透过空隙与所述载体的通孔暴露出来。
9.根据权利要求4所述的半导体封装制造方法，其特征在于所述半导体封装制造方法还包括：所述屏蔽层形成之后，执行单一化制程，切断所述载体，以得到单个的半导体封装。
10.根据权利要求9所述的半导体封装制造方法，其特征在于所述半导体封装制造方法还包括：在所述屏蔽层形成之前，执行半切割制程，以移除所述模塑化合物的一部分。
11.根据权利要求4所述的半导体封装制造方法，其中所述屏蔽层是通过丝网印刷制程或电镀制程形成。
12.根据权利要求4所述的半导体封装制造方法，其中所述屏蔽层形成后覆盖着所述模塑化合物的暴露表面以及所述载体的至少一个接地过孔。
13.一种半导体封装，其特征在于所述半导体封装包括：
载体，具有至少一个通孔与多个接点；
至少一个芯片，配置在所述载体上，且电性连接到所述载体的所述接点；
至少一个感测元件，配置在所述载体上，且通过多个凸块电性连接到所述载体，其中所述感测元件的感测表面的至少一部分从所述载体的所述通孔中暴露出来；
模塑化合物，至少封装着所述芯片、所述接点、所述感测元件的一部分以及所述载体的一部分，其中所述感测元件的所述感测表面从所述模塑化合物的空隙中暴露出来；以及
屏蔽层，配置在所述模塑化合物上，且覆盖着所述模塑化合物。
14.根据权利要求13所述的半导体封装，其中所述模塑化合物的所述空隙的尺寸大于或等于所述感测元件的所述感测表面的尺寸，且所述感测表面从所述空隙中完全暴露出来。
15.根据权利要求13所述的半导体封装，其中所述屏蔽层电性连接到所述载体的至少一个接地过孔。
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