CN101800242B - Nano electron device using nanocrystal material as Coulomb island and manufacture method thereof - Google Patents
Nano electron device using nanocrystal material as Coulomb island and manufacture method thereof Download PDFInfo
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- CN101800242B CN101800242B CN 200910077678 CN200910077678A CN101800242B CN 101800242 B CN101800242 B CN 101800242B CN 200910077678 CN200910077678 CN 200910077678 CN 200910077678 A CN200910077678 A CN 200910077678A CN 101800242 B CN101800242 B CN 101800242B
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Abstract
The invention discloses a nano electron device using a nanocrystal material as a Coulomb island and a manufacture method thereof. A pair of nano electrodes is manufactured on a substrate; the nanocrystal material grows between the pair of nano electrodes; the nano electrodes are used as the source and the drain of the device; the nanocrystal is used as the Coulomb island; insulating media growing on the Coulomb island are used as grid media; and electrodes on the insulating media are used as grid electrodes. The nano electron device and the manufacture method thereof have the advantages of simplicity, stability, reliability and few processing steps and are compatible with traditional CMOS processes.
Description
Technical field
The invention belongs to microelectronics technology, relate to nano electron device and nanofabrication technique, particularly a kind of with nanocrystalline material as the nano electron device on coulomb island and preparation method thereof.
Background technology
Follow Moore's Law take complementary Metal-oxide-semicondutor (CMOS) device as the integrated circuit of mainstream technology always developing rapidly, entering 90 nm technology node at integrated circuit in 2004.Along with characteristic size enters into nanoscale, traditional CMOS technology is faced with more and more serious challenge, therefore, becomes the focus of research based on the nano electron device of new principle.
Single-electronic transistor is a kind of typical nano electron device, but have the advantages such as size is little, speed is fast, large-scale integrated low in energy consumption, and have very wide application prospect, as can be used to make single-electron memory, single electron logical circuit, current standard, resistance standard, temperature standard, hypersensitive electrometer, microwave or Infrared Detectors etc.Therefore, single-electronic transistor has become one of following important candidate device that substitutes MOS transistor.
Generally speaking, single-electronic transistor is made of a coulomb structure.As shown in Figure 1, Fig. 1 is the schematic diagram of coulomb structure.Coulomb structure comprises source 101, leakage 102, coulomb island 103, tunnel junction 104 and tunnel junction 105, can further include side grid 106 and side grid 107, and its core is coulomb island 103, tunnel junction 104 and tunnel junction 105.Coulomb island 103 is made of atomic little metal or semiconductor-quantum-point particle, it on a direction respectively the tunnel junction 104 by both sides be connected with source 101, leakage 102 with 105.Source 101 and leakage 102 are positioned at the both sides on coulomb island 103. Tunnel junction 104 and 105 generally is made of insulating barrier, potential barrier of heterogenous junction and the potential field that caused by interfacial state or applied voltage etc.Thereby grid play the effect of the electron number in the electrochemical potential control island of regulating the island.Source 101, leakage 102, side grid 106 and 107 generally are made of metal or doped semiconductor, are connected with the outside.
Single-electronic transistor will work the charging that must satisfy coulomb island can be greater than the condition of heat energy, i.e. e
2/ 2C＞＞k
BT, wherein k
BTherefore be Boltzmann constant, must improve by the capacitor C that reduces the island work temperature of single-electronic transistor, so just must by dwindle as far as possible the tunnel junction area particularly a coulomb island size realize.Therefore, how obtaining undersized coulomb structure is the key of making high temperature even normal temperature single-electron device.
At present, when making the coulomb structure of single-electronic transistor, mostly adopt the direct processing of electron beam lithography and etching or further utilize method for oxidation to obtain and reduce the size on coulomb island, but the working temperature of the device of preparation is not high in this way, and generally all has the shortcomings such as complex manufacturing technology, cost of manufacture height.
Summary of the invention
The technical problem that (one) will solve
For the deficiency that above-mentioned prior art exists, it is a kind of with the nano electron device of nanocrystalline material as the coulomb island that one object of the present invention is to provide, and to simplify device architecture, the raising reliability reaches the compatibility with traditional cmos process.
It is a kind of with the manufacture method of nanocrystalline material as the nano electron device on coulomb island that another object of the present invention is to provide, to simplify manufacture craft, reduce cost of manufacture and to improve make efficiency.
(2) technical scheme
Be an aspect that achieves the above object, the invention provides a kind of with the nano electron device of nanocrystalline material as the coulomb island, this nano electron device is made of source, leakage, grid, coulomb island, gate medium, utilize a pair of nano-electrode on the substrate as source and drain electrode, utilize the nanocrystalline conduct coulomb island between the nano-electrode, utilize the dielectric of growing on the nano-electrode as gate medium, utilize the electrode of growing on the dielectric as gate electrode.
In the such scheme, described substrate is smooth, clean dielectric substrate, comprises SiO
2, Si
3N
4, Al
2O
3, a kind of in MgO, CaO and the polyimides, perhaps be smooth, clean intrinsic semiconductor substrate, comprise a kind of in Si, Ge, GaAs, GaN, GaSb, GaP, AlAs, InAs, InP, InSb, SiC, ZnO, ZnS, CdS, CdTe and the diamond.
In the such scheme, the spacing of described nano-electrode is 5 nanometer to 100 nanometers, and the thickness of nano-electrode is 20 nanometer to 50 nanometers, and the material of nano-electrode is a kind of among Al, Pt, Au, Ag, W, Ti, Cr and the ITO.
In the such scheme, described nanocrystalline material is a kind of among Si, Ni, Cu, Al, Pt, Au, Ag, W, Ti, Cr and the WTi, and nanocrystalline diameter is 2 to 20 nanometers.
In the such scheme, the dielectric of described growth is SiO
2, Si
3N
4, HfO
2, a kind of among HfAlO and the HfSiON, thickness is 5 to 20 nanometers.
In the such scheme, described gate material is polysilicon, TaN and IrO
2In a kind of, the thickness of gate electrode is 20 to 100 nanometers.
Be another aspect that achieves the above object, the invention provides a kind of nanocrystalline material of using as the manufacture method of the nano electron device on coulomb island, the method comprises:
Prepare metal nano electrode in dielectric substrate;
Growth one deck nano thin-film between metal nano electrode, then annealing forms nanocrystalline material;
At coulomb island growth dielectric as gate medium, at the dielectric gate electrode of growing.
In the such scheme, described in the step of dielectric substrate preparation metal nano electrode, be to adopt electron beam lithography, metal deposit and stripping technology to realize.
In the such scheme, described between metal nano electrode in the step of growth one deck nano thin-film, be a kind of in Si, Ni that to utilize a kind of a layer thickness of growing in sputter, evaporation, the Atomic layer deposition method between nano-electrode be 1 nanometer to 3 nanometer, Cu, Al, Pt, Au, Ag, W, Ti, Cr, the WTi film.
In the such scheme, described annealing forms nanocrystalline material, is to anneal to form nanocrystalline material in 10 seconds to 30 seconds in nitrogen under 600 ℃ to 1300 ℃ temperature.
(3) beneficial effect
Can find out from technique scheme, the present invention has following beneficial effect:
1, utilizes the present invention, as source and drain electrode, utilize the nanocrystalline as a coulomb island of growth by a pair of nano-electrode, thereby make device architecture simple, good with the traditional cmos process compatibility.
2, utilize making provided by the invention with the method for nanocrystalline material as the nano electron device on coulomb island, greatly simplified manufacture craft, reduced cost of manufacture, improved make efficiency, be very beneficial for extensive promotion and application of the present invention.
3, the electron beam lithography of the present invention's employing is a kind of effective nanoprocessing means, has nano level resolution, and particularly on the substrate of atomic number less, resolution is higher.The present invention utilizes the spacing of the nano-electrode that electron beam lithography prepares to have nanoscale, and I reaches 5 nanometers, is very suitable for making nano electron device.
4, the present invention adopt growth nano-crystalline granule as the coulomb island, diameter is very little, minimum can reach 2 nanometers, thereby has improved the working temperature of nano electron device.
Description of drawings
Fig. 1 is the structural representation on coulomb island in the prior art;
Fig. 2 is provided by the invention with the manufacture method flow chart of nanocrystalline material as the nano electron device on coulomb island;
Fig. 3 to Figure 11 makes of the process chart of nanocrystalline material as the nano electron device on coulomb island according to the embodiment of the invention.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail.
As shown in Figure 2, Fig. 2 is provided by the invention with the manufacture method flow chart of nanocrystalline material as the nano electron device on coulomb island, and the method comprises:
Step 201: adopt electron beam lithography, metal deposit and stripping technology to prepare metal nano electrode in dielectric substrate;
Step 202: a kind of in Si, the Ni that to utilize a kind of a layer thickness of growing in sputter, evaporation, the Atomic layer deposition method between nano-electrode be 1 nanometer to 3 nanometer, Cu, Al, Pt, Au, Ag, W, Ti, Cr, the WTi film, then in nitrogen under 600 ℃ to 1300 ℃ temperature annealing formed nanocrystalline material in 10 seconds to 30 seconds;
Step 203: at coulomb island growth dielectric as gate medium, at the dielectric gate electrode of growing.
Fig. 3 to Figure 11 shows according to the embodiment of the invention and makes of the process chart of nanocrystalline material as the nano electron device on coulomb island.Need to prove, the invention provides preferred embodiment, but should not be considered to the embodiment that only limits to again set forth.In the drawings, amplify layer and regional thickness for clear, but should not be considered to strictly react the proportionate relationship of physical dimension as schematic diagram.
As shown in Figure 3, applying a layer thickness with sol evenning machine on the dielectric substrate 1 of surfacing, cleaning is the high-resolution positive electronic corrosion-resistant 2 of 100 nanometer to 500 nanometers, such as PMMA, ZEP520, KRS, UV-III, P (SI-CMS) etc.Then adopt baking oven or hot plate to carry out the front baking of certain hour and uniform temperature to the good electronic corrosion-resistant 2 of above-mentioned coating.
As shown in Figure 4, e-beam direct-writing exposure being carried out in zone 3 and the zone 4 of positive corrosion-resisting agent 2, does not expose in zone 5,6.The interval in zone 3 and zone 4 is that unexposed regional 5 width is 5 to 100 nanometers.The accelerating voltage of electron beam exposure is 50 or 100KeV, and electronic beam current is less than or equal to 500pA.Also need after before development, taking after the exposure, to dry by the fire step when adopting these two kinds chemistry of KRS, UV-III to amplify resist.
As shown in Figure 5, the positive corrosion-resisting agent that exposed is developed and photographic fixing, remove the electronic corrosion-resistant of exposure area, be formed for the Etching mask 9,10 of deposition of electrode material film.Obtain groove pattern 7,8 after the development.
As shown in Figure 6, adopt the electrode material membrane 11,12,13 of the conductions such as evaporation or sputtering method depositing Al, Pt, Au, Ag, W, Ti, Cr, ITO, electrode film 11,12,13 thickness are lower than electronic corrosion- resistant mask 9,10 thickness, electrode film is discontinuous, a part (13) is deposited on the electronic corrosion- resistant mask 9,10, another part (11,12) is deposited on the dielectric 1, forms required nano-electrode 11,12.
As shown in Figure 7, adopt that acetone soaks, the ultrasonic Etching mask 9,10 and the metal electrode film 13 of top of peeling off, the interval of finishing on dielectric 1 only is the nano-electrode 11 of 5 nanometer to 100 nanometers, 12 preparation.Fig. 8 is nano-electrode 11,12 top view, and the width of eletrode tip is 5 nanometer to 100 nanometers.
As shown in Figure 9, utilizing the method growth a layer thickness such as sputter, evaporation, ald is Si, Ni, Cu, Al, Pt, Au, Ag, W, Ti, Cr, the WTi film of 1 nanometer to 3 nanometer, and to the film of above-mentioned growth in nitrogen under 600 ℃ to 1300 ℃ temperature annealing formed nanocrystalline material 14 in 10 seconds to 30 seconds, wherein the nano-crystalline granule between nano-electrode 11,12 15 is as a coulomb island.
As shown in figure 10, utilize the methods such as chemical vapour deposition (CVD), sputter, the ald SiO that on coulomb island 15, grows
2, Si
3N
4, HfO
2, the insulated gate media 16 such as HfAlO, HfSiON, the thickness of gate medium is 5 nanometer to 20 nanometers.
As shown in figure 11, utilize method growing polycrystalline silicon, TaN, IrO on insulated gate medium 16 such as chemical vapour deposition (CVD), sputter, ald
2 Deng gate electrode 17, the thickness of gate electrode 17 is 20 nanometer to 100 nanometers.
The below further specifies detailed process method of the present invention and step in conjunction with Fig. 3 to Figure 11 again to use ZEP520 positive electronic corrosion-resistant, evaporation Cr/Au double-level-metal electrode film as example, wherein:
As shown in Figure 3, with sol evenning machine coating individual layer ZEP520 positive electronic corrosion-resistant 2, the coating rotating speed is 2000rpm on silicon dioxide insulator substrate 1, and the coating time is 60 seconds, and resist thickness is 485 nanometers.Then use baking oven 180 ℃ of lower front bakings 20 minutes.
As shown in Figure 4, e-beam direct-writing exposure being carried out in zone 3 and the zone 4 of ZEP520 resist 2, does not expose in zone 5,6.The width in zone 3 and zone 4 is 350 nanometers, and the interval in zone 3 and zone 4 is that unexposed regional 5 width is 50 nanometers.Electron beam exposure can adopt the JEOLJBX-6300FS electron-beam lithography system, and accelerating voltage is 100KeV, and electronic beam current is 500pA, and exposure dose is 170 μ C/cm
2
As shown in Figure 5, use pentyl acetate developing liquid developing 2 minutes, use immediately methyl iso-butyl ketone (MIBK) (MIBK) fixing solution photographic fixing 15 seconds, form the Etching mask 9,10 of electrode material membrane deposit.Obtain groove pattern 7,8 after development, the photographic fixing.
As shown in Figure 6, evaporate the Cr/Au metal electrode material film 11,12,13 of 50 nanometer thickness, wherein the Au layer is thicker, mainly utilizes its good conductivity; The Cr layer is thinner, rises to strengthen Au and SiO
2The adhering effect of medium.The Cr/Au gross thickness is lower than ZEP520 Etching mask 9,10 thickness, and the Cr/Au film is discontinuous, and a part of Cr/Au film (13) is deposited on the ZEP520 Etching mask 9,10, and another part is deposited on SiO
2On the substrate 1, form required Cr/Au nano-electrode 11,12.
As shown in Figure 7, adopt acetone soak, ultrasonic peel off ZEP520 Etching mask 9,10 and on Cr/Au metal electrode film 13, finish the Cr/Au nano-electrode 11 on dielectric 1,12 preparation.Fig. 8 is Cr/Au nano-electrode 11,12 top view, and the width of eletrode tip is less than 100 nanometers, and the interval of nano-electrode is less than 100 nanometers.
As shown in Figure 9, utilizing electron beam evaporation method deposition a layer thickness is the Au film of 2 nanometers, and the Au film of growth was annealed 10 seconds under 900 ℃ of temperature in nitrogen, at SiO
2The upper Au nanocrystalline material 14 that forms in dielectric substrate 1 surface, wherein the Au nano-crystalline granule between nano-electrode 11,12 15 is as a coulomb island.
As shown in figure 10, utilize the Atomic layer deposition method one deck HfSiON insulated gate medium 16 of growing on coulomb island 15, the thickness of gate medium 16 is 10 nanometers.
As shown in figure 11, utilize the sputtering method TaN gate electrode 17 of growing on gate medium 16, the thickness of gate electrode 17 is 60 nanometers.
Above-described specific embodiment; purpose of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the above only is specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any modification of making, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (5)
1. one kind with the nano electron device of nanocrystalline material as the coulomb island, it is characterized in that, this nano electron device is made of source, leakage, grid, coulomb island, gate medium, utilize a pair of nano-electrode on the substrate as source and drain electrode, utilize the nanocrystalline conduct coulomb island between the nano-electrode, utilize the dielectric of growing on the nano-electrode as gate medium, utilize the electrode of growing on the dielectric as gate electrode; Wherein, described nanocrystalline material is a kind of among Si, Ni, Cu, Al, Pt, Au, Ag, W, Ti, Cr and the WTi; The diameter on coulomb island reaches 2 nanometers, has improved the working temperature of nano electron device.
2. the nanocrystalline material of using according to claim 1 is characterized in that as the nano electron device on coulomb island, and described substrate is smooth, clean dielectric substrate, comprises SiO
2, Si
3N
4, Al
2O
3, a kind of in MgO, CaO, the polyimides, perhaps be smooth, clean intrinsic semiconductor substrate, comprise a kind of in Si, Ge, GaAs, GaN, GaSb, GaP, AlAs, InAs, InP, InSb, SiC, ZnO, ZnS, CdS, CdTe, the diamond.
3. according to claim 1 with the nano electron device of nanocrystalline material as the coulomb island, it is characterized in that, the spacing of described nano-electrode is 5 nanometer to 100 nanometers, the thickness of nano-electrode is 20 nanometer to 50 nanometers, and the material of nano-electrode is a kind of among Al, Pt, Au, Ag, W, Ti, Cr and the ITO.
4. the nanocrystalline material of using according to claim 1 is characterized in that as the nano electron device on coulomb island, and the dielectric of described growth is SiO
2, Si
3N
4, HfO
2, a kind of among HfAlO and the HfSiON, thickness is 5 to 20 nanometers.
5. the nanocrystalline material of using according to claim 1 is characterized in that as the nano electron device on coulomb island, and described gate material is polysilicon, TaN and IrO
2In a kind of, the thickness of gate electrode is 20 to 100 nanometers.
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| CN102208340B (en) * | 2011-05-23 | 2014-04-23 | 中国科学院半导体研究所 | Method for making self-support gallium nitride substrate |
| CN102956759B (en) * | 2011-08-22 | 2015-04-01 | 山东浪潮华光光电子有限公司 | Method for preparing ITO (indium tin oxide) patterns by stripping |
Citations (5)
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|---|---|---|---|---|
| US7098092B2 (en) * | 2002-12-10 | 2006-08-29 | Electronics And Telecommunications Research Institute | Single electron device, method of manufacturing the same, and method of simultaneously manufacturing single electron device and MOS transistor |
| CN1979768A (en) * | 2005-12-08 | 2007-06-13 | 中国科学院微电子研究所 | Method for adopting positive electronic corrosion-resistant to prepare metal nano electrode |
| CN101122006A (en) * | 2006-08-10 | 2008-02-13 | 中国科学院微电子研究所 | Method for preparing metal nano-crystal thin film |
| US7419849B2 (en) * | 2006-02-06 | 2008-09-02 | Matsushita Electric Industrial Co., Ltd. | Method for producing single electron semiconductor element |
| CN101542700A (en) * | 2007-09-14 | 2009-09-23 | 忠北大学校产学协力团 | Room temperature-operating single-electron device and the fabrication method thereof |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7098092B2 (en) * | 2002-12-10 | 2006-08-29 | Electronics And Telecommunications Research Institute | Single electron device, method of manufacturing the same, and method of simultaneously manufacturing single electron device and MOS transistor |
| CN1979768A (en) * | 2005-12-08 | 2007-06-13 | 中国科学院微电子研究所 | Method for adopting positive electronic corrosion-resistant to prepare metal nano electrode |
| US7419849B2 (en) * | 2006-02-06 | 2008-09-02 | Matsushita Electric Industrial Co., Ltd. | Method for producing single electron semiconductor element |
| CN101122006A (en) * | 2006-08-10 | 2008-02-13 | 中国科学院微电子研究所 | Method for preparing metal nano-crystal thin film |
| CN101542700A (en) * | 2007-09-14 | 2009-09-23 | 忠北大学校产学协力团 | Room temperature-operating single-electron device and the fabrication method thereof |
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