WO2023082652A1 - Thin film transistor memory and preparation method therefor - Google Patents

Thin film transistor memory and preparation method therefor Download PDF

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Publication number
WO2023082652A1
WO2023082652A1 PCT/CN2022/101236 CN2022101236W WO2023082652A1 WO 2023082652 A1 WO2023082652 A1 WO 2023082652A1 CN 2022101236 W CN2022101236 W CN 2022101236W WO 2023082652 A1 WO2023082652 A1 WO 2023082652A1
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gate
floating gate
channel
gate structure
thin film
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PCT/CN2022/101236
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French (fr)
Chinese (zh)
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朱宝
尹睿
张卫
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上海集成电路制造创新中心有限公司
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Publication of WO2023082652A1 publication Critical patent/WO2023082652A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324—Gate electrodes for transistors with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7841—Field effect transistors with field effect produced by an insulated gate with floating body, e.g. programmable transistors

Definitions

  • the invention relates to the technical field of semiconductor storage, in particular to a thin film transistor storage and a preparation method thereof.
  • Non-volatile memory is an indispensable component in modern electronic devices. At present, non-volatile memory on the market is still dominated by silicon-based devices. However, due to the complex manufacturing process of traditional floating gate non-volatile memories based on single-crystal silicon substrates, usually involving high-temperature processes, it is difficult to manufacture embedded non-volatile memories on glass substrates, resulting in their Restricted when integrated into display panels.
  • a non-volatile memory based on a thin-film transistor (TFT) structure has attracted widespread attention.
  • This memory can not only be fabricated on glass or a flexible substrate, but its manufacturing process can be well compared with the traditional TFT manufacturing process.
  • TFT thin-film transistor
  • the movement of charges between the channel and the trapping layer is still realized through the tunneling layer.
  • the thickness of the tunneling layer is continuously reduced, so that the charges trapped by the trapping layer are easily returned to the tunneling layer, which reduces the charge retention characteristics.
  • wide bandgap semiconductor materials or metal materials with higher work functions are usually used.
  • the use of these new trapping layer materials in turn makes it difficult to erase the charges trapped by the trapping layer.
  • the semi-floating gate TFT memory of the invention comprises: an L-shaped back gate; an L-shaped barrier layer on the bottom of the back gate, whose top is level with the top of the back gate; an L-shaped floating gate on the bottom of the barrier layer, whose top is aligned with the top of the back gate.
  • the top of the blocking layer is level; the tunneling layer at the bottom of the floating gate, the upper surface of which is level with the top of the floating gate; the channel on the upper surfaces of the tunneling layer and the floating gate; the source on the channel electrode and drain; the floating gate and the channel are semiconductor materials, and have opposite conductivity types, and the floating gate, the channel, the barrier layer and the back gate form a gate-controlled diode.
  • the writing and erasing of data in the semi-floating gate TFT memory of the invention is all realized through gate-controlled diodes, which can speed up data erasing and writing.
  • this invention is a semi-floating gate memory, and part of the floating gate is directly in contact with the channel, so that the electrons trapped in the floating gate can easily flow back into the channel, thereby affecting the stability and reliability of charge storage.
  • the object of the present invention is to provide a thin film transistor memory and its preparation method, to speed up the electronic erasing speed, reduce the electronic erasing voltage, thereby reducing power consumption, and the thin film transistor memory is not easy to use compared with the semi-floating gate thin film transistor memory. Leakage, greater reliability.
  • the thin film transistor memory of the present invention includes:
  • the back gate includes a bottom gate structure and a side gate structure, and the side gate structure is arranged on a part of the upper surface of the bottom gate structure to form an L-shaped structure;
  • a barrier layer disposed on the upper surface of the bottom gate structure
  • the floating gate is arranged on the upper surface of the barrier layer, and the floating gate is separated from the back gate, and the upper surface of the floating gate is flat with the upper surface of the side gate structure;
  • a tunneling layer disposed on the upper surface of the floating gate
  • the source and the drain are arranged on the upper surface of the channel.
  • the back gate includes a bottom gate structure and a side gate structure
  • the side gate structure is arranged on a part of the upper surface of the bottom gate structure to form an L-shaped structure
  • the barrier layer is provided On the upper surface of the bottom gate structure
  • the floating gate is arranged on the upper surface of the barrier layer, and the floating gate is separated from the back gate, and the upper surface of the floating gate is separated from the upper surface of the side gate structure.
  • the surfaces are flat, the tunneling layer is arranged on the upper surface of the floating gate, the channel is arranged on the upper surface of the tunneling layer, the channel is not in contact with the floating gate, and the floating gate and the floating gate
  • the channel has opposite conductivity types, and the source and drain are arranged on the upper surface of the channel, so that the energy band of the floating gate of the thin film transistor memory can be adjusted through the side gate structure, so as to accelerate electron erasure.
  • the erasing speed reduces the electronic erasing voltage, thereby reducing power consumption, and because the channel and the floating gate are not in contact with each other, the thin film transistor memory is not easy to leak compared with the semi-floating gate thin film transistor memory, and the reliability is higher.
  • the valence band of the floating gate will be located above the conduction band of the channel, at this time, the electrons located in the valence band of the floating gate will tunnel through the tunneling layer to the channel
  • the conduction band of the channel that is, electrons will flow back to the channel from the floating gate, and the memory will return to its original state.
  • the inflow and outflow of electrons in the floating gate realizes two states of electronic writing and erasing.
  • the barrier layer includes a bottom barrier structure and a side barrier structure, the side barrier structure is arranged on a part of the upper surface of the bottom barrier structure to form an L-shaped structure, and the side barrier structure is arranged on the Between the floating gate and the side gate structure.
  • the beneficial effect is that the floating gate is separated from the side gate structure of the back gate by the side barrier structure, which is more conducive to forming an isolation between the floating gate and the back gate. , so as to ensure that the electrons in the valence band of the floating gate will not flow to the back gate and cause electric leakage.
  • the two symmetrical side surfaces of the side barrier structure respectively bear against the floating gate and the side gate structure, and the upper surface of the side barrier structure is flush with the upper surface of the side gate structure .
  • the beneficial effect is that: while it is more conducive to forming an isolation between the floating gate and the back gate, it is also convenient to prepare the back gate and the barrier layer of the L-shaped structure.
  • the first side surface of the channel close to the side gate structure and the second side surface of the tunneling layer close to the side gate structure are both connected to the third side surface of the floating gate close to the side gate structure.
  • the side surfaces are set flat. The beneficial effect is that it is easy to manufacture, and ensures that the channel and the floating gate are arranged without contact, thus avoiding the risk of electric leakage.
  • both the floating gate and the channel are made of semiconductor material, the material of the channel is n-type semiconductor material, and the material of the floating gate is p-type semiconductor material.
  • the material of the floating gate is any one of NiO, Cu 2 O, SnO, AlSnO, p-type polysilicon semiconductor material, Pt, Pd, Ni and Au.
  • the material of the channel is any one of IGZO, ZnO, In 2 O 3 , Ga 2 O 3 and n-type polysilicon semiconductor materials.
  • the present invention also provides a method for preparing a thin film transistor memory, comprising the steps of:
  • S1 forming a bottom gate structure and a side gate structure, and disposing the side gate structure on a part of the upper surface of the bottom gate structure to form a back gate of an L-shaped structure;
  • S3 sequentially forming a tunneling layer and a channel on the upper surface of the floating gate, making the channel not in contact with the floating gate, and making the floating gate and the channel have opposite conductivity types;
  • the beneficial effect of the preparation method of the thin film transistor memory of the present invention is that: through S1: forming a bottom gate structure and a side gate structure, and setting the side gate structure on a part of the upper surface of the bottom gate structure to form an L-shaped
  • the back gate of the structure S2: a barrier layer and a floating gate are sequentially formed on the upper surface of the bottom gate structure, so that the floating gate is arranged on the upper surface of the barrier layer and separated from the back gate, so that the The upper surface of the floating gate is flush with the upper surface of the side gate structure, S3: sequentially forming a tunneling layer and a channel on the upper surface of the floating gate so that the channel is not in contact with the floating gate, And make the floating gate and the channel have opposite conductivity types, S4: form a source and a drain on the upper surface of the channel, so that the floating gate of the thin film transistor memory can be controlled by the side gate structure.
  • the energy band of the gate is adjusted to speed up the electronic erasing speed and reduce the electronic erasing voltage, thereby reducing power consumption, and because the channel and the floating gate are not in contact with each other, the thin film transistor memory is relatively
  • the thin film transistor memory is not easy to leak, and the reliability is stronger; that is, when the write operation is performed, electrons tunnel from the channel through the tunneling layer and flow into the floating gate to cause a change in the threshold voltage of the memory.
  • the valence band of the floating gate will be located above the conduction band of the channel, and at this time, the electrons located in the valence band of the floating gate will tunnel The tunneling layer reaches the conduction band of the channel, that is, electrons will flow back to the channel from the floating gate, and the memory will return to its original state.
  • the inflow and outflow of electrons in the floating gate realizes the There are two states of writing and erasing; moreover, the preparation method is simple and convenient, and the process is fully compatible with the traditional TFT process.
  • the step of sequentially forming a barrier layer and a floating gate on the upper surface of the bottom gate structure in the step S2 includes:
  • the step S22 further includes the step of forming an L-shaped barrier layer on the upper surface of the bottom gate structure:
  • the step of sequentially forming a tunneling layer and a channel on the upper surface of the floating gate in the step S3 includes:
  • S31 Deposit a tunneling layer material and a channel material on the upper surface of the floating gate, the upper surface of the side barrier structure, and the upper surface of the side gate structure;
  • FIG. 1 is a cross-sectional view of a thin film transistor memory according to a first embodiment of the present invention
  • FIG. 2 is a cross-sectional view of a thin film transistor memory according to a second embodiment of the present invention.
  • FIG. 3 is a cross-sectional view of a thin film transistor memory according to a third embodiment of the present invention.
  • FIG. 4 is a cross-sectional view of a thin film transistor memory according to a fourth embodiment of the present invention.
  • FIG. 5 is a cross-sectional view of a thin film transistor memory according to a fifth embodiment of the present invention.
  • FIG. 6 is a cross-sectional view of a thin film transistor memory according to a sixth embodiment of the present invention.
  • FIG. 7 is a flowchart of a method for manufacturing a thin film transistor memory according to an embodiment of the present invention.
  • FIG. 8 is a cross-sectional view of a back gate in an embodiment of the present invention.
  • FIG. 9 is a cross-sectional view of a structure formed after deposition treatment is performed on the upper surface of the back gate shown in FIG. 8;
  • FIG. 10 is a cross-sectional view of the structure shown in FIG. 9 after etching to form a barrier layer
  • FIG. 11 is a cross-sectional view of a structure formed after deposition treatment is performed on the upper surface of the barrier layer shown in FIG. 10 in some embodiments of the present invention.
  • FIG. 12 is a cross-sectional view of the structure shown in FIG. 11 after etching to form a floating gate
  • FIG. 13 is a cross-sectional view of a structure formed after deposition treatment is performed on the upper surface of the barrier layer shown in FIG. 10 in other embodiments of the present invention.
  • FIG. 14 is a cross-sectional view of the structure after depositing the upper surface of the floating gate shown in FIG. 12 to form an initial tunneling layer;
  • FIG. 15 is a cross-sectional view of the structure after depositing the upper surface of the initial tunneling layer shown in FIG. 14 to form an initial channel;
  • FIG. 16 is a cross-sectional view of the structure after etching the structure shown in FIG. 15 to form a tunneling layer and a channel.
  • the embodiment of the present invention provides a thin film transistor memory and its preparation method, so as to speed up the electronic erasing speed and reduce the electronic erasing voltage, so as to reduce power consumption, and the thin film transistor memory is relatively Semi-floating gate thin film transistor memory is not easy to leak and has stronger reliability.
  • FIG. 1 is a cross-sectional view of a thin film transistor memory according to a first embodiment of the present invention.
  • the thin film transistor memory includes a back gate 100, a barrier layer 200, a floating gate 300, a tunneling layer 400, a channel 500, a source 600 and a drain 700;
  • the back gate 100 Including a bottom gate structure 101 and a side gate structure 102, the side gate structure 102 is arranged on a part of the upper surface of the bottom gate structure 101 to form an L-shaped structure;
  • the barrier layer 200 is arranged on the bottom gate structure 101 surface;
  • the floating gate 300 is disposed on the upper surface of the barrier layer 200, and the floating gate 300 is separated from the back gate 100, and the upper surface of the floating gate 300 is connected to the upper surface of the side gate structure 102
  • the surface is flat;
  • the tunneling layer 400 is arranged on the upper surface of the floating gate 300;
  • the channel 500 is arranged on the upper surface of the tunneling layer 400, and the channel 500 and the floating gate 300 are not Contacts are provided, and the floating gate 300 and the channel 500 have opposite conductivity types;
  • the thin film transistor memory (not shown in the figure) It is possible to regulate the energy band of the floating gate 300 of the thin film transistor memory (not shown in the figure) through the side gate structure 102, so as to speed up the electronic erasing speed and reduce the electronic erasing voltage, thereby reducing power consumption, and Because the channel 500 is not in contact with the floating gate 300 , the thin film transistor memory (not shown in the figure) is less likely to leak than the semi-floating gate thin film transistor memory, and has stronger reliability.
  • the valence band of the floating gate 300 will be located above the conduction band of the channel 500, and the electrons located in the valence band of the floating gate 300 will tunnel through the The tunneling layer 400 reaches the conduction band of the channel 500, that is, electrons will flow back from the floating gate 300 to the channel 500, and the memory will return to its original state, and the inflow and outflow of electrons in the floating gate 300 will realize There are two states of electronic writing and erasing.
  • the barrier layer 200 includes a bottom barrier structure 201 and a side barrier structure 202, and the side barrier structure 202 is disposed on a part of the upper surface of the bottom barrier structure 201 to form a L type structure, the side barrier structure 202 is disposed between the floating gate 300 and the side gate structure 102 .
  • the side barrier structure 202 is disposed between the side surface of the floating gate 300 and the side surface of the side gate structure 102, so that the floating gate 300 and the side gate of the back gate 100
  • the structures 102 are separated by the side barrier structure 202
  • the bottom barrier structure 201 is arranged between the lower surface of the floating gate 300 and the upper surface of the bottom gate structure 101, so that the floating gate 300 and the upper surface of the bottom gate structure 101 are separated.
  • the bottom gate structures 101 of the back gate 100 are separated by the bottom barrier structure 201, which is conducive to forming an isolation between the floating gate and the back gate, so as to ensure that the valence band of the floating gate is avoided.
  • the electrons on the upper gate will flow to the back gate and cause electric leakage to occur.
  • the two symmetrical side surfaces of the side barrier structure 202 are held against the floating gate 300 and the side gate structure 102 respectively, and the upper surface of the side barrier structure 202
  • the surface is flat with the upper surface of the side gate structure 102, that is, the upper surface of the side gate structure 102, the upper surface of the side barrier structure 202 and the upper surface of the floating gate 300 are arranged on the same level. While it is beneficial to form an isolation between the floating gate 300 and the back gate 100 , it is also convenient to prepare the L-shaped structure of the back gate 100 and the L-shaped barrier layer 200 .
  • the first side surface 501 of the channel 500 close to the side gate structure 102 and the second side surface 401 of the tunneling layer 400 close to the side gate structure 102 are both
  • the third side surface 301 of the floating gate 300 close to the side gate structure 102 is arranged flush with the third side surface 301 of the side gate structure 102 , which is convenient for manufacture and ensures that the channel 500 is not in contact with the floating gate 300 , thus avoiding the risk of electric leakage.
  • the upper surface of the side barrier structure is not arranged flush with the upper surface of the side gate structure.
  • the upper surface of the side barrier structure is higher than the upper surface of the side gate structure.
  • the upper surface of the side barrier structure is lower than the upper surface of the side gate structure.
  • FIG. 2 is a cross-sectional view of a thin film transistor memory according to a second embodiment of the present invention.
  • the barrier layer 200 in the second thin film transistor memory shown in FIG. 2 has an L-shaped structure, and the barrier layer 200 includes a bottom barrier structure 201 and a side barrier structure. 202, and the difference between the second type of thin film transistor memory shown in FIG. 2 and the first type of thin film transistor memory shown in FIG. 1 is that the upper surface of the side barrier structure 202 in the second type of thin film transistor memory is higher than the upper surface of the side gate structure 102 , and the upper surface of the side barrier structure 202 is level with the upper surface of the channel 500 , as shown in FIG. 2 .
  • FIG. 3 is a cross-sectional view of a thin film transistor memory according to a third embodiment of the present invention.
  • the barrier layer 200 in the third thin film transistor memory shown in FIG. structure 202 and the difference between the third type of thin film transistor memory shown in FIG. 3 and the first type of thin film transistor memory shown in FIG.
  • the surface is higher than the upper surface of the side gate structure 102 , and the upper surface of the side barrier structure 202 is level with the upper surface of the tunneling layer 400 , as shown in FIG. 3 .
  • FIG. 4 is a cross-sectional view of a thin film transistor memory according to a fourth embodiment of the present invention.
  • the barrier layer 200 in the fourth thin film transistor memory shown in FIG. structure 202 and the difference between the fourth type of thin film transistor memory shown in FIG. 4 and the first type of thin film transistor memory shown in FIG.
  • the surface is lower than the upper surface of the side gate structure 102, that is, the floating gate 300 is separated from part of the side surface of the side gate structure 102 by the side barrier structure 202, and the floating gate 300 is separated from the side gate structure 102.
  • the side surfaces of the remaining part of the side gate structure 102 are separated by gaps.
  • FIG. 5 is a cross-sectional view of a thin film transistor memory according to a fifth embodiment of the present invention.
  • the difference between the fifth type of thin film transistor memory shown in FIG. 5 and the first type of thin film transistor memory shown in FIG. 1 is that the barrier layer in the fifth type of thin film transistor memory has a rectangular structure , referring to FIG. 5, the first rectangular barrier layer 210 is disposed between the lower surface of the floating gate 300 and the upper surface of the bottom gate structure 101, and the first rectangular barrier layer 210 is close to the side gate
  • the fourth side surface 211 of the structure 102 is arranged on the same level as the third side surface 301 of the floating gate 300 close to the side gate structure 102, and the floating gate 300 and the first rectangular barrier layer 210 are aligned with the side gate structure 102 are separated by gaps.
  • FIG. 6 is a cross-sectional view of a thin film transistor memory according to a sixth embodiment of the present invention.
  • the difference between the sixth type of thin film transistor memory shown in FIG. 6 and the first type of thin film transistor memory shown in FIG. 1 is that the barrier layer in the sixth type of thin film transistor memory has a rectangular structure , referring to FIG. 6, the second rectangular barrier layer 220 is disposed between the lower surface of the floating gate 300 and the upper surface of the bottom gate structure 101, and the second rectangular barrier layer 220 is close to the side gate
  • the fifth side surface 221 of the structure 102 is arranged against the side surface of the side gate structure 102 , and the floating gate 300 is separated from the side gate structure 102 by a gap.
  • both the floating gate and the channel are made of semiconductor material, the material of the channel is n-type semiconductor material, and the material of the floating gate is p-type semiconductor material.
  • the material of the floating gate is any one of NiO, Cu 2 O, SnO, AlSnO, p-type polysilicon semiconductor material, Pt, Pd, Ni and Au.
  • the p-type polysilicon semiconductor material is a p-type low-temperature polysilicon semiconductor material.
  • the material of the channel is any one of IGZO, ZnO, In 2 O 3 , Ga 2 O 3 and n-type polysilicon semiconductor material, wherein the n-type polysilicon semiconductor material is n type low temperature polysilicon semiconductor material.
  • the back gate is the substrate of the thin film transistor memory, and the substrate is any one of a low-resistance silicon substrate, an ITO substrate, and a flexible substrate covered with a conductive film.
  • ITO is an N-type oxide semiconductor, that is, an indium tin oxide semiconductor transparent conductive film.
  • the material of the barrier layer is at least one of Al 2 O 3 , SiO 2 , HfO 2 , ZrO 2 , Ta 2 O 5 , TiO 2 , La 2 O 3 , and HfZrO 4 , namely
  • the barrier layer can be any one of the Al 2 O 3 , SiO 2 , HfO 2 , ZrO 2 , Ta 2 O 5 , TiO 2 , La 2 O 3 , HfZrO 4 , or it can be the Al 2 A stack of at least two compositions of O 3 , SiO 2 , HfO 2 , ZrO 2 , Ta 2 O 5 , TiO 2 , La 2 O 3 , and HfZrO 4 .
  • the material of the tunneling layer is at least one of Al 2 O 3 , SiO 2 , HfO 2 , ZrO 2 , Ta 2 O 5 , TiO 2 , La 2 O 3 , and HfZrO 4 , That is, the tunneling layer can be any one of Al 2 O 3 , SiO 2 , HfO 2 , ZrO 2 , Ta 2 O 5 , TiO 2 , La 2 O 3 , HfZrO 4 , or it can be the A stack of at least two compositions of Al 2 O 3 , SiO 2 , HfO 2 , ZrO 2 , Ta 2 O 5 , TiO 2 , La 2 O 3 , and HfZrO 4 .
  • the material of the source electrode and the drain electrode is any one of Au/Ti stack, Au/Cr stack, and TiAlNiAu.
  • the Au/Ti stack is formed by stacking Au material and Ti material
  • the Au/Cr stack is formed by stacking Au material and Cr material.
  • FIG. 7 is a flowchart of a manufacturing method of a thin film transistor memory according to an embodiment of the present invention.
  • the preparation method of the thin film transistor memory includes the steps of:
  • S1 forming a bottom gate structure and a side gate structure, and disposing the side gate structure on a part of the upper surface of the bottom gate structure to form a back gate of an L-shaped structure;
  • the preparation method of the thin film transistor memory in the embodiment of the present invention is simple and convenient, the process is fully compatible with the traditional TFT process, and the energy band of the floating gate of the thin film transistor memory can be adjusted through the side gate structure, To speed up the electronic erasing speed, reduce the electronic erasing voltage, thereby reducing power consumption, and because the channel and the floating gate are not in contact with each other, the thin film transistor memory is not easy to leak compared to the semi-floating gate thin film transistor memory , the reliability is stronger.
  • FIG. 8 is a cross-sectional view of a back gate in an embodiment of the present invention.
  • a bottom gate structure and a side gate structure are formed, and the side gate structure is arranged on a part of the upper surface of the bottom gate structure to form a back gate of an L-shaped structure Specifically include:
  • S12 Spin-coat photoresist on the upper surface of the substrate, and form a pattern for defining a shape through a photolithography process including exposure and development;
  • the substrate is any one of a low-resistance silicon substrate, an ITO substrate, and a flexible substrate whose surface is covered with a conductive film;
  • the dry etching includes ion milling etching, plasma etching , reactive ion etching, laser ablation, and inductively coupled plasma etching.
  • the step of sequentially forming a barrier layer and a floating gate on the upper surface of the bottom gate structure in the step S2 includes:
  • S22 Remove the material of the barrier layer higher than the upper surface of the side gate structure through an etching process, so as to form an L-shaped barrier layer on the upper surface of the bottom gate structure, and make the side portions of the barrier layer
  • the upper surface of the barrier structure is flat with the upper surface of the side gate structure, which is more conducive to forming a partition between the floating gate and the back gate, and also facilitates the preparation of the L-shaped structure of the back gate and the barrier layer .
  • FIG. 9 is a cross-sectional view of the structure formed after depositing layer materials on the upper surface of the back gate shown in FIG. 8;
  • FIG. 10 is a cross-sectional view of the structure after etching the structure shown in FIG. 9 to form a barrier layer.
  • the specific steps of forming a barrier layer on the upper surface of the bottom gate structure in step S2 include:
  • An insulating medium is deposited on the upper surface of the back gate 100 to form an initial barrier layer 230, and the resulting structure is shown in FIG. 9;
  • the photoresist as a mask to form an L-shaped barrier layer 200 by dry etching or wet etching using an etchant solution, even if the barrier layer 200 includes a bottom barrier structure 201 and a side barrier structure 202
  • the side barrier structure 202 is arranged on a part of the upper surface of the bottom barrier structure 201 to form the L-shaped barrier layer 200, and the side barrier structure 202 and the side gate structure 102 are arranged against each other , the resulting structure is shown in Figure 10.
  • an Al 2 O 3 film is formed on the upper surface of the back gate 100 by atomic layer deposition as a barrier layer, but the present invention is not limited thereto, and the material of the barrier layer may also be Other suitable materials, such as SiO 2 , HfO 2 , ZrO 2 , Ta 2 O 5 , TiO 2 , La 2 O 3 , HfZrO 4 , or made of 2.
  • a stack of La 2 O 3 , HfZrO 4 materials, etc.; the method of depositing and forming the initial barrier layer 230 may also be chemical vapor deposition, physical vapor deposition, pulsed laser deposition, electron beam evaporation, etc.; the dry method Etching includes any one of ion milling etching, plasma etching, reactive ion etching, laser ablation, and inductively coupled plasma etching.
  • the step S22 further includes a step after forming an L-shaped barrier layer on the upper surface of the bottom gate structure:
  • Fig. 11 is a cross-sectional view of the structure formed after depositing the upper surface of the barrier layer shown in Fig. 10 in some embodiments of the present invention
  • Fig. 12 is a structure after etching the structure shown in Fig. 11 to form a floating gate cutaway view.
  • the specific steps of forming a floating gate after forming an L-shaped barrier layer on the upper surface of the bottom gate structure in the step S22 include:
  • a layer of p-type semiconductor is deposited on the upper surface of the barrier layer 200 and the upper surface of the side gate structure 102 as the initial floating gate 310, and the resulting structure is shown in FIG. 11 ;
  • the upper surface of the side barrier structure 202 and the part of the initial floating gate on the upper surface of the side gate structure 102 are etched by dry etching or wet etching using an etchant solution. 310, and part of the initial floating gate 310 higher than the upper surface of the side barrier structure 202, so that the upper surface of the obtained floating gate 300 is compatible with the upper surface of the side barrier structure 202 and the
  • the upper surface of the side gate structure 102 is flat, that is, the upper surface of the floating gate 300 , the upper surface of the side barrier structure 202 and the side gate structure 102 are on the same horizontal line, and the resulting structure is shown in FIG. 12 .
  • the upper surface of the initial floating gate 310 located on the upper surface of the bottom barrier structure 201 and the upper surface of the side barrier structure 202 and the upper surface of the side gate structure 102 The surface is flat. At this time, it is only necessary to etch and remove the part of the initial floating gate 310 that is higher than the upper surface of the side barrier structure 202 and the upper surface of the side gate structure 102 .
  • the initial floating gate 310 is deposited on the upper surface of the barrier layer 200 and the upper surface of the side gate structure 102 by atomic layer deposition using NiO as the floating gate material.
  • the floating gate material can also be other suitable materials, such as Cu 2 O, SnO, AlSnO, p-type low-temperature polysilicon semiconductor materials, Pt, Pd, Ni, Au metal materials, etc., deposited to form the
  • the method for initial floating gate 310 described above may also be chemical vapor deposition, physical vapor deposition, pulsed laser deposition, electron beam evaporation, and the like.
  • the dry etching includes any one of ion milling etching, plasma etching, reactive ion etching, laser ablation and inductively coupled plasma etching.
  • FIG. 13 is a cross-sectional view of a structure formed after deposition treatment is performed on the upper surface of the barrier layer shown in FIG. 10 in some other embodiments of the present invention.
  • the upper surface of the initial floating gate 310 located on the upper surface of the bottom barrier structure 201 is lower than the upper surface of the side barrier structure 202 and the side gate.
  • the upper surface of the structure 102 at this time, it is necessary to etch and remove the part of the initial floating gate 310 higher than the upper surface of the side barrier structure 202 and the upper surface of the side gate structure 102, and etch and remove the portion
  • the side barrier structure 202 and part of the side gate structure 102 are arranged so that the upper surface of the floating gate 300 , the upper surface of the side barrier structure 202 and the side gate structure 102 are at the same level.
  • the step of sequentially forming a tunneling layer and a channel on the upper surface of the floating gate in the step S3 includes:
  • S31 Depositing a tunneling layer material and a channel material on the upper surface of the floating gate, the upper surface of the side barrier structure, and the upper surface of the side gate structure;
  • FIG. 14 is a cross-sectional view of the structure after depositing the upper surface of the floating gate shown in Fig. 12 to form an initial tunneling layer;
  • Fig. 15 is depositing the upper surface of the initial tunneling layer shown in Fig. 14 to form an initial trench
  • FIG. 16 is a cross-sectional view of the structure after etching the structure shown in FIG. 15 to form a tunneling layer and a channel.
  • the specific steps of sequentially forming a tunneling layer and a channel on the upper surface of the floating gate in the step S3 include:
  • a layer of insulating medium is deposited on the upper surface of the floating gate 300, the upper surface of the side barrier structure 202 and the upper surface of the side gate structure 102 as the initial tunneling layer 410, and the resulting structure is shown in FIG. 14 Show;
  • a layer of n-type semiconductor is deposited on the upper surface of the initial tunneling layer 410 as the initial channel 510, and the resulting structure is shown in FIG. 15 ;
  • an Al 2 O 3 thin film is formed by atomic layer deposition as the initial tunneling layer, but the present invention is not limited thereto, and the tunneling layer can also be other suitable materials, such as SiO 2 , HfO 2 , ZrO 2 , Ta 2 O 5 , TiO 2 , La 2 O 3 , HfZrO 4 , or made of the SiO 2 , HfO 2 , ZrO 2 , Ta 2 O 5 , TiO 2 , La 2 O 3 , HfZrO 4 Material composition stacks, etc.
  • the deposition method for forming the initial tunneling layer may also be chemical vapor deposition, physical vapor deposition, pulsed laser deposition, electron beam evaporation, etc.
  • the IGZO thin film is formed as the initial channel by physical vapor deposition, but the present invention is not limited thereto, and the material of the channel may also be other suitable materials, such as ZnO, In 2 O 3 , Ga 2 O 3 or n-type low-temperature polysilicon, the deposition method for forming the initial channel may also be chemical vapor deposition, atomic layer deposition, pulsed laser deposition, electron beam evaporation and the like.
  • the dry etching includes any one of ion milling etching, plasma etching, reactive ion etching, laser ablation and inductively coupled plasma etching.
  • the specific steps of forming a source and a drain on the upper surface of the channel in step S4 include:
  • the Au/Ti stack was grown by physical vapor deposition, and a source 600 and a drain 700 were respectively formed on part of the upper surface of the channel 500 by photolithography and etching.
  • the resulting structure is shown in FIG. 1 .
  • the present invention is not limited thereto, and the material of the source electrode 600 and the drain electrode 700 may also be Au/Cr stack or TiAlNiAu material.
  • the back gate 100 when a positive voltage is applied to the back gate 100, electrons flow from the channel 500 into the floating gate 300, causing the threshold voltage of the thin film transistor memory to change; when the back gate When a negative voltage is applied to 100, since the side gate structure 102 existing in the vertical direction of the back gate 100 regulates the energy band of the floating gate 300 through the barrier layer 200, the valence band of the p-type floating gate 300 will rise. Above the conduction band of the n-type channel 500, the electrons located in the valence band of the floating gate 300 can easily tunnel directly through the tunneling layer 400 to the conduction band of the channel 500, thereby restoring the thin film transistor memory to its original state. state, that is, two states of charge writing and erasing are realized through the inflow and outflow of electrons in the floating gate 300 .

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Abstract

The present invention provides a thin film transistor memory, comprising a back gate, a barrier layer, a floating gate, a tunneling layer, a channel, a source and a drain. The back gate comprises a bottom gate structure and a side gate structure; the side gate structure is provided on part of the upper surface of the bottom gate structure to form an L-shaped structure; the barrier layer is provided on the upper surface of the bottom gate structure; the floating gate is provided on the upper surface of the barrier layer; the upper surface of the floating gate is flush with the upper surface of the side gate structure; the tunneling layer is provided on the upper surface of the floating gate; the channel is provided on the upper surface of the tunneling layer; the source and the drain are provided on the upper surface of the channel, so that energy band regulation and control can be performed on the floating gate by means of the side gate structure to increase the electronic erasing speed and reduce the electronic erasing voltage, thereby reducing the power consumption; moreover, the channel is not in contact with the floating gate, so that the memory is not prone to leakage, and has higher reliability. The present invention also provides a preparation method for the thin film transistor memory.

Description

薄膜晶体管存储器及其制备方法Thin film transistor memory and its preparation method
交叉引用cross reference
本申请要求2021年11月09日提交的申请号为2021113225624的中国申请的优先权。上述申请的内容以引用方式被包含于此。This application claims the priority of the Chinese application number 2021113225624 filed on November 09, 2021. The content of the above application is incorporated herein by reference.
技术领域technical field
本发明涉及半导体存储技术领域，尤其涉及一种薄膜晶体管存储器及其制备方法。The invention relates to the technical field of semiconductor storage, in particular to a thin film transistor storage and a preparation method thereof.
背景技术Background technique
非挥发性存储器是现代电子器件中不可缺少的一种元器件，目前市场上的非挥发性存储器仍是以硅基器件为主。然而，基于单晶硅衬底的传统浮栅结构的非挥发性存储器由于制作工艺复杂，通常涉及到高温工艺，因此很难在玻璃衬底上来制作嵌入式的非挥发性存储器，从而导致其在集成到显示面板上时受到限制。Non-volatile memory is an indispensable component in modern electronic devices. At present, non-volatile memory on the market is still dominated by silicon-based devices. However, due to the complex manufacturing process of traditional floating gate non-volatile memories based on single-crystal silicon substrates, usually involving high-temperature processes, it is difficult to manufacture embedded non-volatile memories on glass substrates, resulting in their Restricted when integrated into display panels.
目前，一种基于薄膜晶体管(TFT)结构的非挥发性存储器引起了大家的广泛关注，该存储器不仅可以制作在玻璃或者柔性衬底上，而且其制程工艺能很好地与传统的TFT制程工艺相兼容，在未来的先进***面板或者***级封装领域有很大的应用前景。然而对于现有的TFT存储器结构，仍然经由隧穿层来实现电荷在沟道和俘获层之间的移动。随着集成电路工艺节点的不断推进，隧穿层的厚度不断减小，从而导致被俘获层俘获的电荷很容易返回到隧穿层，降低了电荷保持特性。为了增强电荷保持特性，通常采用宽禁带半导体材料或者功函数较高的金属材料。然而使用这些新型俘获层材料，又反过来导致被俘获层俘获的电荷很难被擦除。At present, a non-volatile memory based on a thin-film transistor (TFT) structure has attracted widespread attention. This memory can not only be fabricated on glass or a flexible substrate, but its manufacturing process can be well compared with the traditional TFT manufacturing process. Compatible with each other, it has great application prospects in the field of advanced system panels or system-in-packages in the future. However, for the existing TFT memory structure, the movement of charges between the channel and the trapping layer is still realized through the tunneling layer. With the continuous advancement of the process node of the integrated circuit, the thickness of the tunneling layer is continuously reduced, so that the charges trapped by the trapping layer are easily returned to the tunneling layer, which reduces the charge retention characteristics. In order to enhance the charge retention characteristics, wide bandgap semiconductor materials or metal materials with higher work functions are usually used. However, the use of these new trapping layer materials in turn makes it difficult to erase the charges trapped by the trapping layer.
公开号为CN111477628A的中国专利公开了一种半浮栅TFT存储器及其制 备方法。该发明半浮栅TFT存储器包括：L型背栅；背栅底部上的L型阻挡层，其顶部与所述背栅的顶部相持平；在阻挡层底部上的L型浮栅，其顶部与所述阻挡层的顶部相持平；在浮栅底部的隧穿层，其上表面与所述浮栅的顶部相持平；在隧穿层和浮栅的上表面的沟道；在沟道上的源极和漏极；所述浮栅和沟道均为半导体材料，而且具有相反的导电类型，所述浮栅、所述沟道、所述阻挡层以及所述背栅构成栅控二极管。该发明的半浮栅TFT存储器数据写入和擦除全部通过栅控二极管来实现，可以加快数据擦写速度。但该发明为半浮栅型存储器，部分浮栅和沟道直接接触设置，使得浮栅中所俘获的电子很容易回流到沟道中，从而影响电荷存储的稳定性和可靠性Publication number is that the Chinese patent of CN111477628A discloses a kind of semi-floating gate TFT memory and preparation method thereof. The semi-floating gate TFT memory of the invention comprises: an L-shaped back gate; an L-shaped barrier layer on the bottom of the back gate, whose top is level with the top of the back gate; an L-shaped floating gate on the bottom of the barrier layer, whose top is aligned with the top of the back gate. The top of the blocking layer is level; the tunneling layer at the bottom of the floating gate, the upper surface of which is level with the top of the floating gate; the channel on the upper surfaces of the tunneling layer and the floating gate; the source on the channel electrode and drain; the floating gate and the channel are semiconductor materials, and have opposite conductivity types, and the floating gate, the channel, the barrier layer and the back gate form a gate-controlled diode. The writing and erasing of data in the semi-floating gate TFT memory of the invention is all realized through gate-controlled diodes, which can speed up data erasing and writing. However, this invention is a semi-floating gate memory, and part of the floating gate is directly in contact with the channel, so that the electrons trapped in the floating gate can easily flow back into the channel, thereby affecting the stability and reliability of charge storage.
因此，有必要提供一种新型的薄膜晶体管存储器及其制备方法以解决现有技术中存在的上述问题。Therefore, it is necessary to provide a novel thin film transistor memory and its preparation method to solve the above-mentioned problems existing in the prior art.
发明内容Contents of the invention
本发明的目的在于提供一种薄膜晶体管存储器及其制备方法，以加快电子擦除速度，降低电子擦除电压，从而可以降低功耗，而且该薄膜晶体管存储器相对于半浮栅薄膜晶体管存储器不容易泄漏，可靠性更强。The object of the present invention is to provide a thin film transistor memory and its preparation method, to speed up the electronic erasing speed, reduce the electronic erasing voltage, thereby reducing power consumption, and the thin film transistor memory is not easy to use compared with the semi-floating gate thin film transistor memory. Leakage, greater reliability.
为实现上述目的，本发明的所述薄膜晶体管存储器，包括：To achieve the above purpose, the thin film transistor memory of the present invention includes:
背栅，包括底栅结构和侧栅结构，所述侧栅结构设置于所述底栅结构的部分上表面以构成L型结构；The back gate includes a bottom gate structure and a side gate structure, and the side gate structure is arranged on a part of the upper surface of the bottom gate structure to form an L-shaped structure;
阻挡层，设置于所述底栅结构的上表面；a barrier layer disposed on the upper surface of the bottom gate structure;
浮栅，设置于所述阻挡层的上表面，且所述浮栅与所述背栅分隔设置，所述浮栅的上表面与所述侧栅结构的上表面相持平；The floating gate is arranged on the upper surface of the barrier layer, and the floating gate is separated from the back gate, and the upper surface of the floating gate is flat with the upper surface of the side gate structure;
隧穿层，设置于所述浮栅的上表面；a tunneling layer disposed on the upper surface of the floating gate;
沟道，设置于所述隧穿层的上表面，所述沟道与所述浮栅不接触设置，且所述浮栅和所述沟道具有相反的导电类型；a channel disposed on the upper surface of the tunneling layer, the channel is not in contact with the floating gate, and the floating gate and the channel have opposite conductivity types;
源极和漏极，设置于所述沟道的上表面。The source and the drain are arranged on the upper surface of the channel.
本发明的所述薄膜晶体管存储器的有益效果在于：通过背栅包括底栅结构和侧栅结构，所述侧栅结构设置于所述底栅结构的部分上表面以构成L型结构，阻挡层设置于所述底栅结构的上表面，浮栅设置于所述阻挡层的上表面，且所述浮栅与所述背栅分隔设置，所述浮栅的上表面与所述侧栅结构的上表面相持平，隧穿层设置于所述浮栅的上表面，沟道设置于所述隧穿层的上表面，所述沟道与所述浮栅不接触设置，且所述浮栅和所述沟道具有相反的导电类型，源极和漏极设置于所述沟道的上表面，使得可以通过所述侧栅结构对薄膜晶体管存储器的所述浮栅进行能带调控，以加快电子擦除速度，降低电子擦除电压，从而可以降低功耗，而且因为所述沟道与所述浮栅不接触设置，使得该薄膜晶体管存储器相对于半浮栅薄膜晶体管存储器不容易泄漏，可靠性更强；即当进行写入操作时，电子从所述沟道隧穿通过所述隧穿层流入所述浮栅，以引起存储器阈值电压的变化，而当进行擦除操作时，由于所述侧栅结构的控制作用，所述浮栅的价带会位于所述沟道的导带之上，此时位于所述浮栅价带上的电子会隧穿通过所述隧穿层到达所述沟道的导带，即电子会从所述浮栅流回所述沟道，存储器又恢复到原始状态，电子在浮栅内的流入和流出，实现了电子写入和擦除两种状态。The beneficial effect of the thin film transistor memory of the present invention is that: the back gate includes a bottom gate structure and a side gate structure, the side gate structure is arranged on a part of the upper surface of the bottom gate structure to form an L-shaped structure, and the barrier layer is provided On the upper surface of the bottom gate structure, the floating gate is arranged on the upper surface of the barrier layer, and the floating gate is separated from the back gate, and the upper surface of the floating gate is separated from the upper surface of the side gate structure. The surfaces are flat, the tunneling layer is arranged on the upper surface of the floating gate, the channel is arranged on the upper surface of the tunneling layer, the channel is not in contact with the floating gate, and the floating gate and the floating gate The channel has opposite conductivity types, and the source and drain are arranged on the upper surface of the channel, so that the energy band of the floating gate of the thin film transistor memory can be adjusted through the side gate structure, so as to accelerate electron erasure. The erasing speed reduces the electronic erasing voltage, thereby reducing power consumption, and because the channel and the floating gate are not in contact with each other, the thin film transistor memory is not easy to leak compared with the semi-floating gate thin film transistor memory, and the reliability is higher. Strong; that is, when the write operation is performed, electrons tunnel from the channel through the tunneling layer and flow into the floating gate to cause a change in the threshold voltage of the memory, while when the erase operation is performed, due to the side The control function of the gate structure, the valence band of the floating gate will be located above the conduction band of the channel, at this time, the electrons located in the valence band of the floating gate will tunnel through the tunneling layer to the channel The conduction band of the channel, that is, electrons will flow back to the channel from the floating gate, and the memory will return to its original state. The inflow and outflow of electrons in the floating gate realizes two states of electronic writing and erasing.
优选的，所述阻挡层包括底部阻挡结构和侧部阻挡结构，所述侧部阻挡结构设置于所述底部阻挡结构的部分上表面以构成L型结构，所述侧部阻挡结构设置于所述浮栅与所述侧栅结构之间。其有益效果在于：使得所述浮栅与所述背栅的所述侧栅结构之间通过所述侧部阻挡结构分隔，从而更有利于使所述浮栅和所述背栅之间形成隔断，以确保避免所述浮栅价带上的电子会流至所述背栅而导致漏电发生。Preferably, the barrier layer includes a bottom barrier structure and a side barrier structure, the side barrier structure is arranged on a part of the upper surface of the bottom barrier structure to form an L-shaped structure, and the side barrier structure is arranged on the Between the floating gate and the side gate structure. The beneficial effect is that the floating gate is separated from the side gate structure of the back gate by the side barrier structure, which is more conducive to forming an isolation between the floating gate and the back gate. , so as to ensure that the electrons in the valence band of the floating gate will not flow to the back gate and cause electric leakage.
优选的，所述侧部阻挡结构的两对称侧表面分别抵持于所述浮栅和所述侧栅结构，且所述侧部阻挡结构的上表面与所述侧栅结构的上表面相持平。其有益效果在于：在更有利于使所述浮栅和所述背栅之间形成隔断的同时，也便于制备L型结构的背栅和阻挡层。Preferably, the two symmetrical side surfaces of the side barrier structure respectively bear against the floating gate and the side gate structure, and the upper surface of the side barrier structure is flush with the upper surface of the side gate structure . The beneficial effect is that: while it is more conducive to forming an isolation between the floating gate and the back gate, it is also convenient to prepare the back gate and the barrier layer of the L-shaped structure.
优选的，所述沟道靠近所述侧栅结构的第一侧表面和所述隧穿层靠近所述侧栅结构的第二侧表面均与所述浮栅靠近所述侧栅结构的第三侧表面持平设置。其有益效果在于：便于制备，确保了所述沟道与所述浮栅不接触设置，从而避免了漏电风险。Preferably, the first side surface of the channel close to the side gate structure and the second side surface of the tunneling layer close to the side gate structure are both connected to the third side surface of the floating gate close to the side gate structure. The side surfaces are set flat. The beneficial effect is that it is easy to manufacture, and ensures that the channel and the floating gate are arranged without contact, thus avoiding the risk of electric leakage.
优选的，所述浮栅和所述沟道均采用半导体材料制作而成，所述沟道的材料为n型半导体材料，所述浮栅的材料为p型半导体材料。Preferably, both the floating gate and the channel are made of semiconductor material, the material of the channel is n-type semiconductor material, and the material of the floating gate is p-type semiconductor material.
优选的，所述浮栅的材料为NiO、Cu 2O、SnO、AlSnO、p型多晶硅半导体材料、Pt、Pd、Ni和Au中的任意一种。 Preferably, the material of the floating gate is any one of NiO, Cu 2 O, SnO, AlSnO, p-type polysilicon semiconductor material, Pt, Pd, Ni and Au.
优选的，所述沟道的材料为IGZO、ZnO、In 2O 3、Ga 2O 3和n型多晶硅半导体材料中的任意一种。 Preferably, the material of the channel is any one of IGZO, ZnO, In 2 O 3 , Ga 2 O 3 and n-type polysilicon semiconductor materials.
优选的，本发明还提供一种薄膜晶体管存储器的制备方法，包括步骤：Preferably, the present invention also provides a method for preparing a thin film transistor memory, comprising the steps of:
S1：形成底栅结构和侧栅结构，且使所述侧栅结构设置于所述底栅结构的部分上表面以构成L型结构的背栅；S1: forming a bottom gate structure and a side gate structure, and disposing the side gate structure on a part of the upper surface of the bottom gate structure to form a back gate of an L-shaped structure;
S2：在所述底栅结构的上表面依次形成阻挡层和浮栅，使所述浮栅设置于所述阻挡层的上表面并与所述背栅分隔设置，使所述浮栅的上表面与所述侧栅结构的上表面相持平；S2: sequentially forming a barrier layer and a floating gate on the upper surface of the bottom gate structure, so that the floating gate is arranged on the upper surface of the barrier layer and separated from the back gate, so that the upper surface of the floating gate being flat with the upper surface of the side gate structure;
S3：在所述浮栅的上表面依次形成隧穿层和沟道，使所述沟道与所述浮栅不接触设置，且使所述浮栅和所述沟道具有相反的导电类型；S3: sequentially forming a tunneling layer and a channel on the upper surface of the floating gate, making the channel not in contact with the floating gate, and making the floating gate and the channel have opposite conductivity types;
S4：在所述沟道的上表面形成源极和漏极。S4: forming a source and a drain on the upper surface of the channel.
本发明的所述薄膜晶体管存储器的制备方法的有益效果在于：通过S1：形成底栅结构和侧栅结构，且使所述侧栅结构设置于所述底栅结构的部分上表面以构成L型结构的背栅，S2：在所述底栅结构的上表面依次形成阻挡层和浮栅，使所述浮栅设置于所述阻挡层的上表面并与所述背栅分隔设置，使所述浮栅的上表面与所述侧栅结构的上表面相持平，S3：在所述浮栅的上表面依次形成隧穿层和沟道，使所述沟道与所述浮栅不接触设置，且使所述浮栅和所述沟道具 有相反的导电类型，S4：在所述沟道的上表面形成源极和漏极，使得可以通过所述侧栅结构对薄膜晶体管存储器的所述浮栅进行能带调控，以加快电子擦除速度，降低电子擦除电压，从而可以降低功耗，而且因为所述沟道与所述浮栅不接触设置，使得该薄膜晶体管存储器相对于半浮栅薄膜晶体管存储器不容易泄漏，可靠性更强；即当进行写入操作时，电子从所述沟道隧穿通过所述隧穿层流入所述浮栅，以引起存储器阈值电压的变化，而当进行擦除操作时，由于所述侧栅结构的控制作用，所述浮栅的价带会位于所述沟道的导带之上，此时位于所述浮栅价带上的电子会隧穿通过所述隧穿层到达所述沟道的导带，即电子会从所述浮栅流回所述沟道，存储器又恢复到原始状态，电子在浮栅内的流入和流出，实现了电子写入和擦除两种状态；而且该制备方法简单方便，工艺制程可以与传统的TFT工艺完全兼容。The beneficial effect of the preparation method of the thin film transistor memory of the present invention is that: through S1: forming a bottom gate structure and a side gate structure, and setting the side gate structure on a part of the upper surface of the bottom gate structure to form an L-shaped The back gate of the structure, S2: a barrier layer and a floating gate are sequentially formed on the upper surface of the bottom gate structure, so that the floating gate is arranged on the upper surface of the barrier layer and separated from the back gate, so that the The upper surface of the floating gate is flush with the upper surface of the side gate structure, S3: sequentially forming a tunneling layer and a channel on the upper surface of the floating gate so that the channel is not in contact with the floating gate, And make the floating gate and the channel have opposite conductivity types, S4: form a source and a drain on the upper surface of the channel, so that the floating gate of the thin film transistor memory can be controlled by the side gate structure. The energy band of the gate is adjusted to speed up the electronic erasing speed and reduce the electronic erasing voltage, thereby reducing power consumption, and because the channel and the floating gate are not in contact with each other, the thin film transistor memory is relatively The thin film transistor memory is not easy to leak, and the reliability is stronger; that is, when the write operation is performed, electrons tunnel from the channel through the tunneling layer and flow into the floating gate to cause a change in the threshold voltage of the memory. During the erasing operation, due to the control effect of the side gate structure, the valence band of the floating gate will be located above the conduction band of the channel, and at this time, the electrons located in the valence band of the floating gate will tunnel The tunneling layer reaches the conduction band of the channel, that is, electrons will flow back to the channel from the floating gate, and the memory will return to its original state. The inflow and outflow of electrons in the floating gate realizes the There are two states of writing and erasing; moreover, the preparation method is simple and convenient, and the process is fully compatible with the traditional TFT process.
优选的，所述步骤S2中在所述底栅结构的上表面依次形成阻挡层和浮栅的步骤包括：Preferably, the step of sequentially forming a barrier layer and a floating gate on the upper surface of the bottom gate structure in the step S2 includes:
S21：在所述背栅的上表面沉积阻挡层材料；S21: Deposit a barrier layer material on the upper surface of the back gate;
S22：通过蚀刻工艺去除高于所述侧栅结构的上表面的所述阻挡层材料，以在所述底栅结构的上表面形成L型结构的所述阻挡层，且使所述阻挡层的侧部阻挡结构的上表面与所述侧栅结构的上表面相持平。其有益效果在于：在更有利于使所述浮栅和所述背栅之间形成隔断的同时，也便于制备L型结构的背栅和阻挡层。S22: removing the material of the barrier layer higher than the upper surface of the side gate structure through an etching process, so as to form the barrier layer of an L-shaped structure on the upper surface of the bottom gate structure, and make the barrier layer The upper surface of the side barrier structure is level with the upper surface of the side gate structure. The beneficial effect is that: while it is more conducive to forming an isolation between the floating gate and the back gate, it is also convenient to prepare the back gate and the barrier layer of the L-shaped structure.
优选的，所述步骤S22中在所述底栅结构的上表面形成L型结构的阻挡层之后还包括步骤：Preferably, the step S22 further includes the step of forming an L-shaped barrier layer on the upper surface of the bottom gate structure:
S23：在所述阻挡层的上表面和所述侧栅结构的上表面沉积浮栅材料；S23: depositing a floating gate material on the upper surface of the barrier layer and the upper surface of the side gate structure;
S24：通过蚀刻工艺去除部分所述浮栅材料，以在所述阻挡层的上表面形成所述浮栅，且使所述浮栅的上表面、所述侧部阻挡结构的上表面和所述侧栅结 构的上表面相持平。其有益效果在于：制备方法简单方便，工艺制程可以与传统的TFT工艺完全兼容。S24: Remove part of the floating gate material by etching to form the floating gate on the upper surface of the barrier layer, and make the upper surface of the floating gate, the upper surface of the side barrier structure and the The upper surface of the side gate structure is flat. The beneficial effect is that the preparation method is simple and convenient, and the process can be completely compatible with the traditional TFT process.
优选的，所述步骤S3中在所述浮栅的上表面依次形成隧穿层和沟道的步骤包括：Preferably, the step of sequentially forming a tunneling layer and a channel on the upper surface of the floating gate in the step S3 includes:
S31：在所述浮栅的上表面、所述侧部阻挡结构的上表面和所述侧栅结构的上表面沉积隧穿层材料和沟道材料；S31: Deposit a tunneling layer material and a channel material on the upper surface of the floating gate, the upper surface of the side barrier structure, and the upper surface of the side gate structure;
S32：通过蚀刻工艺去除位于所述侧部阻挡结构的上表面和所述侧栅结构的上表面的所述隧穿层材料和所述沟道材料，以形成所述隧穿层和所述沟道，使所述沟道靠近所述侧栅结构的第一侧表面和所述隧穿层靠近所述侧栅结构的第二侧表面均与所述浮栅靠近所述侧栅结构的第三侧表面持平设置。其有益效果在于：制备方法简单方便，工艺制程可以与传统的TFT工艺完全兼容。S32: removing the tunneling layer material and the channel material located on the upper surface of the side barrier structure and the upper surface of the side gate structure through an etching process, so as to form the tunneling layer and the trench channel, so that the first side surface of the channel close to the side gate structure and the second side surface of the tunneling layer close to the side gate structure are both connected to the third side surface of the floating gate close to the side gate structure The side surfaces are set flat. The beneficial effect is that the preparation method is simple and convenient, and the process can be completely compatible with the traditional TFT process.
附图说明Description of drawings
图1为本发明第一种实施例的薄膜晶体管存储器的剖视图；1 is a cross-sectional view of a thin film transistor memory according to a first embodiment of the present invention;
图2为本发明第二种实施例的薄膜晶体管存储器的剖视图；2 is a cross-sectional view of a thin film transistor memory according to a second embodiment of the present invention;
图3为本发明第三种实施例的薄膜晶体管存储器的剖视图；3 is a cross-sectional view of a thin film transistor memory according to a third embodiment of the present invention;
图4为本发明第四种实施例的薄膜晶体管存储器的剖视图；4 is a cross-sectional view of a thin film transistor memory according to a fourth embodiment of the present invention;
图5为本发明第五种实施例的薄膜晶体管存储器的剖视图；5 is a cross-sectional view of a thin film transistor memory according to a fifth embodiment of the present invention;
图6为本发明第六种实施例的薄膜晶体管存储器的剖视图；6 is a cross-sectional view of a thin film transistor memory according to a sixth embodiment of the present invention;
图7为本发明实施例的薄膜晶体管存储器的制备方法的流程图；7 is a flowchart of a method for manufacturing a thin film transistor memory according to an embodiment of the present invention;
图8为本发明实施例中背栅的剖视图；8 is a cross-sectional view of a back gate in an embodiment of the present invention;
图9为对图8所示的背栅的上表面进行沉积处理后形成的结构的剖视图；FIG. 9 is a cross-sectional view of a structure formed after deposition treatment is performed on the upper surface of the back gate shown in FIG. 8;
图10为对图9所示结构进行刻蚀处理形成阻挡层后的结构剖视图；FIG. 10 is a cross-sectional view of the structure shown in FIG. 9 after etching to form a barrier layer;
图11为本发明一些实施例中对图10所示的阻挡层的上表面进行沉积处理后形成的结构的剖视图；FIG. 11 is a cross-sectional view of a structure formed after deposition treatment is performed on the upper surface of the barrier layer shown in FIG. 10 in some embodiments of the present invention;
图12为对图11所示的结构进行刻蚀处理形成浮栅后的结构的剖视图；12 is a cross-sectional view of the structure shown in FIG. 11 after etching to form a floating gate;
图13为本发明另一些实施例中对图10所示的阻挡层的上表面进行沉积处理后形成的结构的剖视图；FIG. 13 is a cross-sectional view of a structure formed after deposition treatment is performed on the upper surface of the barrier layer shown in FIG. 10 in other embodiments of the present invention;
图14为对图12所示的浮栅的上表面进行沉积处理形成初始隧穿层后的结构的剖视图；FIG. 14 is a cross-sectional view of the structure after depositing the upper surface of the floating gate shown in FIG. 12 to form an initial tunneling layer;
图15为对图14所示的初始隧穿层的上表面进行沉积处理形成初始沟道后的结构的剖视图；FIG. 15 is a cross-sectional view of the structure after depositing the upper surface of the initial tunneling layer shown in FIG. 14 to form an initial channel;
图16为对图15所示结构进行刻蚀处理形成隧穿层和沟道后的结构的剖视图。FIG. 16 is a cross-sectional view of the structure after etching the structure shown in FIG. 15 to form a tunneling layer and a channel.
具体实施方式Detailed ways
为使本发明的目的、技术方案和优点更加清楚，下面将结合本发明的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。除非另外定义，此处使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本文中使用的“包括”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。In order to make the purpose, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the present invention. Obviously, the described embodiments are part of the present invention Examples, not all examples. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention. Unless otherwise defined, the technical terms or scientific terms used herein shall have the usual meanings understood by those skilled in the art to which the present invention belongs. As used herein, "comprising" and similar words mean that the elements or items appearing before the word include the elements or items listed after the word and their equivalents, without excluding other elements or items.
为克服现有技术中存在的问题，本发明实施例提供了薄膜晶体管存储器及其制备方法，以加快电子擦除速度，降低电子擦除电压，从而可以降低功耗，而 且该薄膜晶体管存储器相对于半浮栅薄膜晶体管存储器不容易泄漏，可靠性更强。In order to overcome the problems existing in the prior art, the embodiment of the present invention provides a thin film transistor memory and its preparation method, so as to speed up the electronic erasing speed and reduce the electronic erasing voltage, so as to reduce power consumption, and the thin film transistor memory is relatively Semi-floating gate thin film transistor memory is not easy to leak and has stronger reliability.
图1为本发明第一种实施例的薄膜晶体管存储器的剖视图。FIG. 1 is a cross-sectional view of a thin film transistor memory according to a first embodiment of the present invention.
本发明实施例的所述薄膜晶体管存储器，参考图1，包括背栅100、阻挡层200、浮栅300、隧穿层400、沟道500、源极600和漏极700；所述背栅100包括底栅结构101和侧栅结构102，所述侧栅结构102设置于所述底栅结构101的部分上表面以构成L型结构；所述阻挡层200设置于所述底栅结构101的上表面；所述浮栅300设置于所述阻挡层200的上表面，且所述浮栅300与所述背栅100分隔设置，所述浮栅300的上表面与所述侧栅结构102的上表面相持平；所述隧穿层400设置于所述浮栅300的上表面；所述沟道500设置于所述隧穿层400的上表面，所述沟道500与所述浮栅300不接触设置，且所述浮栅300和所述沟道500具有相反的导电类型；所述源极600和漏极700设置于所述沟道500的上表面。使得可以通过所述侧栅结构102对薄膜晶体管存储器(图中未标示)的所述浮栅300进行能带调控，以加快电子擦除速度，降低电子擦除电压，从而可以降低功耗，而且因为所述沟道500与所述浮栅300不接触设置，使得该薄膜晶体管存储器(图中未标示)相对于半浮栅薄膜晶体管存储器不容易泄漏，可靠性更强。The thin film transistor memory according to the embodiment of the present invention, referring to FIG. 1 , includes a back gate 100, a barrier layer 200, a floating gate 300, a tunneling layer 400, a channel 500, a source 600 and a drain 700; the back gate 100 Including a bottom gate structure 101 and a side gate structure 102, the side gate structure 102 is arranged on a part of the upper surface of the bottom gate structure 101 to form an L-shaped structure; the barrier layer 200 is arranged on the bottom gate structure 101 surface; the floating gate 300 is disposed on the upper surface of the barrier layer 200, and the floating gate 300 is separated from the back gate 100, and the upper surface of the floating gate 300 is connected to the upper surface of the side gate structure 102 The surface is flat; the tunneling layer 400 is arranged on the upper surface of the floating gate 300; the channel 500 is arranged on the upper surface of the tunneling layer 400, and the channel 500 and the floating gate 300 are not Contacts are provided, and the floating gate 300 and the channel 500 have opposite conductivity types; the source 600 and the drain 700 are provided on the upper surface of the channel 500 . It is possible to regulate the energy band of the floating gate 300 of the thin film transistor memory (not shown in the figure) through the side gate structure 102, so as to speed up the electronic erasing speed and reduce the electronic erasing voltage, thereby reducing power consumption, and Because the channel 500 is not in contact with the floating gate 300 , the thin film transistor memory (not shown in the figure) is less likely to leak than the semi-floating gate thin film transistor memory, and has stronger reliability.
具体的，当进行写入操作时，电子从所述沟道500隧穿通过所述隧穿层400流入所述浮栅300，以引起存储器阈值电压的变化，而当进行擦除操作时，由于所述侧栅结构102的控制作用，所述浮栅300的价带会位于所述沟道500的导带之上，此时位于所述浮栅300价带上的电子会隧穿通过所述隧穿层400到达所述沟道500的导带，即电子会从所述浮栅300流回所述沟道500，存储器又恢复到原始状态，电子在浮栅300内的流入和流出，实现了电子写入和擦除两种状态。Specifically, when a write operation is performed, electrons tunnel from the channel 500 through the tunneling layer 400 and flow into the floating gate 300 to cause a change in the threshold voltage of the memory, while when an erase operation is performed, due to The control function of the side gate structure 102, the valence band of the floating gate 300 will be located above the conduction band of the channel 500, and the electrons located in the valence band of the floating gate 300 will tunnel through the The tunneling layer 400 reaches the conduction band of the channel 500, that is, electrons will flow back from the floating gate 300 to the channel 500, and the memory will return to its original state, and the inflow and outflow of electrons in the floating gate 300 will realize There are two states of electronic writing and erasing.
本发明一些实施例中，参考图1，所述阻挡层200包括底部阻挡结构201和 侧部阻挡结构202，所述侧部阻挡结构202设置于所述底部阻挡结构201的部分上表面以构成L型结构，所述侧部阻挡结构202设置于所述浮栅300与所述侧栅结构102之间。In some embodiments of the present invention, referring to FIG. 1, the barrier layer 200 includes a bottom barrier structure 201 and a side barrier structure 202, and the side barrier structure 202 is disposed on a part of the upper surface of the bottom barrier structure 201 to form a L type structure, the side barrier structure 202 is disposed between the floating gate 300 and the side gate structure 102 .
具体的，所述侧部阻挡结构202设置于所述浮栅300的侧表面与所述侧栅结构102的侧表面之间，使得所述浮栅300与所述背栅100的所述侧栅结构102之间通过所述侧部阻挡结构202分隔，所述底部阻挡结构201设置于所述浮栅300的下表面与所述底栅结构101的上表面之间，使得所述浮栅300与所述背栅100的所述底栅结构101之间通过所述底部阻挡结构201分隔，从而有利于使所述浮栅和所述背栅之间形成隔断，以确保避免所述浮栅价带上的电子会流至所述背栅而导致漏电发生。Specifically, the side barrier structure 202 is disposed between the side surface of the floating gate 300 and the side surface of the side gate structure 102, so that the floating gate 300 and the side gate of the back gate 100 The structures 102 are separated by the side barrier structure 202, and the bottom barrier structure 201 is arranged between the lower surface of the floating gate 300 and the upper surface of the bottom gate structure 101, so that the floating gate 300 and the upper surface of the bottom gate structure 101 are separated. The bottom gate structures 101 of the back gate 100 are separated by the bottom barrier structure 201, which is conducive to forming an isolation between the floating gate and the back gate, so as to ensure that the valence band of the floating gate is avoided. The electrons on the upper gate will flow to the back gate and cause electric leakage to occur.
本发明一些实施例中，参考图1，所述侧部阻挡结构202的两对称侧表面分别抵持于所述浮栅300和所述侧栅结构102，且所述侧部阻挡结构202的上表面与所述侧栅结构102的上表面相持平，即所述侧栅结构102的上表面、所述侧部阻挡结构202的上表面和所述浮栅300的上表面持平设置，在更有利于使所述浮栅300和所述背栅100之间形成隔断的同时，也便于制备形成L型结构的背栅100和L型结构的阻挡层200。In some embodiments of the present invention, referring to FIG. 1 , the two symmetrical side surfaces of the side barrier structure 202 are held against the floating gate 300 and the side gate structure 102 respectively, and the upper surface of the side barrier structure 202 The surface is flat with the upper surface of the side gate structure 102, that is, the upper surface of the side gate structure 102, the upper surface of the side barrier structure 202 and the upper surface of the floating gate 300 are arranged on the same level. While it is beneficial to form an isolation between the floating gate 300 and the back gate 100 , it is also convenient to prepare the L-shaped structure of the back gate 100 and the L-shaped barrier layer 200 .
本发明一些实施例中，参考图1，所述沟道500靠近所述侧栅结构102的第一侧表面501和所述隧穿层400靠近所述侧栅结构102的第二侧表面401均与所述浮栅300靠近所述侧栅结构102的第三侧表面301持平设置，便于制备，确保了所述沟道500与所述浮栅300不接触设置，从而避免了漏电风险。In some embodiments of the present invention, referring to FIG. 1 , the first side surface 501 of the channel 500 close to the side gate structure 102 and the second side surface 401 of the tunneling layer 400 close to the side gate structure 102 are both The third side surface 301 of the floating gate 300 close to the side gate structure 102 is arranged flush with the third side surface 301 of the side gate structure 102 , which is convenient for manufacture and ensures that the channel 500 is not in contact with the floating gate 300 , thus avoiding the risk of electric leakage.
本发明另一些实施例中，所述侧部阻挡结构的上表面与所述侧栅结构的上表面不持平设置。In some other embodiments of the present invention, the upper surface of the side barrier structure is not arranged flush with the upper surface of the side gate structure.
本发明一些可能实施例中，所述侧部阻挡结构的上表面高于所述侧栅结构的上表面。In some possible embodiments of the present invention, the upper surface of the side barrier structure is higher than the upper surface of the side gate structure.
本发明另一些可能实施例中，所述侧部阻挡结构的上表面低于所述侧栅结构的上表面。In other possible embodiments of the present invention, the upper surface of the side barrier structure is lower than the upper surface of the side gate structure.
图2为本发明第二种实施例的薄膜晶体管存储器的剖视图。FIG. 2 is a cross-sectional view of a thin film transistor memory according to a second embodiment of the present invention.
本发明一些具体实施例中，参考图2，图2所示的第二种薄膜晶体管存储器中的所述阻挡层200呈L型结构，所述阻挡层200包括底部阻挡结构201和侧部阻挡结构202，而图2所示的第二种薄膜晶体管存储器与图1所示的第一种薄膜晶体管存储器的区别在于：所述第二种薄膜晶体管存储器中的所述侧部阻挡结构202的上表面高于所述侧栅结构102的上表面，且所述侧部阻挡结构202的上表面与所述沟道500的上表面相持平，如图2所示。In some specific embodiments of the present invention, referring to FIG. 2, the barrier layer 200 in the second thin film transistor memory shown in FIG. 2 has an L-shaped structure, and the barrier layer 200 includes a bottom barrier structure 201 and a side barrier structure. 202, and the difference between the second type of thin film transistor memory shown in FIG. 2 and the first type of thin film transistor memory shown in FIG. 1 is that the upper surface of the side barrier structure 202 in the second type of thin film transistor memory is higher than the upper surface of the side gate structure 102 , and the upper surface of the side barrier structure 202 is level with the upper surface of the channel 500 , as shown in FIG. 2 .
图3为本发明第三种实施例的薄膜晶体管存储器的剖视图。FIG. 3 is a cross-sectional view of a thin film transistor memory according to a third embodiment of the present invention.
本发明另一些具体实施例中，参考图3，图3所示的第三种薄膜晶体管存储器中的所述阻挡层200呈L型结构，所述阻挡层200包括底部阻挡结构201和侧部阻挡结构202，而图3所示的第三种薄膜晶体管存储器与图1所示的第一种薄膜晶体管存储器的区别在于：所述第三种薄膜晶体管存储器中的所述侧部阻挡结构202的上表面高于所述侧栅结构102的上表面，且所述侧部阻挡结构202的上表面与所述隧穿层400的上表面相持平，如图3所示。In other specific embodiments of the present invention, referring to FIG. 3, the barrier layer 200 in the third thin film transistor memory shown in FIG. structure 202, and the difference between the third type of thin film transistor memory shown in FIG. 3 and the first type of thin film transistor memory shown in FIG. The surface is higher than the upper surface of the side gate structure 102 , and the upper surface of the side barrier structure 202 is level with the upper surface of the tunneling layer 400 , as shown in FIG. 3 .
图4为本发明第四种实施例的薄膜晶体管存储器的剖视图。FIG. 4 is a cross-sectional view of a thin film transistor memory according to a fourth embodiment of the present invention.
本发明又一些具体实施例中，参考图4，图4所示的第四种薄膜晶体管存储器中的所述阻挡层200呈L型结构，所述阻挡层200包括底部阻挡结构201和侧部阻挡结构202，而图4所示的第四种薄膜晶体管存储器与图1所示的第一种薄膜晶体管存储器的区别在于：所述第四种薄膜晶体管存储器中的所述侧部阻挡结构202的上表面低于所述侧栅结构102的上表面，即所述浮栅300与所述侧栅结构102的部分侧表面之间通过所述侧部阻挡结构202分隔设置，所述浮栅300与所述侧栅结构102的剩余部分侧表面之间通过间隙分隔设置。In still some specific embodiments of the present invention, referring to FIG. 4, the barrier layer 200 in the fourth thin film transistor memory shown in FIG. structure 202, and the difference between the fourth type of thin film transistor memory shown in FIG. 4 and the first type of thin film transistor memory shown in FIG. The surface is lower than the upper surface of the side gate structure 102, that is, the floating gate 300 is separated from part of the side surface of the side gate structure 102 by the side barrier structure 202, and the floating gate 300 is separated from the side gate structure 102. The side surfaces of the remaining part of the side gate structure 102 are separated by gaps.
图5为本发明第五种实施例的薄膜晶体管存储器的剖视图。FIG. 5 is a cross-sectional view of a thin film transistor memory according to a fifth embodiment of the present invention.
本发明另一些实施例中，图5所示的第五种薄膜晶体管存储器与图1所示的第一种薄膜晶体管存储器的区别在于：所述第五种薄膜晶体管存储器中的阻挡层为矩形结构，参考图5，第一矩形阻挡层210设置于所述所述浮栅300的下表面与所述底栅结构101的上表面之间，且所述第一矩形阻挡层210靠近所述侧栅结构102的第四侧表面211与所述浮栅300靠近所述侧栅结构102的第三侧表面301持平设置，所述浮栅300和所述第一矩形阻挡层210与所述侧栅结构102之间通过间隙分隔设置。In other embodiments of the present invention, the difference between the fifth type of thin film transistor memory shown in FIG. 5 and the first type of thin film transistor memory shown in FIG. 1 is that the barrier layer in the fifth type of thin film transistor memory has a rectangular structure , referring to FIG. 5, the first rectangular barrier layer 210 is disposed between the lower surface of the floating gate 300 and the upper surface of the bottom gate structure 101, and the first rectangular barrier layer 210 is close to the side gate The fourth side surface 211 of the structure 102 is arranged on the same level as the third side surface 301 of the floating gate 300 close to the side gate structure 102, and the floating gate 300 and the first rectangular barrier layer 210 are aligned with the side gate structure 102 are separated by gaps.
图6为本发明第六种实施例的薄膜晶体管存储器的剖视图。FIG. 6 is a cross-sectional view of a thin film transistor memory according to a sixth embodiment of the present invention.
本发明另一些实施例中，图6所示的第六种薄膜晶体管存储器与图1所示的第一种薄膜晶体管存储器的区别在于：所述第六种薄膜晶体管存储器中的阻挡层为矩形结构，参考图6，第二矩形阻挡层220设置于所述所述浮栅300的下表面与所述底栅结构101的上表面之间，且所述第二矩形阻挡层220靠近所述侧栅结构102的第五侧表面221与所述侧栅结构102的侧表面抵持设置，而所述浮栅300与所述侧栅结构102之间通过间隙分隔设置。In other embodiments of the present invention, the difference between the sixth type of thin film transistor memory shown in FIG. 6 and the first type of thin film transistor memory shown in FIG. 1 is that the barrier layer in the sixth type of thin film transistor memory has a rectangular structure , referring to FIG. 6, the second rectangular barrier layer 220 is disposed between the lower surface of the floating gate 300 and the upper surface of the bottom gate structure 101, and the second rectangular barrier layer 220 is close to the side gate The fifth side surface 221 of the structure 102 is arranged against the side surface of the side gate structure 102 , and the floating gate 300 is separated from the side gate structure 102 by a gap.
本发明一些实施例中，所述浮栅和所述沟道均采用半导体材料制作而成，所述沟道的材料为n型半导体材料，所述浮栅的材料为p型半导体材料。In some embodiments of the present invention, both the floating gate and the channel are made of semiconductor material, the material of the channel is n-type semiconductor material, and the material of the floating gate is p-type semiconductor material.
本发明一些实施例中，所述浮栅的材料为NiO、Cu 2O、SnO、AlSnO、p型多晶硅半导体材料、Pt、Pd、Ni和Au中的任意一种。其中，所述p型多晶硅半导体材料为p型低温多晶硅半导体材料。 In some embodiments of the present invention, the material of the floating gate is any one of NiO, Cu 2 O, SnO, AlSnO, p-type polysilicon semiconductor material, Pt, Pd, Ni and Au. Wherein, the p-type polysilicon semiconductor material is a p-type low-temperature polysilicon semiconductor material.
本发明一些实施例中，所述沟道的材料为IGZO、ZnO、In 2O 3、Ga 2O 3和n型多晶硅半导体材料中的任意一种，其中，所述n型多晶硅半导体材料为n型低温多晶硅半导体材料。 In some embodiments of the present invention, the material of the channel is any one of IGZO, ZnO, In 2 O 3 , Ga 2 O 3 and n-type polysilicon semiconductor material, wherein the n-type polysilicon semiconductor material is n type low temperature polysilicon semiconductor material.
本发明一些实施例中，所述背栅为所述薄膜晶体管存储器的衬底，所述衬底为低阻硅衬底、ITO衬底和表面覆盖导电薄膜的柔性衬底中的任意一种。其中，ITO为N型氧化物半导体，即铟锡氧化物半导体透明导电膜。In some embodiments of the present invention, the back gate is the substrate of the thin film transistor memory, and the substrate is any one of a low-resistance silicon substrate, an ITO substrate, and a flexible substrate covered with a conductive film. Wherein, ITO is an N-type oxide semiconductor, that is, an indium tin oxide semiconductor transparent conductive film.
本发明一些实施例中，所述阻挡层的材料为Al 2O 3、SiO 2、HfO 2、ZrO 2、Ta 2O 5、TiO 2、La 2O 3、HfZrO 4中的至少一种，即所述阻挡层可以是所述Al 2O 3、SiO 2、HfO 2、ZrO 2、Ta 2O 5、TiO 2、La 2O 3、HfZrO 4中的任意一种，也可以是所述Al 2O 3、SiO 2、HfO 2、ZrO 2、Ta 2O 5、TiO 2、La 2O 3、HfZrO 4中至少两种组成的叠层。 In some embodiments of the present invention, the material of the barrier layer is at least one of Al 2 O 3 , SiO 2 , HfO 2 , ZrO 2 , Ta 2 O 5 , TiO 2 , La 2 O 3 , and HfZrO 4 , namely The barrier layer can be any one of the Al 2 O 3 , SiO 2 , HfO 2 , ZrO 2 , Ta 2 O 5 , TiO 2 , La 2 O 3 , HfZrO 4 , or it can be the Al 2 A stack of at least two compositions of O 3 , SiO 2 , HfO 2 , ZrO 2 , Ta 2 O 5 , TiO 2 , La 2 O 3 , and HfZrO 4 .
本发明一些实施例中，所述隧穿层的材料为Al 2O 3、SiO 2、HfO 2、ZrO 2、Ta 2O 5、TiO 2、La 2O 3、HfZrO 4中的至少一种，即所述隧穿层可以是所述Al 2O 3、SiO 2、HfO 2、ZrO 2、Ta 2O 5、TiO 2、La 2O 3、HfZrO 4中的任意一种，也可以是所述Al 2O 3、SiO 2、HfO 2、ZrO 2、Ta 2O 5、TiO 2、La 2O 3、HfZrO 4中至少两种组成的叠层。 In some embodiments of the present invention, the material of the tunneling layer is at least one of Al 2 O 3 , SiO 2 , HfO 2 , ZrO 2 , Ta 2 O 5 , TiO 2 , La 2 O 3 , and HfZrO 4 , That is, the tunneling layer can be any one of Al 2 O 3 , SiO 2 , HfO 2 , ZrO 2 , Ta 2 O 5 , TiO 2 , La 2 O 3 , HfZrO 4 , or it can be the A stack of at least two compositions of Al 2 O 3 , SiO 2 , HfO 2 , ZrO 2 , Ta 2 O 5 , TiO 2 , La 2 O 3 , and HfZrO 4 .
本发明一些实施例中，所述源极和所述漏极的材料为Au/Ti叠层、Au/Cr叠层、TiAlNiAu中的任意一种。其中，所述Au/Ti叠层是由Au材料和Ti材料堆叠设置而成，所述Au/Cr叠层是由Au材料和Cr材料堆叠设置而成。In some embodiments of the present invention, the material of the source electrode and the drain electrode is any one of Au/Ti stack, Au/Cr stack, and TiAlNiAu. Wherein, the Au/Ti stack is formed by stacking Au material and Ti material, and the Au/Cr stack is formed by stacking Au material and Cr material.
图7为本发明实施例的薄膜晶体管存储器的制备方法的流程图。FIG. 7 is a flowchart of a manufacturing method of a thin film transistor memory according to an embodiment of the present invention.
本发明一些实施例中，所述薄膜晶体管存储器的制备方法，参考图7，包括步骤：In some embodiments of the present invention, the preparation method of the thin film transistor memory, referring to FIG. 7, includes the steps of:
S1：形成底栅结构和侧栅结构，且使所述侧栅结构设置于所述底栅结构的部分上表面以构成L型结构的背栅；S1: forming a bottom gate structure and a side gate structure, and disposing the side gate structure on a part of the upper surface of the bottom gate structure to form a back gate of an L-shaped structure;
S2：在所述底栅结构的上表面依次形成阻挡层和浮栅，使所述浮栅设置于所述阻挡层的上表面并与所述背栅分隔设置，使所述浮栅的上表面与所述侧栅结构的上表面相持平；S2: sequentially forming a barrier layer and a floating gate on the upper surface of the bottom gate structure, so that the floating gate is arranged on the upper surface of the barrier layer and separated from the back gate, so that the upper surface of the floating gate being flat with the upper surface of the side gate structure;
S3：在所述浮栅的上表面依次形成隧穿层和沟道，使所述沟道与所述浮栅 不接触设置，且使所述浮栅和所述沟道具有相反的导电类型；S3: sequentially forming a tunneling layer and a channel on the upper surface of the floating gate, so that the channel is not in contact with the floating gate, and the floating gate and the channel have opposite conductivity types;
S4：在所述沟道的上表面形成源极和漏极。S4: forming a source and a drain on the upper surface of the channel.
本发明实施例中的所述薄膜晶体管存储器的制备方法简单方便，工艺制程可以与传统的TFT工艺完全兼容，而且可以通过所述侧栅结构对薄膜晶体管存储器的所述浮栅进行能带调控，以加快电子擦除速度，降低电子擦除电压，从而可以降低功耗，而且因为所述沟道与所述浮栅不接触设置，使得该薄膜晶体管存储器相对于半浮栅薄膜晶体管存储器不容易泄漏，可靠性更强。The preparation method of the thin film transistor memory in the embodiment of the present invention is simple and convenient, the process is fully compatible with the traditional TFT process, and the energy band of the floating gate of the thin film transistor memory can be adjusted through the side gate structure, To speed up the electronic erasing speed, reduce the electronic erasing voltage, thereby reducing power consumption, and because the channel and the floating gate are not in contact with each other, the thin film transistor memory is not easy to leak compared to the semi-floating gate thin film transistor memory , the reliability is stronger.
图8为本发明实施例中背栅的剖视图。FIG. 8 is a cross-sectional view of a back gate in an embodiment of the present invention.
本发明一些具体实施例中，所述步骤S1中形成底栅结构和侧栅结构，且使所述侧栅结构设置于所述底栅结构的部分上表面以构成L型结构的背栅的步骤具体包括：In some specific embodiments of the present invention, in the step S1, a bottom gate structure and a side gate structure are formed, and the side gate structure is arranged on a part of the upper surface of the bottom gate structure to form a back gate of an L-shaped structure Specifically include:
S11：提供衬底，以作为TFT存储器的背栅100的材料；S11: providing a substrate as a material for the back gate 100 of the TFT memory;
S12：在所述衬底的上表面旋涂光刻胶，并通过其中包括曝光和显影的光刻工艺形成用于限定形状的图案；S12: Spin-coat photoresist on the upper surface of the substrate, and form a pattern for defining a shape through a photolithography process including exposure and development;
S13：采用光刻胶作为掩膜，通过干法蚀刻或者通过使用蚀刻剂溶液的湿法蚀刻形成外观呈L型的背栅100，即使所述背栅100包括底栅结构101和侧栅结构102，使所述侧栅结构102设置于所述底栅结构101的部分上表面以构成L型结构的背栅100，所得结构如图8所示。S13: Using photoresist as a mask, form an L-shaped back gate 100 by dry etching or wet etching using an etchant solution, even if the back gate 100 includes a bottom gate structure 101 and a side gate structure 102 , the side gate structure 102 is disposed on part of the upper surface of the bottom gate structure 101 to form an L-shaped back gate 100, and the obtained structure is shown in FIG. 8 .
具体的，在本实施方式中，所述衬底为低阻硅衬底、ITO衬底和表面覆盖导电薄膜的柔性衬底中的任意一种；所述干法蚀刻包括离子铣蚀刻、等离子蚀刻、反应离子蚀刻、激光烧蚀和电感耦合等离子体蚀刻中的任意一种。Specifically, in this embodiment, the substrate is any one of a low-resistance silicon substrate, an ITO substrate, and a flexible substrate whose surface is covered with a conductive film; the dry etching includes ion milling etching, plasma etching , reactive ion etching, laser ablation, and inductively coupled plasma etching.
本发明一些实施例中，所述步骤S2中在所述底栅结构的上表面依次形成阻挡层和浮栅的步骤包括：In some embodiments of the present invention, the step of sequentially forming a barrier layer and a floating gate on the upper surface of the bottom gate structure in the step S2 includes:
S21：在所述背栅的上表面沉积阻挡层材料；S21: Deposit a barrier layer material on the upper surface of the back gate;
S22：通过蚀刻工艺去除高于所述侧栅结构的上表面的所述阻挡层材料，以在所述底栅结构的上表面形成L型结构的阻挡层，且使所述阻挡层的侧部阻挡结构的上表面与所述侧栅结构的上表面相持平，在更有利于使所述浮栅和所述背栅之间形成隔断的同时，也便于制备L型结构的背栅和阻挡层。S22: Remove the material of the barrier layer higher than the upper surface of the side gate structure through an etching process, so as to form an L-shaped barrier layer on the upper surface of the bottom gate structure, and make the side portions of the barrier layer The upper surface of the barrier structure is flat with the upper surface of the side gate structure, which is more conducive to forming a partition between the floating gate and the back gate, and also facilitates the preparation of the L-shaped structure of the back gate and the barrier layer .
图9为对图8所示的背栅的上表面沉积层材料后形成的结构的剖视图；图10为对图9所示结构进行刻蚀处理形成阻挡层后的结构剖视图。FIG. 9 is a cross-sectional view of the structure formed after depositing layer materials on the upper surface of the back gate shown in FIG. 8; FIG. 10 is a cross-sectional view of the structure after etching the structure shown in FIG. 9 to form a barrier layer.
本发明一些具体实施例中，参考图9和图10，所述步骤S2中在所述底栅结构的上表面形成阻挡层的具体步骤包括：In some specific embodiments of the present invention, referring to FIG. 9 and FIG. 10 , the specific steps of forming a barrier layer on the upper surface of the bottom gate structure in step S2 include:
在背栅100的上表面沉积绝缘介质以形成初始阻挡层230，所得结构如图9所示；An insulating medium is deposited on the upper surface of the back gate 100 to form an initial barrier layer 230, and the resulting structure is shown in FIG. 9;
在所述初始阻挡层230的上表面旋涂光刻胶，并通过其中包括曝光和显影的光刻工艺形成用于限定形状的图案；spin-coating a photoresist on the upper surface of the initial barrier layer 230, and forming a pattern for defining a shape through a photolithography process including exposure and development;
再采用光刻胶作为掩膜，通过干法蚀刻或者通过使用蚀刻剂溶液的湿法蚀刻形成外观呈L型的阻挡层200，即使所述阻挡层200包括底部阻挡结构201和侧部阻挡结构202，使所述侧部阻挡结构202设置于所述底部阻挡结构201的部分上表面以构成L型结构的阻挡层200，且使所述侧部阻挡结构202与所述侧栅结构102抵持设置，所得结构如图10所示。Then use the photoresist as a mask to form an L-shaped barrier layer 200 by dry etching or wet etching using an etchant solution, even if the barrier layer 200 includes a bottom barrier structure 201 and a side barrier structure 202 The side barrier structure 202 is arranged on a part of the upper surface of the bottom barrier structure 201 to form the L-shaped barrier layer 200, and the side barrier structure 202 and the side gate structure 102 are arranged against each other , the resulting structure is shown in Figure 10.
具体的，在本实施方式中，通过原子层沉积的方法在所述背栅100的上表面形成Al 2O 3薄膜以作为阻挡层，但是本发明不限定于此，阻挡层的材料也可以是其它合适的材料，比如SiO 2、HfO 2、ZrO 2、Ta 2O 5、TiO 2、La 2O 3、HfZrO 4，或者由所述SiO 2、HfO 2、ZrO 2、Ta 2O 5、TiO 2、La 2O 3、HfZrO 4材料组成的叠层等；沉积形成所述初始阻挡层230的方法也可以是化学气相沉积、物理气相沉积、 脉冲激光沉积、电子束蒸发等；所述干法蚀刻包括离子铣蚀刻、等离子蚀刻、反应离子蚀刻、激光烧蚀和电感耦合等离子体蚀刻中的任意一种。 Specifically, in this embodiment, an Al 2 O 3 film is formed on the upper surface of the back gate 100 by atomic layer deposition as a barrier layer, but the present invention is not limited thereto, and the material of the barrier layer may also be Other suitable materials, such as SiO 2 , HfO 2 , ZrO 2 , Ta 2 O 5 , TiO 2 , La 2 O 3 , HfZrO 4 , or made of 2. A stack of La 2 O 3 , HfZrO 4 materials, etc.; the method of depositing and forming the initial barrier layer 230 may also be chemical vapor deposition, physical vapor deposition, pulsed laser deposition, electron beam evaporation, etc.; the dry method Etching includes any one of ion milling etching, plasma etching, reactive ion etching, laser ablation, and inductively coupled plasma etching.
本发明一些实施例中，所述步骤S22中在所述底栅结构的上表面形成L型结构的阻挡层之后还包括步骤：In some embodiments of the present invention, the step S22 further includes a step after forming an L-shaped barrier layer on the upper surface of the bottom gate structure:
S23：在所述阻挡层的上表面和所述侧栅结构的上表面沉积浮栅材料；S23: depositing a floating gate material on the upper surface of the barrier layer and the upper surface of the side gate structure;
S24：通过蚀刻工艺去除部分所述浮栅材料，以在所述阻挡层的上表面形成所述浮栅，且使所述浮栅的上表面、所述侧部阻挡结构的上表面和所述侧栅结构的上表面相持平，制备方法简单方便，工艺制程可以与传统的TFT工艺完全兼容。S24: Remove part of the floating gate material by etching to form the floating gate on the upper surface of the barrier layer, and make the upper surface of the floating gate, the upper surface of the side barrier structure and the The upper surface of the side gate structure is flat, the preparation method is simple and convenient, and the process is fully compatible with the traditional TFT process.
图11为本发明一些实施例中对图10所示的阻挡层的上表面进行沉积处理后形成的结构的剖视图；图12为对图11所示的结构进行刻蚀处理形成浮栅后的结构的剖视图。Fig. 11 is a cross-sectional view of the structure formed after depositing the upper surface of the barrier layer shown in Fig. 10 in some embodiments of the present invention; Fig. 12 is a structure after etching the structure shown in Fig. 11 to form a floating gate cutaway view.
本发明一些具体实施例中，参考图11和图12，所述步骤S22中在所述底栅结构的上表面形成L型结构的阻挡层之后形成浮栅的具体步骤包括：In some specific embodiments of the present invention, referring to FIG. 11 and FIG. 12 , the specific steps of forming a floating gate after forming an L-shaped barrier layer on the upper surface of the bottom gate structure in the step S22 include:
在所述阻挡层200的上表面和所述侧栅结构102的上表面沉积一层p型半导体作为初始浮栅310，所得结构如图11所示；A layer of p-type semiconductor is deposited on the upper surface of the barrier layer 200 and the upper surface of the side gate structure 102 as the initial floating gate 310, and the resulting structure is shown in FIG. 11 ;
在所述初始浮栅310的上表面涂光刻胶，并通过其中包括曝光和显影的光刻工艺形成用于限定形状的图案；Coating photoresist on the upper surface of the initial floating gate 310, and forming a pattern for defining a shape through a photolithography process including exposure and development;
再采用光刻胶作为掩膜，通过干法蚀刻或者通过使用蚀刻剂溶液的湿法蚀刻所述侧部阻挡结构202的上表面和所述侧栅结构102的上表面的部分所述初始浮栅310，以及高于所述侧部阻挡结构202的上表面的部分位置的所述初始浮栅310，以使得到的浮栅300的上表面与所述侧部阻挡结构202的上表面和所述侧 栅结构102的上表面相持平，即所述浮栅300的上表面、所述侧部阻挡结构202的上表面和所述侧栅结构102处于同一水平线，所得结构如图12所示。Using photoresist as a mask, the upper surface of the side barrier structure 202 and the part of the initial floating gate on the upper surface of the side gate structure 102 are etched by dry etching or wet etching using an etchant solution. 310, and part of the initial floating gate 310 higher than the upper surface of the side barrier structure 202, so that the upper surface of the obtained floating gate 300 is compatible with the upper surface of the side barrier structure 202 and the The upper surface of the side gate structure 102 is flat, that is, the upper surface of the floating gate 300 , the upper surface of the side barrier structure 202 and the side gate structure 102 are on the same horizontal line, and the resulting structure is shown in FIG. 12 .
在本实施方式中，参考图11，位于所述底部阻挡结构201的上表面的所述初始浮栅310的上表面与所述侧部阻挡结构202的上表面和所述侧栅结构102的上表面相持平，此时，只要刻蚀去除高于所述侧部阻挡结构202的上表面和所述侧栅结构102的上表面的部分所述初始浮栅310即可。In this embodiment, referring to FIG. 11 , the upper surface of the initial floating gate 310 located on the upper surface of the bottom barrier structure 201 and the upper surface of the side barrier structure 202 and the upper surface of the side gate structure 102 The surface is flat. At this time, it is only necessary to etch and remove the part of the initial floating gate 310 that is higher than the upper surface of the side barrier structure 202 and the upper surface of the side gate structure 102 .
具体的，在本实施方式中，通过原子层沉积的方法并采用NiO作为浮栅材料以在所述阻挡层200的上表面和所述侧栅结构102的上表面沉积形成所述初始浮栅310，但是本发明不限定于此，浮栅材料也可以是其它合适的材料，比如Cu 2O、SnO、AlSnO、p型低温多晶硅半导体材料、Pt、Pd、Ni、Au金属材料等，沉积形成所述初始浮栅310的方法也可以是化学气相沉积、物理气相沉积、脉冲激光沉积、电子束蒸发等。所述干法蚀刻包括离子铣蚀刻、等离子蚀刻、反应离子蚀刻、激光烧蚀和电感耦合等离子体蚀刻中的任意一种。 Specifically, in this embodiment, the initial floating gate 310 is deposited on the upper surface of the barrier layer 200 and the upper surface of the side gate structure 102 by atomic layer deposition using NiO as the floating gate material. , but the present invention is not limited thereto, the floating gate material can also be other suitable materials, such as Cu 2 O, SnO, AlSnO, p-type low-temperature polysilicon semiconductor materials, Pt, Pd, Ni, Au metal materials, etc., deposited to form the The method for initial floating gate 310 described above may also be chemical vapor deposition, physical vapor deposition, pulsed laser deposition, electron beam evaporation, and the like. The dry etching includes any one of ion milling etching, plasma etching, reactive ion etching, laser ablation and inductively coupled plasma etching.
图13为本发明另一些实施例中对图10所示的阻挡层的上表面进行沉积处理后形成的结构的剖视图。FIG. 13 is a cross-sectional view of a structure formed after deposition treatment is performed on the upper surface of the barrier layer shown in FIG. 10 in some other embodiments of the present invention.
本发明另一些具体实施例中，参考图13，位于所述底部阻挡结构201的上表面的所述初始浮栅310的上表面低于所述侧部阻挡结构202的上表面和所述侧栅结构102的上表面，此时，需要刻蚀去除高于所述侧部阻挡结构202的上表面和所述侧栅结构102的上表面的部分所述初始浮栅310，以及刻蚀去除部分所述侧部阻挡结构202和部分所述侧栅结构102，以使所述浮栅300的上表面、所述侧部阻挡结构202的上表面和所述侧栅结构102处于同一水平线。In other specific embodiments of the present invention, referring to FIG. 13 , the upper surface of the initial floating gate 310 located on the upper surface of the bottom barrier structure 201 is lower than the upper surface of the side barrier structure 202 and the side gate. The upper surface of the structure 102, at this time, it is necessary to etch and remove the part of the initial floating gate 310 higher than the upper surface of the side barrier structure 202 and the upper surface of the side gate structure 102, and etch and remove the portion The side barrier structure 202 and part of the side gate structure 102 are arranged so that the upper surface of the floating gate 300 , the upper surface of the side barrier structure 202 and the side gate structure 102 are at the same level.
本发明一些实施例中，所述步骤S3中在所述浮栅的上表面依次形成隧穿层和沟道的步骤包括：In some embodiments of the present invention, the step of sequentially forming a tunneling layer and a channel on the upper surface of the floating gate in the step S3 includes:
S31：在所述浮栅的上表面、所述侧部阻挡结构的上表面和所述侧栅结构的 上表面沉积隧穿层材料和沟道材料；S31: Depositing a tunneling layer material and a channel material on the upper surface of the floating gate, the upper surface of the side barrier structure, and the upper surface of the side gate structure;
S32：通过蚀刻工艺去除位于所述侧部阻挡结构的上表面和所述侧栅结构的上表面的所述隧穿层材料和所述沟道材料，使所述沟道靠近所述侧栅结构的第一侧表面和所述隧穿层靠近所述侧栅结构的第二侧表面均与所述浮栅靠近所述侧栅结构的第三侧表面持平设置，以形成所述隧穿层和所述沟道，制备方法简单方便，工艺制程可以与传统的TFT工艺完全兼容。S32: removing the tunneling layer material and the channel material located on the upper surface of the side barrier structure and the upper surface of the side gate structure through an etching process, so that the channel is close to the side gate structure The first side surface of the floating gate and the second side surface of the tunneling layer close to the side gate structure are arranged on a level with the third side surface of the floating gate close to the side gate structure, so as to form the tunneling layer and The preparation method of the channel is simple and convenient, and the process is fully compatible with the traditional TFT process.
图14为对图12所示的浮栅的上表面进行沉积处理形成初始隧穿层后的结构的剖视图；图15为对图14所示的初始隧穿层的上表面进行沉积处理形成初始沟道后的结构的剖视图；图16为对图15所示结构进行刻蚀处理形成隧穿层和沟道后的结构的剖视图。Fig. 14 is a cross-sectional view of the structure after depositing the upper surface of the floating gate shown in Fig. 12 to form an initial tunneling layer; Fig. 15 is depositing the upper surface of the initial tunneling layer shown in Fig. 14 to form an initial trench FIG. 16 is a cross-sectional view of the structure after etching the structure shown in FIG. 15 to form a tunneling layer and a channel.
本发明一些具体实施例中，参考图14、图15和图16，所述步骤S3中在所述浮栅的上表面依次形成隧穿层和沟道的具体步骤包括：In some specific embodiments of the present invention, referring to FIG. 14 , FIG. 15 and FIG. 16 , the specific steps of sequentially forming a tunneling layer and a channel on the upper surface of the floating gate in the step S3 include:
在所述所述浮栅300的上表面、所述侧部阻挡结构202的上表面和所述侧栅结构102的上表面沉积一层绝缘介质作为初始隧穿层410，所得结构如图14所示；A layer of insulating medium is deposited on the upper surface of the floating gate 300, the upper surface of the side barrier structure 202 and the upper surface of the side gate structure 102 as the initial tunneling layer 410, and the resulting structure is shown in FIG. 14 Show;
在所述初始隧穿层410的上表面沉积一层n型半导体作为初始沟道510，所得结构如图15所示；A layer of n-type semiconductor is deposited on the upper surface of the initial tunneling layer 410 as the initial channel 510, and the resulting structure is shown in FIG. 15 ;
在所述初始沟道510的上表面涂光刻胶，并通过其中包括曝光和显影的光刻工艺形成用于限定形状的图案；Coating photoresist on the upper surface of the initial trench 510, and forming a pattern for defining a shape through a photolithography process including exposure and development;
再采用光刻胶作为掩膜，通过干法蚀刻或者通过使用蚀刻剂溶液的湿法蚀刻去除位于所述侧栅结构102的上表面和所述侧部阻挡结构202的上表面的所述初始隧穿层410和所述初始沟道510，以形成只覆盖浮栅300的隧穿层400和沟道500，所得结构如图16所示。Using photoresist as a mask, remove the initial tunnels located on the upper surface of the side gate structure 102 and the upper surface of the side barrier structure 202 by dry etching or wet etching using an etchant solution. The layer 410 and the initial channel 510 are penetrated to form the tunneling layer 400 and the channel 500 covering only the floating gate 300, and the resulting structure is shown in FIG. 16 .
具体的，在本实施方式中，通过原子层沉积的方法形成Al 2O 3薄膜作为初始隧穿层，但是本发明不限定于此，隧穿层也可以是其它合适的材料，比如SiO 2、HfO 2、ZrO 2、Ta 2O 5、TiO 2、La 2O 3、HfZrO 4，或者由所述SiO 2、HfO 2、ZrO 2、Ta 2O 5、TiO 2、La 2O 3、HfZrO 4材料组成的叠层等，形成所述初始隧穿层的沉积方法也可以是化学气相沉积、物理气相沉积、脉冲激光沉积、电子束蒸发等。在本实施方式中，通过物理气相沉积的方法形成IGZO薄膜作为所述初始沟道，但是本发明不限定于此，沟道的材料也可以是其它合适的材料，比如ZnO、In 2O 3、Ga 2O 3或者n型低温多晶硅，形成所述初始沟道的沉积方法也可以是化学气相沉积、原子层沉积、脉冲激光沉积、电子束蒸发等。所述干法蚀刻包括离子铣蚀刻、等离子蚀刻、反应离子蚀刻、激光烧蚀和电感耦合等离子体蚀刻中的任意一种。 Specifically, in this embodiment, an Al 2 O 3 thin film is formed by atomic layer deposition as the initial tunneling layer, but the present invention is not limited thereto, and the tunneling layer can also be other suitable materials, such as SiO 2 , HfO 2 , ZrO 2 , Ta 2 O 5 , TiO 2 , La 2 O 3 , HfZrO 4 , or made of the SiO 2 , HfO 2 , ZrO 2 , Ta 2 O 5 , TiO 2 , La 2 O 3 , HfZrO 4 Material composition stacks, etc., the deposition method for forming the initial tunneling layer may also be chemical vapor deposition, physical vapor deposition, pulsed laser deposition, electron beam evaporation, etc. In this embodiment, the IGZO thin film is formed as the initial channel by physical vapor deposition, but the present invention is not limited thereto, and the material of the channel may also be other suitable materials, such as ZnO, In 2 O 3 , Ga 2 O 3 or n-type low-temperature polysilicon, the deposition method for forming the initial channel may also be chemical vapor deposition, atomic layer deposition, pulsed laser deposition, electron beam evaporation and the like. The dry etching includes any one of ion milling etching, plasma etching, reactive ion etching, laser ablation and inductively coupled plasma etching.
本发明一些具体实施例中，参考图1，所述步骤S4中在所述沟道的上表面形成源极和漏极的具体步骤包括：In some specific embodiments of the present invention, referring to FIG. 1, the specific steps of forming a source and a drain on the upper surface of the channel in step S4 include:
采用物理气相沉积的方法生长Au/Ti叠层，并通过光刻和刻蚀在沟道500的部分上表面分别形成源极600和漏极700，所得结构如图1所示。但是本发明不限定与此，所述源极600和漏极700的材料也可以是Au/Cr叠层或者TiAlNiAu材料。The Au/Ti stack was grown by physical vapor deposition, and a source 600 and a drain 700 were respectively formed on part of the upper surface of the channel 500 by photolithography and etching. The resulting structure is shown in FIG. 1 . However, the present invention is not limited thereto, and the material of the source electrode 600 and the drain electrode 700 may also be Au/Cr stack or TiAlNiAu material.
本发明的实施例中，当所述背栅100加正电压时，电子从所述沟道500流入所述浮栅300中，导致所述薄膜晶体管存储器的阈值电压发生变化；当所述背栅100加负电压时，由于所述背栅100在纵向存在的所述侧栅结构102通过所述阻挡层200对所述浮栅300进行能带调控，导致p型浮栅300的价带会升到n型沟道500的导带上方，这时位于浮栅300的价带的电子可以很容易通过隧穿层400直接隧穿到达沟道500的导带，从而使薄膜晶体管存储器又恢复到原始状态，即通过电子在浮栅300的流入和流出实现电荷写入和擦除两种状态。In an embodiment of the present invention, when a positive voltage is applied to the back gate 100, electrons flow from the channel 500 into the floating gate 300, causing the threshold voltage of the thin film transistor memory to change; when the back gate When a negative voltage is applied to 100, since the side gate structure 102 existing in the vertical direction of the back gate 100 regulates the energy band of the floating gate 300 through the barrier layer 200, the valence band of the p-type floating gate 300 will rise. Above the conduction band of the n-type channel 500, the electrons located in the valence band of the floating gate 300 can easily tunnel directly through the tunneling layer 400 to the conduction band of the channel 500, thereby restoring the thin film transistor memory to its original state. state, that is, two states of charge writing and erasing are realized through the inflow and outflow of electrons in the floating gate 300 .
虽然在上文中详细说明了本发明的实施方式，但是对于本领域的技术人员来 说显而易见的是，能够对这些实施方式进行各种修改和变化。但是，应理解，这种修改和变化都属于权利要求书中所述的本发明的范围和精神之内。而且，在此说明的本发明可有其它的实施方式，并且可通过多种方式实施或实现。Although the embodiments of the present invention have been described in detail above, it will be apparent to those skilled in the art that various modifications and changes can be made to the embodiments. However, it should be understood that such modifications and changes are within the scope and spirit of the present invention described in the claims. Furthermore, the invention described herein is capable of other embodiments and of being practiced or carried out in various ways.

Claims (11)

  1. 一种薄膜晶体管存储器，其特征在于，包括：A thin film transistor memory, characterized in that it comprises:
    背栅，包括底栅结构和侧栅结构，所述侧栅结构设置于所述底栅结构的部分上表面以构成L型结构；The back gate includes a bottom gate structure and a side gate structure, and the side gate structure is arranged on a part of the upper surface of the bottom gate structure to form an L-shaped structure;
    阻挡层，设置于所述底栅结构的上表面；a barrier layer disposed on the upper surface of the bottom gate structure;
    浮栅，设置于所述阻挡层的上表面，且所述浮栅与所述背栅分隔设置，所述浮栅的上表面与所述侧栅结构的上表面相持平；The floating gate is arranged on the upper surface of the barrier layer, and the floating gate is separated from the back gate, and the upper surface of the floating gate is flat with the upper surface of the side gate structure;
    隧穿层，设置于所述浮栅的上表面；a tunneling layer disposed on the upper surface of the floating gate;
    沟道，设置于所述隧穿层的上表面，所述沟道与所述浮栅不接触设置，且所述浮栅和所述沟道具有相反的导电类型；a channel disposed on the upper surface of the tunneling layer, the channel is not in contact with the floating gate, and the floating gate and the channel have opposite conductivity types;
    源极和漏极，设置于所述沟道的上表面。The source and the drain are arranged on the upper surface of the channel.
  2. 根据权利要求1所述的薄膜晶体管存储器，其特征在于，所述阻挡层包括底部阻挡结构和侧部阻挡结构，所述侧部阻挡结构设置于所述底部阻挡结构的部分上表面以构成L型结构，所述侧部阻挡结构设置于所述浮栅与所述侧栅结构之间。The thin film transistor memory according to claim 1, wherein the barrier layer comprises a bottom barrier structure and a side barrier structure, and the side barrier structure is arranged on a part of the upper surface of the bottom barrier structure to form an L-shaped structure, the side barrier structure is disposed between the floating gate and the side gate structure.
  3. 根据权利要求2所述的薄膜晶体管存储器，其特征在于，所述侧部阻挡结构的两对称侧表面分别抵持于所述浮栅和所述侧栅结构，且所述侧部阻挡结构的上表面与所述侧栅结构的上表面相持平。The thin film transistor memory according to claim 2, wherein the two symmetrical side surfaces of the side barrier structure respectively bear against the floating gate and the side gate structure, and the upper surface of the side barrier structure The surface is flat with the upper surface of the side gate structure.
  4. 根据权利要求2所述的薄膜晶体管存储器，其特征在于，所述沟道靠近所述侧栅结构的第一侧表面和所述隧穿层靠近所述侧栅结构的第二侧表面均与所述浮栅靠近所述侧栅结构的第三侧表面持平设置。The thin film transistor memory according to claim 2, wherein the first side surface of the channel close to the side gate structure and the second side surface of the tunnel layer close to the side gate structure are both in contact with the side gate structure. The floating gate is disposed flatly close to the third side surface of the side gate structure.
  5. 根据权利要求1所述的薄膜晶体管存储器，其特征在于，所述浮栅和所述沟道均采用半导体材料制作而成，所述沟道的材料为n型半导体材料，所述浮栅的材料为p型半导体材料。The thin film transistor memory according to claim 1, wherein the floating gate and the channel are both made of semiconductor material, the material of the channel is an n-type semiconductor material, and the material of the floating gate is It is a p-type semiconductor material.
  6. 根据权利要求1所述的薄膜晶体管存储器，其特征在于，所述浮栅的材料为NiO、Cu 2O、SnO、AlSnO、p型多晶硅半导体材料、Pt、Pd、Ni和Au中的任意一种。 The thin film transistor memory according to claim 1, wherein the material of the floating gate is any one of NiO, Cu2O , SnO, AlSnO, p-type polysilicon semiconductor material, Pt, Pd, Ni and Au .
  7. 根据权利要求1所述的薄膜晶体管存储器，其特征在于，所述沟道的材料为IGZO、ZnO、In 2O 3、Ga 2O 3和n型多晶硅半导体材料中的任意一种。 The thin film transistor memory according to claim 1, wherein the material of the channel is any one of IGZO, ZnO, In 2 O 3 , Ga 2 O 3 and n-type polysilicon semiconductor materials.
  8. 一种薄膜晶体管存储器的制备方法，其特征在于，包括步骤：A method for preparing a thin film transistor memory, comprising the steps of:
    S1：形成底栅结构和侧栅结构，且使所述侧栅结构设置于所述底栅结构的部分上表面以构成L型结构的背栅；S1: forming a bottom gate structure and a side gate structure, and disposing the side gate structure on a part of the upper surface of the bottom gate structure to form a back gate of an L-shaped structure;
    S2：在所述底栅结构的上表面依次形成阻挡层和浮栅，使所述浮栅设置于所述阻挡层的上表面并与所述背栅分隔设置，使所述浮栅的上表面与所述侧栅结构的上表面相持平；S2: sequentially forming a barrier layer and a floating gate on the upper surface of the bottom gate structure, so that the floating gate is arranged on the upper surface of the barrier layer and separated from the back gate, so that the upper surface of the floating gate being flat with the upper surface of the side gate structure;
    S3：在所述浮栅的上表面依次形成隧穿层和沟道，使所述沟道与所述浮栅不接触设置，且使所述浮栅和所述沟道具有相反的导电类型；S3: sequentially forming a tunneling layer and a channel on the upper surface of the floating gate, making the channel not in contact with the floating gate, and making the floating gate and the channel have opposite conductivity types;
    S4：在所述沟道的上表面形成源极和漏极。S4: forming a source and a drain on the upper surface of the channel.
  9. 根据权利要求8所述的薄膜晶体管存储器的制备方法，其特征在于，所述步骤S2中在所述底栅结构的上表面依次形成阻挡层和浮栅的步骤包括：The method for manufacturing a thin film transistor memory according to claim 8, wherein the step of sequentially forming a barrier layer and a floating gate on the upper surface of the bottom gate structure in the step S2 comprises:
    S21：在所述背栅的上表面沉积阻挡层材料；S21: Deposit a barrier layer material on the upper surface of the back gate;
    S22：通过蚀刻工艺去除高于所述侧栅结构的上表面的所述阻挡层材料，以在所述底栅结构的上表面形成L型结构的所述阻挡层，且使所述阻挡层的侧部阻挡结构的上表面与所述侧栅结构的上表面相持平。S22: removing the material of the barrier layer higher than the upper surface of the side gate structure through an etching process, so as to form the barrier layer of an L-shaped structure on the upper surface of the bottom gate structure, and make the barrier layer The upper surface of the side barrier structure is level with the upper surface of the side gate structure.
  10. 根据权利要求9所述的薄膜晶体管存储器的制备方法，其特征在于，所述步骤S22中在所述底栅结构的上表面形成L型结构的阻挡层之后还包括步骤：The method for manufacturing a thin film transistor memory according to claim 9, characterized in that, in the step S22, after forming a barrier layer of an L-shaped structure on the upper surface of the bottom gate structure, the step further includes:
    S23：在所述阻挡层的上表面和所述侧栅结构的上表面沉积浮栅材料；S23: depositing a floating gate material on the upper surface of the barrier layer and the upper surface of the side gate structure;
    S24：通过蚀刻工艺去除部分所述浮栅材料，以在所述阻挡层的上表面形成所述浮栅，且使所述浮栅的上表面、所述侧部阻挡结构的上表面和所述侧栅结构的上表面相持平。S24: Remove part of the floating gate material by etching to form the floating gate on the upper surface of the barrier layer, and make the upper surface of the floating gate, the upper surface of the side barrier structure and the The upper surface of the side gate structure is flat.
  11. 根据权利要求10所述的薄膜晶体管存储器的制备方法，其特征在于，所述步骤S3中在所述浮栅的上表面依次形成隧穿层和沟道的步骤包括：The method for manufacturing a thin film transistor memory according to claim 10, wherein the step of sequentially forming a tunneling layer and a channel on the upper surface of the floating gate in the step S3 comprises:
    S31：在所述浮栅的上表面、所述侧部阻挡结构的上表面和所述侧栅结构的上表面沉积隧穿层材料和沟道材料；S31: Deposit a tunneling layer material and a channel material on the upper surface of the floating gate, the upper surface of the side barrier structure, and the upper surface of the side gate structure;
    S32：通过蚀刻工艺去除位于所述侧部阻挡结构的上表面和所述侧栅结构的上表面的所述隧穿层材料和所述沟道材料，以形成所述隧穿层和所述沟道，使所述沟道靠近所述侧栅结构的第一侧表面和所述隧穿层靠近所述侧栅结构的第二侧表面均与所述浮栅靠近所述侧栅结构的第三侧表面持平设置。S32: removing the tunneling layer material and the channel material located on the upper surface of the side barrier structure and the upper surface of the side gate structure through an etching process, so as to form the tunneling layer and the trench channel, so that the first side surface of the channel close to the side gate structure and the second side surface of the tunneling layer close to the side gate structure are both connected to the third side surface of the floating gate close to the side gate structure The side surfaces are set flat.
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