CN103606564B - A kind of memory device structures and preparation method thereof of electrical programming-ultraviolet light erasing - Google Patents
A kind of memory device structures and preparation method thereof of electrical programming-ultraviolet light erasing Download PDFInfo
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Abstract
The present invention proposes electrical programming-ultraviolet light erasing memory device structures and preparation method thereof.Using the n type single crystal silicon piece of heavy doping as substrate, and the extraction electrode as grid；Make the electric charge barrier layer of memory with the preferable oxide-insulator of compactness；Using the more thin-film material of charge defects or nanocrystalline as electric charge capture layer；With compactness is preferable and the biggish oxide-insulator of forbidden bandwidth makees the tunnel layer of memory；It is used as the conducting channel of memory with IGZO film, active area is defined by photoetching, wet etching and forms conducting channel；By photoetching, Metal deposition and lift-off technology, the processing in source, drain electrode is completed；When test, on gate electrode plus positive pulse realizes the programming operation to device；With ultraviolet light device, while any bias is not added, realizes and device is wiped.The present invention solves the problems, such as that the TFT memory based on IGZO channel is not wiped；Improve the efficiency of erasing and operating rate of device；Expand the application space based on IGZO channel TFT memory.
Description
Technical field
The present invention relates to semiconductor integrated circuit technology fields to propose one for non-volatile flash memory
Kind electrical programming-ultraviolet light erasing memory structure and preparation method.
Background technique
System panel (SOP) technology is that multiple functions element is fully integrated on the same display panel, to obtain height
The system of performance and low cost is led in automobile, computer, consumer electronics, Military Electronics, wireless communication field and food inspection etc.
Domain is with important application prospects.Non-volatile thin film's transistor (TFT) memory not only may be used as the critical elements in SOP
For circuit-level adjustment and voltage modification, the massive store etc. of complex display parameter is applied also for, pixel in future is stored and deposited
Storage block is also expected to be directly integrated on display board, has both been able to achieve data storage, can also reduce power consumption, especially low towards those
On the portable electronic device of power consumption.It therefore, has been the heat of domestic and international scientific research personnel to the research of non-volatile TFT memory
Door topic.And amorphous indium gallium zinc oxide-semiconductor (a-IGZO) is as a kind of novel oxide semiconductor, have low temperature deposition, compared with
High electron mobility (>=10cm2/ V s) and the excellent performances such as biggish forbidden bandwidth (> 3.0eV), it is a kind of ideal
Channel material.Therefore, the non-volatile TFT memory based on IGZO channel has a good application prospect.
However, the TFT memory based on IGZO channel reported at present have the shortcomings that it is one very big: electrically erasable efficiency is very
It is low, or even cannot achieve electrically erasable.
Summary of the invention
Based on the above background, in order to solve the problems, such as that device efficiency of erasing is low, the invention proposes a kind of electrical programming-is ultraviolet
The non-volatile TFT memory structure and preparation method thereof of light erasing, i.e., wipe device using the method for ultraviolet light
It removes.In this way, not needing any back bias voltage in erasing had both been able to achieve moving to left for memory threshold voltage, to improve memory
Efficiency of erasing, improve the operating rate and stability of memory.
In order to achieve the above object, a technical solution of the invention is to provide a kind of depositing for electrical programming-ultraviolet light erasing
Memory device structure, it includes:
Use the n type single crystal silicon piece of heavy doping for substrate, and the extraction electrode as gate electrode；
Over the substrate, the insulated by oxide body thin film with good compactness is formed, as barrier oxide layer；
In the barrier oxide layer, formed it is nanocrystalline, or formed by being made with electric charge capture ability material
Film, as electric charge capture layer；
On the electric charge capture layer, being formed has good compactness and the big insulated by oxide body thin film of forbidden bandwidth,
As tunnel oxide；
On the tunnel oxide, IGZO film is formed, active area is defined based on the IGZO film and is formed and is led
Electric channel；
On the conducting channel, forms source, drain region and deposit one layer of metallic film, to form source electrode and drain electrode；
The memory device, can be in source electrode, grounded drain, by applying a positive voltage arteries and veins on gate electrode
It brings and is programmed operation；Further, it is possible to carry out erasing operation under ultraviolet light, appoint without applying on each electrode
What voltage.
With following any one or its arbitrary combination in the memory device:
The resistivity of the n type single crystal silicon piece is 0.008 ~ 0.100 Ω cm；
The barrier oxide layer is Al2O3Film or SiO2Film or HfO2Film；The film of the barrier oxide layer is thick
Degree is 20 ~ 150nm；
The electric charge capture layer is that Pt is nanocrystalline or Ru is nanocrystalline, when the electric charge capture layer is metallic nano crystal particle,
Density is 5 × 1010~5×1012 cm-2；Or the electric charge capture layer is SiNxFilm or ZnAlO film or ZnGaO are thin
Film, with a thickness of 10 ~ 50nm；
The tunnel oxide is SiO2Film or Al2O3Film；The tunnel oxide with a thickness of 5 ~ 20nm；
The IGZO film with a thickness of 10 ~ 200nm；
To form source electrode and drain electrode be Au or Al metallic film；The metallic film with a thickness of 50 ~ 250nm.
Another technical solution of the invention is to provide a kind of preparation of the memory device structures of electrical programming-ultraviolet light erasing
Method, it includes:
Surface clean is carried out to the n type single crystal silicon piece of the heavy doping as substrate, the n type single crystal silicon piece is also by as grid electricity
The extraction electrode of pole；
Over the substrate, growth has the insulated by oxide body thin film of good compactness, as barrier oxide layer；
In the barrier oxide layer, growing nano-crystal, or growth is with thin made of electric charge capture ability material
Film, as electric charge capture layer；
On the electric charge capture layer, growing has good compactness and the big insulated by oxide body thin film of forbidden bandwidth,
As tunnel oxide；
On the tunnel oxide, IGZO film is grown, active area is defined based on the IGZO film and is formed and is led
Electric channel；
On the conducting channel, forms source, drain region and deposit one layer of metallic film, to form source electrode and drain electrode；
And the test of electric property is carried out to manufactured memory device, by source electrode, grounded drain, by gate electrode
One positive voltage pulse of upper application operates to be programmed；Also, erasing operation is carried out under ultraviolet light, without
Apply any voltage on each electrode.
When preparing the memory device, based on following any one or its arbitrary combination:
The resistivity of the n type single crystal silicon piece used is 0.008 ~ 0.100 Ω cm；
The barrier oxide layer is by ALD or CVD method, the Al of growth2O3Film or SiO2Film or HfO2It is thin
Film；The film thickness of the barrier oxide layer is 20 ~ 150nm；
The electric charge capture layer is the Pt that is prepared by ALD or PVD method nanocrystalline or Ru is nanocrystalline, the charge prisoner
Obtain layer be metallic nano crystal particle when, density be 5 × 1010~5×1012 cm-2；Either pass through CVD or ALD or PVD method
The SiN of growthxFilm or ZnAlO film or ZnGaO film；When the electric charge capture layer is film, with a thickness of 10 ~ 50nm；
The tunnel oxide is by ALD or CVD method, the SiO of growth2Film or Al2O3Film；The tunnelling
Oxide layer with a thickness of 5 ~ 20nm；
It to form the IGZO film of conducting channel, is grown by ALD or PVD method, the IGZO film
With a thickness of 10 ~ 200nm；And it defines active area using photoetching and wet-etching technology and forms conducting channel；
It is that the Au deposited by electron beam evaporation method or Al are thin to form the metallic film of source electrode and drain electrode
Film；The metallic film with a thickness of 50 ~ 250nm.
In a preferred embodiment, the preparation method, it includes following steps:
Step 1: choosing the n type single crystal silicon piece for the heavy doping that resistivity is 0.008 ~ 0.100 Ω cm as substrate, and lead to
The RCA cleaning process for crossing standard cleans silicon wafer, later with the oxide layer of hydrofluoric acid removal silicon chip surface；
Step 2: on cleaned substrate, using ALD method deposit growth thickness for the Al of 20 ~ 150nm2O3Film is made
For the barrier oxide layer；In deposition process, underlayer temperature is controlled between 100 ~ 300 DEG C；Grow Al2O3Reaction source be three
Aluminium methyl and vapor；
Step 3: in the barrier oxide layer, one layer of Pt nano-crystalline granule being deposited as the charge using ALD method
Capture layer；Depositing the nanocrystalline reaction source of Pt is (MeCp) Pt (Me) 3 and O2, deposition temperature is 200 ~ 400 DEG C, deposits recurring number
It is 10 ~ 100；
Alternatively, using ALD method to deposit a layer thickness is the ZnAlO film of 10 ~ 50nm as the electric charge capture layer；It forms sediment
The reaction source of product ZnAlO film is trimethyl aluminium, diethyl zinc and vapor, and deposition temperature is 100 ~ 300 DEG C, each of deposit
ZnO and Al in growth cycle2O3Reaction cycle number ratio between 1:100 to 1:1；
Step 4: on the electric charge capture layer, the deposit of ALD method being used to grow another a layer thickness for the Al of 5 ~ 20nm2O3
Film is as the tunnel oxide；Grow Al2O3Reaction source be trimethyl aluminium and water vapour；Underlayer temperature in deposition process
Control is between 100 ~ 300 DEG C；
Step 5: on the tunnel oxide, using the method deposition thickness of magnetron sputtering for the IGZO of 50 ~ 100nm
Film is to form conducting channel；The deposit power of the IGZO film is 70W, and the group of target is divided into In:Ga:Zn:O=1:1:1:
4；
Step 6: using the method for photoetching, the region for being photo-etched glue protection is formed on the IGZO film, which is
For the active area of device；Then, using concentration is 0.01% ~ 2% hydrochloric acid, nitric acid, phosphoric acid or hydrofluoric acid as etching agent, is utilized
The method of wet etching performs etching IGZO film, and etch period is 10 ~ 600s；Photoresist is removed later, forms single device
The active area of part；
Step 7: source, drain electrode opening area using the method for photoetching in formation device；Later, pass through electron beam evaporation
Method deposits the Ti/Au metallic film that a layer thickness is 50 ~ 250nm, and source, the electric leakage of device are formed using the method for removing
Pole；
Step 8: being annealed by the way of rapid thermal annealing to device；The temperature of rapid thermal annealing is 100 ~ 400 DEG C；
Time is 1 ~ 600s；Gases used is N2。
When carrying out electrical performance testing below to manufactured memory device, the output under memory device original state is tested
Characteristic curve, to obtain the threshold voltage of device under original state；With positive voltage pulse be applied on gate electrode to device into
Row programming, and test the threshold voltage of device after different programming times；Device is wiped with the method for ultraviolet light, and is tested not
With the threshold voltage of device after the erasing time.
In conclusion proposing a kind of electrical programming-ultraviolet light wiping the invention belongs to non-volatile semiconductor memory field
Thin-film transistor memory removed and preparation method thereof.Use the n type single crystal silicon piece of heavy doping for substrate, and the extraction as grid
Electrode；Make the electric charge barrier layer of memory using the preferable oxide-insulator of compactness；Using the more film of charge defects
Material is nanocrystalline as electric charge capture layer；Using compactness, the biggish oxide-insulator of preferable and forbidden bandwidth makees memory
Tunnel layer；It is used as the conducting channel of memory using IGZO film, active area is defined simultaneously by photoetching and wet-etching technology
Form conducting channel；Source, drain region are formed by photoetching process, then deposits one layer of metal, and combine lift-off technology, it is complete
Cheng Yuan, drain electrode processing；When test, on gate electrode plus a positive voltage pulse is to realize the programming operation to device；With
Ultraviolet light device, while any bias is not added, to realize the erasing operation to device.
The present invention wipes memory using the method for ultraviolet light, is primarily due to ultraviolet lighting in IGZO ditch
A large amount of electron-hole pair is produced in road, and the hole being stimulated is had an opportunity tunnelling under the action of built in field
Into in electric charge capture layer, and then the threshold voltage of memory is made to occur obviously to move to left.Therefore, ultraviolet light, which solves, is based on
Not the problem of TFT memory of IGZO channel is not wiped；Improve the efficiency of erasing and operating rate of device；It improves and is based on
A possibility that TFT memory of IGZO channel is applied in SOP, and expand the application space of SOP.
Detailed description of the invention
Fig. 1 is IGZO channel TFT memory (abbreviation nano memory) structure based on nanocrystalline electric charge capture layer
Sectional view.
Fig. 2 is the IGZO channel TFT memory (abbreviation trapping dielectric type memory) based on trapping dielectric electric charge capture layer
The sectional view of structure.
The band structure figure that Fig. 3 is nano memory in programming, between IGZO channel and gate electrode.
The band structure figure that Fig. 4 is nano memory under erasure case, between IGZO channel and gate electrode.
Fig. 5 be nano memory at different conditions electrical programming (voltage 10V) and UV erasing after threshold voltage
Change schematic diagram.
Fig. 6 is data retention characteristics curve of the nano memory respectively after programming 10V 1ms, UV erasing 5s.
Fig. 7 is the threshold voltage window of nano memory with the variation of electrical programming and UV erasing times.
Fig. 8 is that trapping dielectric type memory carries out threshold voltage corresponding to electrical programming and UV erasing at different conditions
Variation.
Specific embodiment
The present invention is illustrated in detail with specific example with reference to the accompanying drawing.
The non-volatile TFT memory of electrical programming proposed by the present invention-ultraviolet light erasing is mainly characterized by that purple can be used
The method of outer light irradiation wipes device, does not need any applied voltage on the electrode of device when erasing.
As shown in Figure 1 or 2, memory of the present invention includes the structure of following (1) ~ (6):
(1) use the n type single crystal silicon piece of heavy doping for substrate, and the extraction electrode as gate electrode 10；For example, N-type list
The resistivity of crystal silicon chip is 0.008 ~ 0.100 Ω cm.
(2) on substrate, grow one layer of oxide dielectric material film, as memory electric charge barrier layer (or resistance
Keep off oxide layer 20)；For example, oxide dielectric material can be Al2O3、SiO2、HfO2Etc. the preferable oxide of compactness, film
With a thickness of 20 ~ 150nm, the growing method of film can be atomic layer deposition (ALD), chemical vapor deposition (CVD) etc..
(3) on electric charge barrier layer, growth charge defects more thin-film material (or trapping dielectric material) or nanometer
Crystalline substance, as electric charge capture layer (respectively 32 and 31)；For example, electric charge capture layer can be Pt(platinum) nanocrystalline, Ru(ruthenium) nanometer
The materials such as crystalline substance (see figure 1) or SiNxFilm, ZnAlO film, ZnGaO film etc. have the material of electric charge capture ability (see figure
2)；The growing method of electric charge capture layer material can be ALD, physical vapor deposit (PVD) etc..
(4) on electric charge capture layer 31 or 32, one layer of oxide dielectric material film, the tunnel layer as memory are grown
(or tunnel oxide 40)；For example, tunnel layer can be SiO2、Al2O3Etc. the oxide that compactness are good and forbidden bandwidth is big it is thin
Film, film thickness are 5 ~ 20nm, and the growing method of film can be ALD, CVD etc..
(5) on the tunneling layer, one layer of IGZO(indium gallium zinc oxide of deposit growth) film 50, the conduction band ditch as memory
Road defines active area by photoetching and wet-etching technology and forms conducting channel；For example, the thickness control of IGZO film 50 exists
Between 10 ~ 200nm, the growing method of film can be PVD, ALD etc..
(6) at conducting channel, source, drain region is formed by photoetching process, then deposit one layer of metal, and combine
Lift-off(removing) technology, form the source electrode and drain electrode 60 of device；Wherein, it is e.g. deposited by the method for electron beam evaporation
A layer thickness is the metallic film of 50 ~ 250nm, and metallic film can be the low metal material of the resistivity such as Au, Al.
When carrying out the test of electric property to the memory of above structure, it is programmed with voltage pulse pair device, with purple
Device is wiped in outer light irradiation.That is, adding a positive voltage pulse on gate electrode, by source, grounded drain, with realization pair
The programming operation of device；Device is exposed in the atmosphere of ultraviolet light, to realize the erasing operation to device, and memory is each
It does not need to apply any voltage on a electrode.
Below with two preferred embodiments, to illustrate the non-volatile TFT of electrical programming of the present invention-ultraviolet light erasing
The preparation method of memory.
Embodiment one
Step 1: choosing the n type single crystal silicon piece for the heavy doping that resistivity is 0.008 ~ 0.100 Ω cm as substrate, and lead to
The RCA cleaning process for crossing standard cleans silicon wafer, later with the oxide layer of hydrofluoric acid removal silicon chip surface.
Step 2: on cleaned silicon wafer, using the method deposit growth Al of ALD2O3Blocking of the film as memory
Oxide layer.Al2O3Film with a thickness of 20 ~ 150nm；In deposition process, underlayer temperature is controlled between 100 ~ 300 DEG C；Growth
Al2O3Reaction source be trimethyl aluminium and vapor.
Step 3: using the method for ALD in Al2O3The nanocrystalline electric charge capture as memory of one layer of Pt is deposited on film
Layer.Depositing the nanocrystalline reaction source of Pt is (MeCp) Pt (Me) 3 and O2, deposition temperature is 200 ~ 400 DEG C, and deposit recurring number is 10
~100。
Step 4: using the method for ALD, growing one layer of Al in the nanocrystalline upper deposit of Pt2O3Tunnelling oxygen of the film as device
Change layer.Al2O3Reaction source be trimethyl aluminium and water vapour, Al2O3Film with a thickness of 5 ~ 20nm；Substrate temperature in deposition process
Degree control is between 100 ~ 300 DEG C.
Step 5: using the method for magnetron sputtering, depositing IGZO film on tunnel oxide to form the conduction of memory
Channel.The deposit power of IGZO film is 70W, and the group of target is divided into In:Ga:Zn:O=1:1:1:4, with a thickness of 50 ~ 100nm.
Step 6: one layer photoresist of spin coating on IGZO film, and the area for being photo-etched glue protection is formed using the method for photoetching
Domain, the region are the active area of device.Then, use concentration for 0.01% ~ 2% hydrochloric acid, nitric acid, phosphoric acid or hydrofluoric acid conduct
Etching agent performs etching IGZO film using the method for wet etching, and etch period is 10 ~ 600s.Photoresist is removed later,
Form the active area of individual devices.
Step 7: one layer photoresist of spin coating again forms source, the drain electrode aperture of device using the method for photoetching on a photoresist
Region.Later, a layer thickness is deposited by the method for electron beam evaporation and is the Ti/Au metallic film of 50 ~ 250nm, and used
The method of lift-off forms the source of device, drain electrode.
Step 8: being annealed by the way of rapid thermal annealing (RTP) to device.The temperature of RTP is 100 ~ 400 DEG C；When
Between be 1 ~ 600s；Gases used is N2.Resulting devices cross-sectional view of the structure is as shown in Figure 1.
Step 9: the test of electric property is carried out to ready-made device.When programming, a 10V is added on the gate electrode of device
The voltage pulse of 1ms, and the source/drain of device (S/D) is held and is grounded, so that the electronics in channel IGZO passes through Fowler-
The mode of Nordheim tunnelling be tunneling to Pt it is nanocrystalline in, band structure figure such as Fig. 3 between IGZO channel and gate electrode at this time
It is shown.It is 100mW/cm with intensity when erasing2, wave-length coverage is the ultraviolet light device of 320 ~ 390nm, and irradiation time is
1s.By the irradiation of ultraviolet light, a large amount of electron-hole pair can be generated in IGZO channel, hole is under the action of built in field
Be tunneling to Pt it is nanocrystalline in, the band structure figure at this time between IGZO channel and gate electrode is as shown in Figure 4.In erase process, deposit
Any voltage is not added in the gate electrode and S/D of reservoir.
Step 10: the time used in the voltage and UV erasing during change electrical programming, and measure corresponding transfer characteristic
Curve, to obtain the variation of threshold voltage.TFT memory based on IGZO channel in original state, program 10V 0.1ms,
After 1ms, 10ms, 100ms, the threshold voltage after UV erasing 1s, 5s, 10s, 15s is as shown in Figure 5.
Step 11: testing the data retention characteristics of device.Device is programmed under conditions of 10V, 1ms, often later
The transfer characteristic that a device is surveyed at interval at regular intervals measures always 2 × 10 to obtain the threshold voltage value of device5After s
The threshold voltage of device；Device is wiped under conditions of UV, 5s, surveys a device every certain time interval later
Transfer characteristic measure 2 × 10 always to obtain the threshold voltage value of device5The threshold voltage of device after s.Fig. 6 is device
Retention performance curve, the voltage window of device is 2.56V after extrapolating 10 years in figure.
Step 12: the voltage stress characteristic during test.Programming repeatedly and erasable is carried out to device, and it is special to test output
Property, whether the threshold voltage window to confirm device is stable.Fig. 7 is repeatedly No. 100 built-in storage threshold voltages of programmed and erased
With the situation of change of program/erase number.
Embodiment two
Step 1: choosing the n type single crystal silicon piece for the heavy doping that resistivity is 0.008 ~ 0.100 Ω cm as substrate, and lead to
The RCA cleaning process for crossing standard cleans silicon wafer, later with the oxide layer of hydrofluoric acid removal silicon chip surface.
Step 2: on cleaned silicon wafer, using the method deposit growth Al of ALD2O3Blocking of the film as memory
Oxide layer. Al2O3Film with a thickness of 20 ~ 150nm；In deposition process, underlayer temperature is controlled between 100 ~ 300 DEG C；Growth
Al2O3Reaction source be trimethyl aluminium and vapor.
Step 3: using the method for ALD in Al2O3The ZnAlO film that deposit a layer thickness is 10 ~ 50nm on film, which is used as, to be deposited
The electric charge capture layer of reservoir.The reaction source for depositing ZnAlO film is trimethyl aluminium, diethyl zinc and vapor, and deposition temperature is
100 ~ 300 DEG C, ZnO and Al in each growth cycle of deposit2O3Reaction cycle number ratio between 1:100 to 1:1.
Step 4: using the method for ALD, one layer of Al of deposit growth on ZnAlO film2O3Tunnelling oxygen of the film as device
Change layer.Al2O3Reaction source be trimethyl aluminium and water vapour, Al2O3Film with a thickness of 5 ~ 20nm；Substrate temperature in deposition process
Degree control is between 100 ~ 300 DEG C.
Step 5: using the method for magnetron sputtering, depositing IGZO film on tunnel oxide to form the conduction of memory
Channel.The deposit power of IGZO film is 70W, and the group of target is divided into In:Ga:Zn:O=1:1:1:4, with a thickness of 50 ~ 100nm.
Step 6: one layer photoresist of spin coating on IGZO film, and the area for being photo-etched glue protection is formed using the method for photoetching
Domain, the region are the active area of device.Then, use concentration for 0.01% ~ 2% hydrochloric acid, nitric acid, phosphoric acid or hydrofluoric acid conduct
Etching agent performs etching IGZO film using the method for wet etching, and etch period is 10 ~ 600s.Photoresist is removed later,
Form the active area of individual devices.
Step 7: one layer photoresist of spin coating again forms source, the drain electrode aperture of device using the method for photoetching on a photoresist
Region.Later, the Ti/Au metallic film that a layer thickness is 50 ~ 250nm is deposited by the method for electron beam evaporation, and using stripping
From method form the source of device, drain electrode.
Step 8: being annealed by the way of rapid thermal annealing (RTP) to device.The temperature of RTP is 100 ~ 400 DEG C；When
Between be 1 ~ 600s；Gases used is N2.Resulting devices cross-sectional view of the structure is as shown in Figure 2.
Step 9: the test of electric property is carried out to ready-made device.The output characteristics under device original state is tested first
Curve, to obtain the threshold voltage of device under original state.It is applied on gate voltage with positive voltage pulse and device is compiled
Journey, and test the threshold voltage of device after different programming times；Device is wiped with the method for ultraviolet light, and tests different wipings
Except the threshold voltage of device after the time.Fig. 8 is the threshold voltage schematic diagram of device after different programmed and erased processes.
It is discussed in detail although the contents of the present invention have passed through above preferred embodiment, but it should be appreciated that above-mentioned
Description is not considered as limitation of the present invention.After those skilled in the art have read above content, for of the invention
A variety of modifications and substitutions all will be apparent.Therefore, protection scope of the present invention should be limited to the appended claims.
Claims (8)
1. a kind of electrical programming-memory device structures of ultraviolet light erasing, characterized by comprising:
Use the n type single crystal silicon piece of heavy doping for substrate, and the extraction electrode as gate electrode；
Over the substrate, the insulated by oxide body thin film with good compactness is formed, as barrier oxide layer；
In the barrier oxide layer, formed it is nanocrystalline, or formed with thin made of electric charge capture ability material
Film, as electric charge capture layer；
On the electric charge capture layer, the insulated by oxide body thin film with good compactness and forbidden bandwidth > 3.0eV is formed,
As tunnel oxide；
On the tunnel oxide, IGZO film is formed, active area is defined based on the IGZO film and forms conductive ditch
Road；
On the conducting channel, forms source, drain region and deposit one layer of metallic film, to form source electrode and drain electrode；
The memory device, can in source electrode, grounded drain, by gate electrode apply a positive voltage pulse come
It is programmed operation；Further, it is possible to erasing operation be carried out under ultraviolet light, without applying any electricity on each electrode
Pressure.
2. memory device structures as described in claim 1, which is characterized in that
With following any one or its arbitrary combination in the memory device:
The resistivity of the n type single crystal silicon piece is 0.008 ~ 0.100 Ω cm；
The barrier oxide layer is Al2O3Film or SiO2Film or HfO2Film；
The electric charge capture layer is that Pt is nanocrystalline or Ru is nanocrystalline or SiNxFilm or ZnAlO or ZnGaO film；
The tunnel oxide is SiO2Film or Al2O3Film；
To form source electrode and drain electrode be Au or Al metallic film.
3. memory device structures as claimed in claim 1 or 2, which is characterized in that
The film thickness of the barrier oxide layer is 20 ~ 150nm；
When the electric charge capture layer is with film made of electric charge capture ability material, with a thickness of 10 ~ 50nm；Or the electricity
When lotus capture layer is metallic nano crystal particle, density is 5 × 1010~5×1012 cm-2；
The tunnel oxide with a thickness of 5 ~ 20nm；
The IGZO film with a thickness of 10 ~ 200nm；
The metallic film with a thickness of 50 ~ 250nm.
4. a kind of electrical programming-preparation methods of the memory device structures of ultraviolet light erasing, characterized by comprising:
Surface clean is carried out to the n type single crystal silicon piece of the heavy doping as substrate, the n type single crystal silicon piece is also by as gate electrode
Extraction electrode；
Over the substrate, growth has the insulated by oxide body thin film of good compactness, as barrier oxide layer；
In the barrier oxide layer, growing nano-crystal, or growth is making with film made of electric charge capture ability material
For electric charge capture layer；
On the electric charge capture layer, the insulated by oxide body thin film with good compactness and forbidden bandwidth > 3.0eV is grown,
As tunnel oxide；
On the tunnel oxide, IGZO film is grown, active area is defined based on the IGZO film and forms conductive ditch
Road；
On the conducting channel, forms source, drain region and deposit one layer of metallic film, to form source electrode and drain electrode；
And the test of electric property is carried out to manufactured memory device, by source electrode, grounded drain, by being applied on gate electrode
Add a positive voltage pulse to be programmed operation；Also, erasing operation is carried out under ultraviolet light, without each
Apply any voltage on electrode.
5. preparation method as claimed in claim 4, which is characterized in that
When preparing the memory device, based on following any one or its arbitrary combination:
The resistivity of the n type single crystal silicon piece used is 0.008 ~ 0.100 Ω cm；
The barrier oxide layer is by ALD or CVD method, the Al of growth2O3Film or SiO2Film or HfO2Film；
The electric charge capture layer is that Pt is nanocrystalline or Ru is nanocrystalline, or passes through ALD or PVD method, the SiN of growthxIt is thin
Film or ZnAlO film or ZnGaO film；
The tunnel oxide is to grow SiO by ALD or CVD method2Film or Al2O3Film；
It to form the IGZO film of conducting channel, is grown by ALD or PVD method；And using photoetching and wet
Method etching technics defines active area and forms conducting channel；
It is Au the or Al film deposited by electron beam evaporation method to form the metallic film of source electrode and drain electrode.
6. preparation method as described in claim 4 or 5, which is characterized in that
The film thickness of the barrier oxide layer is 20 ~ 150nm；
When the electric charge capture layer is with film made of electric charge capture ability material, with a thickness of 10 ~ 50nm；Or the electricity
When lotus capture layer is metallic nano crystal particle, density is 5 × 1010~5×1012 cm-2；
The tunnel oxide with a thickness of 5 ~ 20nm；
The IGZO film with a thickness of 10 ~ 200nm；
The metallic film with a thickness of 50 ~ 250nm.
7. preparation method as claimed in claim 4, which is characterized in that comprise the steps of:
Step 1: choosing the n type single crystal silicon piece for the heavy doping that resistivity is 0.008 ~ 0.100 Ω cm as substrate, and pass through mark
Quasi- RCA cleaning process cleans silicon wafer, later with the oxide layer of hydrofluoric acid removal silicon chip surface；
Step 2: on cleaned substrate, using ALD method deposit growth thickness for the Al of 20 ~ 150nm2O3Film is as institute
State barrier oxide layer；In deposition process, underlayer temperature is controlled between 100 ~ 300 DEG C；Grow Al2O3Reaction source be trimethyl
Aluminium and vapor；
Step 3: in the barrier oxide layer, it is nanocrystalline as the electric charge capture layer that one layer of Pt being deposited using ALD method；It forms sediment
Product Pt nanocrystalline reaction source is (MeCp) Pt (Me) 3 and O2, deposition temperature is 200 ~ 400 DEG C, and deposit recurring number is 10 ~ 100；
Alternatively, using ALD method to deposit a layer thickness is the ZnAlO film of 10 ~ 50nm as the electric charge capture layer；Deposit
The reaction source of ZnAlO film is trimethyl aluminium, diethyl zinc and vapor, and deposition temperature is 100 ~ 300 DEG C, each life of deposit
ZnO and Al in long period2O3Reaction cycle number ratio between 1:100 to 1:1；
Step 4: on the electric charge capture layer, the deposit of ALD method being used to grow another a layer thickness for the Al of 5 ~ 20nm2O3Film
As the tunnel oxide；Grow Al2O3Reaction source be trimethyl aluminium and water vapour；Underlayer temperature controls in deposition process
Between 100 ~ 300 DEG C；
Step 5: on the tunnel oxide, using the method deposition thickness of magnetron sputtering for the IGZO film of 10 ~ 200nm
To form conducting channel；The deposit power of the IGZO film is 70W, and the group of target is divided into In:Ga:Zn:O=1:1:1:4；
Step 6: using the method for photoetching, the region for being photo-etched glue protection is formed on the IGZO film, which is device
The active area of part；Then, using concentration is 0.01% ~ 2% hydrochloric acid, nitric acid, phosphoric acid or hydrofluoric acid as etching agent, utilizes wet process
The method of etching performs etching IGZO film, and etch period is 10 ~ 600s；Photoresist is removed later, forms individual devices
Active area；
Step 7: source, the drain electrode opening area of device are formed using the method for photoetching；Later, it is formed sediment by the method for electron beam evaporation
The Ti/Au double-layer metal film that product a layer thickness is 50 ~ 250nm, and using the source of the method for removing formation device, drain electrode；
Step 8: being annealed by the way of rapid thermal annealing to device；The temperature of rapid thermal annealing is 100 ~ 400 DEG C；Time
For 1 ~ 600s；Gases used is N2。
8. the preparation method as described in claim 4 or 7, which is characterized in that
When carrying out electrical performance testing below to manufactured memory device, the output characteristics under memory device original state is tested
Curve, to obtain the threshold voltage of device under original state；It is applied on gate electrode with positive voltage pulse and device is compiled
Journey, and test the threshold voltage of device after different programming times；Device is wiped with the method for ultraviolet light, and tests different wipings
Except the threshold voltage of device after the time.
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| CN108257968A (en) * | 2016-12-28 | 2018-07-06 | 上海新昇半导体科技有限公司 | A kind of no pn junction p n trench gate array memory structure and preparation method thereof |
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| CN110120349A (en) * | 2019-05-15 | 2019-08-13 | 东南大学成贤学院 | The source-drain electrode and crystal tube preparation method of InGaZnO thin film transistor (TFT) |
| CN111755528A (en) * | 2020-07-31 | 2020-10-09 | 山东华芯半导体有限公司 | Flash memory unit and manufacturing method thereof |
| CN112164656B (en) * | 2020-09-24 | 2022-09-30 | 山东华芯半导体有限公司 | Method for improving performance of flash memory unit by using ITO as source and drain |
| CN112331668B (en) * | 2020-10-27 | 2022-11-29 | 复旦大学 | Visible-infrared band two-dimensional charge trapping memory and preparation method thereof |
| CN112309833A (en) * | 2020-10-30 | 2021-02-02 | 山东华芯半导体有限公司 | Flash memory unit for depositing IGZO film based on ALD (atomic layer deposition), and preparation method and application thereof |
| CN112436053A (en) * | 2020-11-23 | 2021-03-02 | 山东华芯半导体有限公司 | Flash memory unit and preparation method thereof |
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