CN101795144A - 抗干扰本地振荡器 - Google Patents
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- H03B2202/044—Reduction of undesired oscillations originated from outside noise or interferences, e.g. from parasitic couplings with circuit elements outside the oscillator the circuit element belonging to transmitter circuitry
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Abstract
本发明的名称为抗干扰本地振荡器。根据一些实施例,VCO(压控振荡器)以所需传输频率的整数倍(N)操作。VCO可以锁相在稳定参考振荡器(晶体振荡器)的整数或分数倍。VCO信号可以较高的频率被分配到多个无线电装置并且N-分频分频器可在分配放大器和Tx/Rx之间使用,使得其混频器以处于目标传输频率的本地振荡器(LO)信号工作。
Description
技术领域
本发明涉及一种抗干扰本地振荡器。
背景技术
诸如压控振荡器(VCO)的高频生成器电路被用作本地振荡器(LO)以混合信号,以便例如在无线或有线的信道上发射和/或接收信息。由于具有较高传输频率(例如,1GHz以上),很难生成“纯净”的高频信号。LO生成的常规方法具有高谐波和杂散,可使接收机不敏感且对发射机产生频谱柔性挑战(spectralcompliance challenge)。LO上的噪声可与阻断器(blocker)混合且使接收机不敏感。当在单个芯片中实现支持不同频带的各种收发机时,这可能更是一个挑战。例如,本地振荡器的多余的频谱音调(spectral tone)会干扰另一个收发机的接收机部分。
由于成本低、尺寸小和可重新配置调制带宽,直接变频发射机(directconversion transmitter)是所希望的。需要使用PLL锁相到晶体振荡器的频率生成器、即VCO来用于上变频。但是,运行在发射频率的VCO会遭受(suffer from)发射放大器的频率牵引。对于更高功率发射放大器而言,可将高功率段与VCO电路分离和屏蔽(例如金属外壳内的不同芯片)(或者VCO可以由分离的屏蔽芯片实现),以抑制从高功率发射机返回对敏感的VCO电路的干扰。很遗憾,由于成本原因,人们不太愿意使用分离的芯片,但是采用现有的方法,如果在单个芯片中实现时,VCO可能会受到更高功率段有害干扰。一些收发机解决方案已涉及将变频(conversion)分解成若干级,使得如发射功率放大器的更高功率级处于与本地振荡器中使用的VCO相比不同的频率。但这需要多于一个VCO、并且可能需要多于一个PLL。其它所谓的直接变频解决方案间接地从偏离载波频率的VCO生成LO信号。例如,如果需要6GHz的传输频率,可使用VCO生成4GHz信号,该4GHz信号可被分频以获得2GHz的分量。然后使用该4GHz和2GHz信号来获得所期望的6GHz LO信号。很遗憾,这需要附加电路(混频器等)。由于频率混合,除了所期望的6GHz分量之外,LO频谱还可能包含多余的2GHz、4GHz、8GHz等分量,在某些情况下,需要调谐电路以降低这些水平(level)。这些电路以及用于LO生成的混频器还需要大的电感器,这些电感器消耗更多的功率和芯片面积,并使该解决方案费用昂贵。因此,需要新的方法。
发明内容
本发明提供一种芯片,包括:生成信号的VCO;以及将所述信号的降频版本提供给发射混频器的分频电路,该发射混频器后接与所述VCO位于同一小片上的功率放大器。
本发明还提供一种方法,包括:用VCO以N倍于所需传输频率的频率生成信号;远离公共芯片上的所述VCO对所述信号进行N分频,并将其提供给与所述VCO位于同一芯片上的输出无线传输级放大器的混频器。
本发明还提供一种计算机***,包括:处理器;以及无线接口,耦合至所述处理器以可通信地将所述处理器链接到无线网络,所述无线接口包括至少一个片上本地振荡器,所述本地振荡器包括提供N倍于传输频率的信号的VCO,以及N分频电路,所述N分频电路将来自所述VCO的信号进行N分频以便以所述传输频率提供给与所述VCO位于同一小片上的更高功率级的混频器。
附图说明
附图中以示例性并非限制性地图示了本发明的实施例,其中类似的参考标记代表相似的元件。
图1A是根据一些实施例、具备抗干扰本地振荡器的发射机的一部分的简图。
图1B是根据一些实施例、具备抗干扰本地振荡器的接收机的一部分的简图。
图2是根据一些实施例、压控振荡器的简图。
图3A-3D示出根据一些不同实施例的电感器几何形状(geometry)。
图4是根据一些实施例、具备抗干扰LO的传输***的简图。
图5是根据一些实施例、具备功率输送***的VCO的简图。
图6是根据一些实施例、具备其中具有抗干扰LO的收发机的计算机***的简图。
具体实施方式
在一些实施例中,影响本地振荡器的干扰可以通过使用本文所公开的方法来减少。这些方法可不仅适用于低功率发射机,也可适用于中到高功率发射机。采用一些实施例,VCO(压控振荡器)在所需的传输频率的整数倍(N)上工作。VCO可以锁相在稳定参考振荡器(晶体振荡器)的整数或分数倍。VCO信号可以较高的频率被分配到多个无线电装置并且N-分频分频器可在分配放大器和Tx/Rx之间使用,使得其混频器以处于目标传输频率的本地振荡器(LO)信号工作。当VCO运行在与用于较高功率段的传输不同的(比如,更高)频率时,更容易抵抗VCO中的干扰。此外,在一些实施例中,也可以和/或备选地在VCO中使用例如硅隔离和使用抗噪电感器等技术,以便使其更加抗干扰。
图1A和1B分别示出发射机和接收机的一般框图部分,根据一些实施例,其中发射机和接收机具备抗干扰本地振荡器。它们在芯片100上并且可以是或可以不是公共收发机的一部分。它们每个包括如图所示耦合的VCO 102、N分频电路104、混频器106、放大器108和天线109。放大器108对应于通过天线来发射信号(发射机101A情况)或从天线109接收它(接收机101B情况)的更高功率放大器和/或滤波器。在发射机的情况下,基带(BB)信号与本地振荡器信号LO(Fo)混合,在放大器108的输出端生成信号(Tout(Fo))。在接收机101B的情况下,接收到的传输信号(Tin(Fo))与本地振荡器信号(LO(Fo))混合,生成基带信号(BB)。
VCO被构造成生成频率为发射所需频率的N倍大的信号。(应该注意到,术语“传输”意指发射和接收二者。即,可接收或发射处于传输频率的信号。此外,按照如此方法,传输频率指的是更高功率级的混频器或调制器处所使用的频率。取决于所利用的传输方案,如WiMax、WiFi、GPS等,它包括了发射信号可以扩展或调制(虽然在一些情况下可能轻微地扩展或调制)的方案。P分频电路可以置于VCO和以Fc(例如来自晶体时钟生成器)为参考的PLL(锁相环)之间,以便控制VCO在PFc(PFc=NFo)上运行。N分频块104将VCO生成信号(处于NFo)分频为所需的传输频率(Fo)。
在一些实施例中,如本文所述,VCO可被构造成更能抵抗来自发射信号的干扰。例如,可以采用如与高阻通道交错的多保护环的硅隔离方法,可为这些保护环使用多个不同的向下键(down-bonds),且供应给VCO的功率可以一种用以增强VCO稳定性的方式来提供。此外,由于VCO在相对高的频率操作,当采用谐振电路配置时,所用的电感器可构造得更小,且正如本文所教导的,所用的电感器可构造成对电磁干扰更有抵抗力。
图2一般示出与图1的电路一起使用的基于谐振电路(tank-based)的示范性VCO电路。它包括如图所示耦合的交叉耦合晶体管N1和N2、可变电容器C和电感器L。可通过电感器的中心抽头提供VCO的电源(VDD)。虽然任何合适的方式均可以用于基于控制信号(电压或电流,即使电路被称作压控振荡器)来控制生成频率,但是变容二极管(可变电容器,一般为电压控制的)通常用于控制谐振电路中的电容并由此控制生成频率。(谐振电路中的生成频率通常是1/[2π√(LC)]。)因此,通过在较高频率操作VCO,可以使电感器和/或电容器块(block)更小。在电感器的情况下,这可启用用于抗干扰的更灵活的电感器设计。
图3A到3D示出用于实现可能使用的平面、抗干扰电感器(集成在芯片上)的不同实施例。图3A到3C中的电感器具有端子T1和T2,且一般被设计成具有某种程度上对称的环路(环路1和环路2)。它们还可具有位于任一环路上端子之间的中心抽头。图3D的电感器是具备初级和次级绕组336和338的耦合电感器。(同样示于此图的是块段332和334,其中用于VCO的电容器组和有源电路可在芯片中相对于彼此而设置。)可以布置(或定向(orient))电感器,使得电消除(electrically cancel)环路中的干扰(否则干扰将被接收(pick up)且并入电感器的电信号中),类似于干扰遇到差分双绞线(twisted differential pair line)。即,到达电感器的辐射(radiation)耦合至两个(或多个)对称结构,且根据电路布局至少在给定的程度上抵消(cancel out)。
通过优化电感器对磁干扰方向的相对定向,可以取得干扰的最大程度消除。例如,在图3A的电感器的情况下,环路间影响电感器的干扰(如沿着分割环路的轴)将被消除最多,因为来自干扰的电信号在环路中以相反的极性生成(electrical signals from the interference are generated in opposite polarities in theloops),且彼此消除,达到两个环路中的磁场相同的程度。可以预想使用多个环,如四个或更多,类似于图3C的电感器,将产生更好的抗干扰性,因为消除的质量将较少取决于即将来临的干扰的方向。但是,实验确定,由额外干扰导致的不利因素超过减少定向敏感性的益处。无论怎样,存在许多不同的几何形状,可以采用它们来提供改进的VCO抗干扰性并且预期在本发明的范围内。同样,在给定的VCO电路中如果有必要,可使用多个上述电感。以适当的定向使用这些结构可使块间隔紧密,以便最小化面积而不牺牲性能。
还可以使用环绕电感器的屏蔽环来保护电感器免受磁干扰,屏蔽环使电流在圆环中流动。例如,低阻抗圆环可用于围住(enclose)电感器,并将使辐射接收最小化。但是应当了解,在电感器***使用这种闭合导电路径会使VCO谐振电路的Q降级。
如图3D所示的变压器(或耦合电感器)还可用于在参与频率调谐时降低耦合。VCO可包括电感器,主要由初级绕组336以及电容器组(cap bank)和有源装置334构成。次级绕组338可连接到另一个切换电容器组(switched cap bank)332或简单的开关(switch),以提供闭合回路或切换电感,以便在增强对辐射接收的抗干扰性(immunity)时增加主谐振电路的调谐范围。
图4示出收发机(发射机和/或接收机)***的简图,该***具备包括抗干扰VCO 102的抗干扰本地振荡器。VCO 102以及相位频率检测器(PFD)404、电荷泵406、缓冲器(放大器)10和P分频块412构成了以晶体时钟402作为参考的锁相环(a phase locked loop referenced off of a crystal clock 402)。为了简化,其他的电路元件已被省略。例如,可以包含用于调整频率(Fc)的组件,如用于载波恢复或将晶体参考频率与基站频率对准。此外,可以采用任意合适的PLL类型,如整数或分数类型。可以在环路内部使用∑-Δ调制以减少噪声。此外,可以在PLL中使用数字或模拟环路滤波器,或者可采用全数字PLL。缓冲器410将从VCO生成的信号(具有频率PFc)提供给高频传输线(T线)和分配放大器414,该高频传输线和分配放大器414将更高频信号馈送至一或多个收发机:收发机1至收发机M。每个收发机均包含N分频块416、混频器418和更高功率放大器420,以便将向下分频的信号(处于频率Fo)与基带(BB)信号混合。信号在VCO 102至与混频器418之间经过的距离可能相对长,并且因此以较高频率从VCO路由信号,并且一旦处于收发机则将它们向下分频至所需的发射频率是有利的。N分频块416和混频器418之间的距离也应被最小化。
再参照图1A和1B,将N分频块416置于上/下变频混频器418附近降低了从分频器416输出到低噪声放大器(例如可能干扰Rx操作的来自图1B的LNA118)对衬底的频率上耦合(With additional reference back to Figures 1A and 1B,placing the divide-by-N block 416 close to the up/down conversion mixer 418 reducesthe on-frequency coupling to the substrate from the divider 416 output to a low noiseamplifier,e.g.,LNA 118 from Figure 1B,which could interfere with Rx operation)。更高功率传输将生成泄漏回VCO的不希望有的噪声。这包括在高功率段108生成的噪声,如谐波。来自高功率放大器108的供应节点(supply node)的强二次谐波(strong second harmonics)也可耦合至VCO。可以通过降低功率放大器处的磁通量以及通过设计对该频率处的辐射接收有抵抗力的VCO来降低VCO对来自功率放大器108的噪声的敏感性。此外,可以通过使用无功元件,如电容器或LC系列共振滤波器来抑制电路中若干点的高频噪声。这些无功元件和滤波器可以被设计成使用集总元件或分布式传输线。幸运的是,滤除由于PA的调制包络而生成的较低频噪声更容易。
此外,VCO 102可包含一个或多个特征,以便使其对更高功率收发机处产生的干扰更具抵抗力。例如,可以采用在VCO中的各种、更多敏感节点处的滤波。同样,可以使用硅隔离。这可能涉及为VCO使用多于一个向下键,且可使用多个保护环以使衬底接收最小化。应当使用多个向下键将保护环固定到纯净的地(Guard rings should be tied to a clean ground using multiple down-bonds)。当使用多个保护环时,它们应该终止于不同的地和电源连接,以便避免通过受到更高噪声的地的破坏来破坏“更安静”的环。
如前所述,抗干扰电感器也可以用于降低磁耦合。而且,如下面参照图5所述,VCO的具有高电源抑制比(PSRR)的电源可用于增强VCO频率和相位稳定性(相位噪声性能)和操作。
分频比的值N可以是任意合适的数字,如2、3或某一其他数字。例如,在具备5.5GHz传输频率(Fo)的WiFi无线电装置的实施例中,N可以是2,并因此VCO可在11GHz操作。N的适当值可以基于给定设计需求来选择。该值应当被选择成在操作性能参数和电感器的尺寸之间进行了良好的折衷。小的N值意味着更简单的设计,但它通常由于电感器所需要的更大的尺寸而需要更大的芯片面积。较大的电感器尺寸也意味着可截取(intercept)更多通量线,并因此导致在VCO中对注入牵引的接收更强(result in a stronger pickup for injection pulling in theVCO)。在一些实施例中,大的N可为每个二分频操作改善VCO相位噪声6dB。随着VCO相位噪声的减小,VCO所接收的噪声(可表现为FM边带)也可减少相同的因素。但是,过大的N值导致很高的VCO频率操作,这可降低调谐范围,尽管该调谐范围可以通过使用多个VCO来进行补偿。由于电感器尺寸在高频时非常小,多个VCO不必然需要消耗过多芯片面积,且所述方法可提供纯净的本地振荡器。此外,较小的N值对功率段的抗干扰能力改善较小(a smaller Nvalue gives lower improvement in interference resistance from the power section)。如前所述,在一些实施例中,值2可能极适合。
图5示出VCO 502,它可以用作图1或4中的VCO 102。VCO包括均如图所示耦合在一起的晶体管N1、N2、电感器L、电容器组503、压控变容二极管505和LC调谐滤波器507。使用调节器的组合为VCO供电,以便为增强VCO的稳定性和抗噪性而提供合适的VDD。电源包括预调节器522,该预调节器向带隙参考(VR)524(块524也包含PTAT电流源,它用于通过向复制晶体管N3供应已调节的电流而生成参考电压)以及向高带宽调节器526供应已调节的电压源。带隙参考VR 524被构造成提供高度准确的参考电压,该参考电压对如温度变化等的环境变化相当(reasonably)不敏感。例如,它可包括如调节器的偏置电路。专用的带隙参考电路可用于确保无噪操作。与绝对温度成比例(PTAT)电路可用于消除由于温度变化而引起的电路行为的变化,因而使操作稳定并确保在温度变更下启动(A Proportional To Absolute Tempeerture circuit can be used tocancel the changes in the circuit behavior over temperature changes,thus stabilizing theoperation and ensuring startup over temperature variations)。参考调节器不仅用于向高带宽调节器526提供精确已调节参考电压(precision regulated referencevoltage),而且它向VCO提供各种偏置控制信号。例如,电容器组503的控制逻辑可以耦合到用于控制其电容的偏置信号。提供给高带宽调节器526的参考电压通过二极管连接的复制晶体管(diode-connected replica transistor)N3而生成,该晶体管N3被构造成相当匹配和接近VCO中使用的晶体管N1和N2。这使VCO的功能性对工艺偏差等不太敏感。
更高带宽调节器被构造成具有足够高的带宽,实质上比发射机的调制带宽更大,以便相对于VCO正生成的频率具有对其供电的足够的响应度(The higherbandwidth regulator is made to have a sufficiently high bandwidth substantially morethan the modulation bandwidth of the transmitter to have sufficient responsiveness forsupplying the VCO relative to the frequency that it is generating)。应对调节器进行内部补偿,以便避免如来自带线耦合(bond-wire coupling)的高频接收,且应当使其低噪声以保持相位噪声较低。通过使用分离的调节器,可以例如经由参考调节器和预调节器522来达到整体电源噪声抑制,而不必忍受有限的响应度,因为通过分离的更高带宽调节器526来获得整体电源噪声抑制。整个偏置电路专用于VCO电路,且连同VCO一起被围在先前所述保护环内,以避免通过衬底接收噪声。
VCO的变容二极管应该被设计成足够小以具有降低的VCO调谐敏感性(亦称KVCO),使得耦合至调谐线的任何噪声都具有最小的影响。小的变容二极管尺寸将提供小的、非线性的电容器并因此提供较低的相位噪声。但是,过小的变容二极管会导致两个问题。首先,Tx隙期间的任何热梯度可能改变操作频率,该操作频率通过改变调谐电压由PLL校正,小变容二极管可具有有限的频率校正且可解锁PLL,除非在电容器组中切换一个新的电容器值。其次,非常小的变容二极管可能没有足够的调谐范围来提供谐振电路的固定(例如,可切换的)电容器的足够重叠(overlap)。此外,VCO块的控制逻辑通过连同VCO一起位于保护环内的逻辑缓冲器,且这些逻辑缓冲器由保护环内的专用偏置电路生成的纯净电源供电。
参照图6,示出了计算平台的一部分(例如,如移动个人电脑、PDA、手机等等的计算***)的一个示例。表示部分包括一个或多个处理器602、集线器功能性电路604、存储器606、无线网络接口608和天线609。处理器602通过集线器功能性块604耦合至存储器606和无线网络接口608。集线器功能性可包括执行各种接口控制功能(例如,存储器控制、图形控制、I/O接口控制等等)的一个或多个电路块。这些电路可能在一个或多个分离芯片上实现和/或可部分或全部在处理器602内实现。
存储器606包括向处理器602提供附加随机存取存储器的一个或多个存储器块。它可采用任何合适的存储器来实现,包括但不限于动态随机存取存储器、静态随机存取存储器、闪存等等。无线网络接口608耦合至天线609以将处理器602无线耦合至无线网络(未示出),如无线局域网或蜂窝网络等。它包括一个或多个具备如本文所述的抗干扰VCO的收发机611。
计算机平台可实现多种不同的计算装置或其他具备计算能力的设备。这些装置包括但不限于膝上计算机、笔记本计算机、个人数字助理装置(PDA)、手机、音频和/或视频媒体播放器等等。它可以构成一个或多个完整的计算***,或者备选地它可以构成在计算***内有用的一个或多个组件。此外,框图可对应于在单个芯片上或在单个封装中实现的片上***(SOC)平台。
在前述的说明中,已提出很多具体细节。但是,应理解可以在没有这些具体细节的情况下实践本发明的实施例。在其他情况下,为了不混淆对说明的理解,公知的电路、结构和技术可能没有详细示出。了解了这点,提及的“一个实施例”、“实施例”、“示例实施例”、“各种实施例”等指如此描述的本发明的实施例可包括特定特征、结构或特性,但并非每一个实施例必然包含特定特征、结构或特性。此外,一些实施例可能具有其他实施例所描述的某些或全部特征,或不具有其他实施例所描述的任何特征。
在前述说明和后续权利要求中,下述术语应按如下理解:可能使用术语“耦合”和“连接”及其派生。应理解,这些术语并不意在彼此同义。相反,在特定实施例中,“连接”被用来表示两个或多个元件彼此直接物理或电接触。“耦合”被用来表示两个或多个元件彼此协作或交互,但它们可能或可能不直接物理或电接触。
术语“PMOS晶体管”指P型金属氧化物半导体场效应晶体管。同样,“NMOS晶体管”指N型金属氧化物半导体场效应晶体管。应当理解,无论何时使用术语“MOS晶体管”、“NMOS晶体管”或“PMOS晶体管”,除非另外明确通过它们的使用本质指示或指出,它们均以示范性方式使用。它们包括不同种类的MOS装置,包含具备不同VTs、材料类型、绝缘厚度和栅极配置的装置,此处仅列出一些。此外,除非明确称作MOS等,术语“晶体管”可包含其他合适的晶体管类型,如结型场效应晶体管、双极结型晶体管、金属半导体FET和各种类型的三维晶体管、MOS或其他当前已知的或还未开发的晶体管。
本发明并不限于所述的实施例,但可在所附的权利要求的精神和范围内通过修改和替换来实践该发明。例如,应当理解,本发明可适用与所有类型的半导体集成电路(“IC”)芯片一起使用。这些IC芯片的例子包括但不限于处理器、控制器、芯片集组件、可编程逻辑阵列(PLA)、存储器芯片、网络芯片等等。
还应理解,在某些附图中,信号导体线用线来表示。一些可能比较粗,以指示更多组成信号路径,可能具有数字标识,以指示多个组成信号路径,和/或可能在一个或多个末端有箭头,以指示主要信息流向。但是,这不应以限制方式来理解。相反,这种增加的细节可以结合一个或多个示范实施例来使用,以促使更容易理解电路。任何表示的信号线,不论是否具有附加信息,都可实际上包含一个或多个信号,所述一个或多个信号可以多个方向传播且可以任何合适类型的信号方案实现,例如,以差分对、光纤线和/或单端线实现的数字或模拟线。
应理解,可能已给出了示例尺寸/模型/取值/范围,但本发明并不限于相同的方案。随着时间的推移,制造技术(例如,光刻)变得成熟,预期可以制造更小尺寸的装置。此外,附图中可能示出或者可能没有示出至IC芯片和其他组件的公知电源/地连接,以便简化图示和表述且不致混淆本发明。此外,布置可以框图形式示出以避免混淆本发明,并且也考虑到如下事实:相对于这些框图布置的实现的细节与实现本发明所在的平台高度相关,即这些细节应为本领域技术人员所熟知。在提出特定细节(如电路)以便描述本发明的示例实施例的情况下,本领域技术人员应当明白,可以不用这些特定细节或用这些细节的变型来实践本发明。因此,说明被视为说明性的而非限制性的。
Claims (22)
1.一个芯片,包括:
生成信号的VCO;以及
将所述信号的降频版本提供给发射混频器的分频电路,该发射混频器后接与所述VCO位于同一小片上的功率放大器。
2.如权利要求1所述的芯片,其中所述分频电路是N分频电路。
3.如权利要求1所述的芯片,其中所述功率放大器生成OFDM输出传输。
4.如权利要求1所述的芯片,其中所述VCO包括具备变容二极管的谐振电路以控制所述VCO的频率。
5.如权利要求1所述的芯片,进一步包括功率调节器,所述功率调节器包括带隙参考调节器和更高带宽调节器以向所述VCO供电。
6.如权利要求5所述的芯片,其中所述参考调节器通过与所述VCO中的一个或多个晶体管匹配和邻近的晶体管而生成参考电压。
7.如权利要求1所述的芯片,其中分频值为2。
8.如权利要求1所述的芯片,其中所述VCO以超过10GHz的频率操作。
9.如权利要求1所述的芯片,其中所述VCO包括抗噪电感器。
10.如权利要求9所述的芯片,其中所述抗噪电感器包括一对或多对实质对称的环路。
11.如权利要求1所述的芯片,其中所述VCO将其生成的更高频率信号通过分配放大器提供给在所述小片上远离所述VCO的多个混频器。
12.一种方法,包括:
用VCO以N倍于所需传输频率的频率生成信号;
远离公共芯片上的所述VCO对所述信号进行N分频,并将其提供给与所述VCO位于同一芯片上的输出无线传输级放大器的混频器。
13.如权利要求12所述的方法,其中N为2。
14.如权利要求12所述的方法,其中使用具备抗噪电感器的VCO来生成所述信号。
15.如权利要求14所述的方法,包括在所述VCO处提供硅隔离。
16.如权利要求12所述的方法,其中所述VCO以超过10GHz操作。
17.一种计算机***,包括:
处理器;以及
无线接口,耦合至所述处理器以可通信地将所述处理器链接到无线网络,所述无线接口包括至少一个片上本地振荡器,所述本地振荡器包括提供N倍于传输频率的信号的VCO,以及N分频电路,所述N分频电路将来自所述VCO的信号进行N分频以便以所述传输频率提供给与所述VCO位于同一小片上的更高功率级的混频器。
18.如权利要求17所述的***,其中所述VCO包括具备变容二极管的谐振电路以控制所述VCO的频率。
19.如权利要求17所述的***,还包括功率调节器,所述功率调节器包括参考调节器和更高带宽调节器以向所述VCO供电。
20.如权利要求19所述的***,其中所述参考调节器通过与所述VCO中的一个或多个晶体管匹配和邻近的晶体管而生成参考电压。
21.如权利要求17所述的***,其中N的值为2。
22.如权利要求17所述的***,其中所述VCO以超过10GHz的频率操作。
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US12/381117 | 2009-03-06 | ||
US12/381,117 US8169271B2 (en) | 2009-03-06 | 2009-03-06 | Interference resistant local oscillator |
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US20120214429A1 (en) | 2012-08-23 |
US8169271B2 (en) | 2012-05-01 |
US20100225407A1 (en) | 2010-09-09 |
US8970314B2 (en) | 2015-03-03 |
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