CN110504308B - High-speed low-loss multi-groove-gate high-voltage power device - Google Patents
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- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7394—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET on an insulating layer or substrate, e.g. thin film device or device isolated from the bulk substrate
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- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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Abstract
The invention belongs to the technical field of power semiconductors, and particularly relates to a high-speed low-loss multi-groove-gate high-voltage power device. Compared with the traditional structure, the invention introduces a plurality of groove grid structures at the emitter end and the collector end. When the collector is conducted in the forward direction, the groove channel on the side wall of the groove gate of the collector terminal is cut off, and the communication path between the N + collector region and the N-type buffer layer is blocked, so that the voltage folding-back effect can be eliminated. The emitter end groove gate structure not only increases channel density to reduce channel region resistance, but also blocks the groove gate and the carrier storage layer to effectively improve the carrier concentration of the drift region, so that the new device can obtain lower forward conduction voltage drop. In the turn-off process, along with the rise of the voltage of the collector, the groove side wall channel of the groove grid of the collector terminal is opened, so that the N + collector region is communicated with the N-type buffer layer to form an electron rapid extraction path, and the turn-off of the device is accelerated to reduce the turn-off loss. Therefore, the invention has smaller forward conduction voltage drop and turn-off loss, and has no voltage retrace effect.
Description
Technical Field
The invention belongs to the technical field of power semiconductors, and relates to a multi-slot Gate SOI LIGBT (Lateral Insulated Gate Bipolar Transistor).
Background
An Insulated Gate Bipolar Transistor (IGBT) is a voltage-controlled bipolar conductive device, has the advantages of high input impedance, simple driving circuit, low driving power consumption, high current density of a bipolar device and low conduction voltage drop of an MOS gate control device, is one of core electronic components in the field of medium and high power, and is widely applied to the fields of rail transit, intelligent power grids, aerospace, electric automobiles, household appliances, new energy equipment and the like. Because the SOI technology has the advantages of small leakage current, easy isolation, small parasitic effect and the like, the SOI LIGBT is a core component of a monolithic power integrated chip.
The LIGBT device is a bipolar device, and high-concentration carriers stored by a conductance modulation effect in a drift region during conduction are favorable for reducing the forward conduction voltage drop (V) of the deviceon) But also results in longer tail current, slower turn-off speed and turn-off loss (E) during device turn-offoff) Becomes larger. Meanwhile, when the hole current passes through the lower part of the N + cathode region and is collected by the P + cathode region, a parasitic thyristor is easily triggered, so that Latch up effect (Latch up effect) of the device is generated, and the Safe working area (SOA) of the device is reduced. Therefore, the safe operating area SOA-forward conduction voltage drop V of the IGBTonTurn-off loss EoffThe contradictory relationship between them is always an important issue for research and development in the industry.
For reducing the forward conduction voltage drop V of the LIGBT deviceonThe folded planar gate structure is adopted in the documents of hanging Zhu, Long Zhung, Weifeng Sun, et al, Further Study of the U-Shaped Channel SOI-LIGBT with Enhanced Current sensitivity for High-Voltage Monolithic ICs, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL.63, NO.3, MARCH 2016 to increase the device Channel Density to reduce Von(ii) a However, the size of the folded gate is almost equal to the length of the drift region, so the device area utilization rate is not high, and the hole current in the planar gate structure certainly flows below the N + emitter region, so the latch-up resistance is limited. To reduce the turn-off loss E of LIGBT deviceoffShort circuited Anode (S)A) The LIGBT introduces an N + collector region at a collector terminal, and provides a rapid extraction channel of electrons during the turn-off process to accelerate the turn-off of the device and reduce EoffHowever, this also causes snapback effect in the on state of the device, which makes the device difficult to be used in parallel and reduces reliability. In order to eliminate the snapback effect, Segmented dielectric isolation grooves are introduced between a P + collector Region and an N + collector Region in documents Long Zhang, Jing Zhu, Weifeng Sun, et al.A High Current sensitivity SOI-LIGBT with Segmented Trenches in the Anode Region for providing a compressed Negative Differential Resistance response register, IEEE ISPSD,2015, and the distance between the dielectric isolation grooves is reduced to compress an electron Current path, so that the distributed Resistance is increased to eliminate the snapback effect; the trench spacing must be small enough to eliminate snapback, but the efficiency of extracting electrons during turn-off of the corresponding N + collector region is also reduced, and deep trench fabrication increases process difficulty and cost.
Disclosure of Invention
The invention aims to solve the problems and provides a multi-groove-gate SOI LIGBT.
The technical scheme of the invention is as follows: a multi-groove gate SOI LIGBT comprises a substrate layer 1, an insulating medium layer 2 and an N-type drift region 3 from bottom to top; one end of the N-type drift region 3 comprises an emitter electrode structure and an emitter electrode groove structure, and the other end of the N-type drift region comprises a collector electrode structure and a collector electrode groove structure.
The emitter structure comprises a P well region 51, a P + body contact region 61 and an N + emitter region 71; the P + body contact region 61 and the N + emission region 71 are positioned at the upper part of the P well region 51, and the common leading-out end of the P + body contact region 61 and the N + emission region 71 is an emitter; the collector structure comprises an N-type buffer layer 42, a P well region 52, a P + collector region 62, an N + collector region 72 and a body contact P + region 63 of the P well region 52, wherein the N-type buffer layer 42 is positioned on the upper part of the N-type drift region 3, the P well region 52 is positioned on the upper part of the N-type buffer layer 42, the P + collector region 62, the body contact P + region 63 and the N + collector region 72 are positioned on the upper part of the P well region 52, the body contact P + region 63 is in contact with the N + collector region 72, and the common leading-out end of the P + collector region 62, the body contact P + region 63 and the N + collector region 72 is a collector.
The method is characterized by comprising the following steps: the emitter groove structure comprises a control groove grid and a blocking groove grid, the control groove grid consists of a groove grid dielectric layer 81 and a groove grid polycrystalline silicon layer 82, two side surfaces of the control groove grid are sequentially contacted with the N + emission region 71, the P well region 51 and the N type storage layer 41 from the surface to the vertical direction in the body, and the leading-out end of the groove grid polycrystalline silicon layer 82 is a grid; the control groove gates form dense channels in a discontinuous or interconnected mode. The blocking groove grid consists of a groove grid dielectric layer 83 and a groove grid polycrystalline silicon layer 84, the blocking groove grid is positioned on one side of the control groove grid close to the collector structure, vertically penetrates through the P well region 51 from the surface and is contacted with the N-type storage layer 41, one side of the blocking groove grid close to the control groove grid is contacted with the P + body contact region 61, and the leading-out end of the groove grid polycrystalline silicon layer 84 is in short circuit with the emitter. The collector groove structure comprises a collector blocking groove grid and a collector groove grid, and the collector blocking groove grid is positioned on one side close to the emitter of the device; the collector blocking slot gate is composed of a slot dielectric layer 91 and a slot gate polycrystalline silicon layer 92, vertically penetrates through the P well region 52 from the surface and is in contact with the N-type buffer layer 42, one side of the collector blocking slot gate, close to the emitter, is in contact with the P + collector region 62, one side of the collector blocking slot gate, far from the emitter, is in contact with the N + collector region 72, and the leading-out end of the slot gate polycrystalline silicon layer 92 is short with the collector. The collector grooved gate consists of a grooved dielectric layer 93 and a grooved gate polycrystalline silicon layer 94, two side faces of the collector grooved gate are sequentially contacted with the N + collector region 72, the P well region 52 and the N-type buffer layer 42 from the surface to the vertical direction in the body, the collector grooved gate extends downwards to the N-type buffer layer 42 from the middle part of the discontinuously distributed N + collector region 72, and the leading-out end of the grooved gate polycrystalline silicon layer 94 is short with a collector; the collector groove grid forms a dense channel in an intermittent or interconnected mode.
Further, a P-type buried layer 53 is arranged below the trench gate structure.
Further, the semiconductor material includes, but is not limited to, Si, SiC, SiGe, GaAs, or GaN.
Compared with the traditional LIGBT structure, the structure has the advantages that the snapback phenomenon is effectively eliminated when the structure is conducted, the carrier injection efficiency and the anti-latch capability of the emitter terminal of the device are enhanced, and the novel structure has higher turn-off speed and lower turn-off loss.
Drawings
FIG. 1, FIG. 2, FIG. 3, FIG. 4 and FIG. 5 are schematic structural views of embodiment 1;
FIG. 6 is a schematic structural view of embodiment 2;
Detailed Description
The technical scheme of the invention is described in detail in the following with reference to the accompanying drawings and embodiments:
example 1
As shown in fig. 1, the SOI LIGBT with multi-grooved gate of this example includes a substrate layer 1, an insulating dielectric layer 2 and an N-type drift region 3 from bottom to top; one end of the N-type drift region 3 comprises an emitter electrode structure and an emitter electrode groove structure, and the other end of the N-type drift region comprises a collector electrode structure and a collector electrode groove structure.
The emitter structure comprises a P well region 51, a P + body contact region 61 and an N + emitter region 71; the P + body contact region 61 and the N + emission region 71 are positioned at the upper part of the P well region 51, and the common leading-out end of the P + body contact region 61 and the N + emission region 71 is an emitter; the collector structure comprises an N-type buffer layer 42, a P well region 52, a P + collector region 62, an N + collector region 72 and a body contact P + region 63 of the P well region 52, wherein the N-type buffer layer 42 is positioned on the upper part of the N-type drift region 3, the P well region 52 is positioned on the upper part of the N-type buffer layer 42, the P + collector region 62, the body contact P + region 63 and the N + collector region 72 are positioned on the upper part of the P well region 52, the body contact P + region 63 is in contact with the N + collector region 72, and the common leading-out end of the P + collector region 62, the body contact P + region 63 and the N + collector region 72 is a collector;
the emitter groove structure comprises a control groove gate and a blocking groove gate, the control groove gate is composed of a groove gate dielectric layer 81 and a groove gate polycrystalline silicon layer 82, two side faces of the control groove gate are sequentially contacted with the N + emission region 71, the P well region 51 and the N type storage layer 41 from the surface to the internal vertical direction, and the leading-out end of the groove gate polycrystalline silicon layer 82 is a gate. The blocking groove grid consists of a groove grid dielectric layer 83 and a groove grid polycrystalline silicon layer 84, the blocking groove grid is positioned on one side of the control groove grid close to the collector structure, vertically penetrates through the P well region 51 from the surface and is contacted with the N-type storage layer 41, one side of the blocking groove grid close to the control groove grid is contacted with the P + body contact region 61, and the leading-out end of the groove grid polycrystalline silicon layer 84 is in short circuit with the emitter. The collector groove structure comprises a collector blocking groove grid and a collector groove grid, and the collector blocking groove grid is positioned on one side close to the emitter of the device; the collector blocking slot gate is composed of a slot dielectric layer 91 and a slot gate polycrystalline silicon layer 92, vertically penetrates through the P well region 52 from the surface and is in contact with the N-type buffer layer 42, one side of the collector blocking slot gate, close to the emitter, is in contact with the P + collector region 62, one side of the collector blocking slot gate, far from the emitter, is in contact with the N + collector region 72, and the leading-out end of the slot gate polycrystalline silicon layer 92 is short with the collector. The collector grooved gate consists of a grooved dielectric layer 93 and a grooved gate polycrystalline silicon layer 94, two side faces of the grooved gate polycrystalline silicon layer are sequentially contacted with the N + collector region 72, the P well region 52 and the N-type buffer layer 42 from the surface to the vertical direction in the collector, and the leading-out end of the grooved gate polycrystalline silicon layer 94 is short with the collector. The emitter terminal control groove grid and the collector electrode groove grid are distributed discontinuously at the moment so as to increase the channel density.
The working principle of the embodiment is as follows:
when the new device is forward conducted, the N + collector region 72 is positioned at the upper part of the P well region 52, the collector blocking slot gate and the slot gate polycrystalline silicon layers 92 and 94 in the collector slot gate are in short circuit with the collector, and the slot gate channels corresponding to the collector end are all turned off, so that the access between the N + collector region 72 and the N-type buffer layer 42 is blocked, and the snapback effect is eliminated when the new device is forward conducted. The emitter end blocking groove gates and the control groove gates play a physical blocking role, the N-type storage layer 41 between the groove gates can serve as a hole barrier, holes can be prevented from being rapidly drawn away by the P + body contact region 61 through the emitter end P well region 51, the improvement of the carrier concentration of a drift region is facilitated, meanwhile, the control groove gates distributed intermittently can increase the channel density of the device to reduce the resistance of the channel region, and the device V can play a role in physical blocking under the comprehensive actiononCan be significantly reduced. Different from the traditional plane gate structure LIGBT, the emitter terminal of the new structure adopts a groove gate structure, and only a small part of hole current flows below the N + collector region 72, so that the latch-up resistance of the device can be greatly improved. In the device turn-off process, as the voltage of the collector electrode rises, the side wall channel of the collector electrode groove gate and the collector electrode barrier groove gate can be gradually opened and is buffered by an N typeThe fast extraction electron path of layer 42-trench gate sidewall trench-N + collector region 72 is opened while the emitter terminal blocking trench gate contacts P + body contact region 61 to form a hole bypass, both of which can accelerate device turn-off and reduce Eoff. Under the off state of the device, the trench gate polysilicon layers 92 and 94 in the collector trench structure and the collector short circuit are both at high potential, the trench of the trench gate side wall in the collector trench structure is opened, and the N + collector region 72 and the N-type buffer layer 42 are equivalently communicated and almost at the same potential, so that the new device structure has an MOS-like single-pole breakdown mode, and the influence of the P + collector region 62 on the withstand voltage of the device is reduced. In the aspect of process preparation, the trench gate structures of the emitter end and the collector end of the new device can be synchronously manufactured, and the N-type storage layer 41, the N-type buffer layer 42, the P well region 51 and the P well region 52 can be synchronously junction-pushed respectively so as to reduce the thermal budget cost of the device.
Compared with the traditional short-circuit anode-LIGBT structure, the novel device not only has lower on-state voltage drop and off-state loss on the premise of eliminating the snapback effect, but also improves the latch-up resistance of the device.
Fig. 2 and fig. 3 are new structures of a multi-slot-gate SOI LIGBT with an interconnection control slot gate and an interconnection collector slot gate, respectively, and fig. 4 is a new structure of a multi-slot-gate SOI LIGBT with both the interconnection control slot gate and the interconnection collector slot gate, wherein the interconnection control slot gate and the interconnection collector slot gate structure can increase channel density to further reduce the on-state voltage drop and turn-off loss of the device. FIG. 5 is a new structure of multi-grooved-gate SOI LIGBT with integrated collector blocking grooved gate and collector grooved gate.
Example 2
As shown in fig. 6, the difference between this example and fig. 1 in embodiment 1 is that a P-type buried layer 53 is introduced below the emitter terminal trench gate structure in this example. The device turn-off mechanism in this example is consistent with that in example 1, except that: when the device is conducted in the forward direction, the introduced P-type buried layer 53 can assist in depleting the N-type storage layer 41, so that the optimized doping concentration of the N-type storage layer 41 is improved, and the carrier storage effect is enhanced, therefore, the carrier concentration in the drift region of the device is higher in the current example, and the conduction voltage drop can be further reduced; meanwhile, in the blocking state, the P-type buried layer 53 can also reduce the electric field peak at the bottom of the emitter end slot structure, thereby improving the reliability of the device. Therefore, compared with embodiment 1, the new device in this example can obtain lower forward conduction voltage drop and improve the reliability of the emitter end slot structure.
Claims (2)
1. A high-speed low-loss multi-groove gate high-voltage power device comprises a substrate layer (1), an insulating dielectric layer (2) and an N-type drift region (3) from bottom to top; one end of the surface of the N-type drift region (3) is of an emitter electrode structure and an emitter electrode groove structure, and the other end of the surface of the N-type drift region is of a collector electrode structure and a collector electrode groove structure; defining the three-dimensional direction of the device by a three-dimensional rectangular coordinate system: defining the transverse direction of the device as the x-axis direction, the vertical direction of the device as the y-axis direction, and the longitudinal direction of the device, namely the third dimension direction, as the z-axis direction;
the emitter structure comprises a first P well region (51), a P + body contact region (61) and an N + emission region (71); the P + body contact region (61) and the N + emission region (71) are positioned at the upper part of the first P well region (51), and the common leading-out end of the P + body contact region (61) and the N + emission region (71) is an emitter; the N + emission regions (71) are distributed discontinuously along the z-axis direction; the collector structure comprises an N-type buffer layer (42), a second P well region (52), a P + collector region (62), an N + collector region (72) and a body contact P + region (63) of the second P well region (52), the N-type buffer layer (42) is positioned at the upper part of the N-type drift region (3), the second P well region (52) is positioned on the upper part of the N-type buffer layer (42), the P + collector region (62), the body contact P + region (63) and the N + collector region (72) are positioned on the upper part of the second P well region (52), the N + collector region (72) is respectively contacted with the body contact P + region (63) and the P + collector region (62), the body P + collector region (62) is positioned at one side close to the emitter structure, the common leading-out ends of the P + collector region (62), the body contact P + region (63) and the N + collector region (72) are collectors;
the method is characterized by comprising the following steps:
the emitter groove structure comprises a control groove grid and a blocking groove grid, the control groove grid consists of a first groove grid dielectric layer (81) and a first groove grid polycrystalline silicon layer (82) positioned in the first groove grid dielectric layer (81), the control groove grid extends downwards to the N-type drift region (3) along the middle part of the N + emission region (71), each control groove grid corresponds to one section of the N + emission region (71), and the leading-out end of the first groove grid polycrystalline silicon layer (82) is a grid electrode; the blocking groove grid consists of a second groove grid dielectric layer (83) and a second groove grid polycrystalline silicon layer (84) positioned in the second groove grid dielectric layer (83), the blocking groove grid is positioned on one side, close to the collector structure, of the P + body contact area (61), the blocking groove grid vertically penetrates through the first P well area (51) along the surface of the device and then extends into the N-type drift area (3), and the leading-out end of the second groove grid polycrystalline silicon layer (84) is in short circuit with the emitter; the bottom of the first P well region (51) on the side, far away from the collector structure, of the blocking groove gate is further provided with an N-type storage layer (41), and the N-type storage layer (41) is separated by the control groove gate along the x-axis direction;
the collector groove structure comprises a collector blocking groove grid and a collector groove grid; the collector blocking groove gate consists of a first groove dielectric layer (91) and a third groove gate polycrystalline silicon layer (92) positioned in the first groove dielectric layer (91); the N + collector region (72) is composed of a part which penetrates through the device along the z-axis direction and is positioned between the body contact P + region (63) and the P + collector region (62), and a part which is distributed discontinuously along the z-axis direction and is positioned in the body contact P + region (63); along the direction of a z axis, a collector blocking groove grid isolates a P + collector region (62) from an N + collector region (72), the collector blocking groove grid also extends downwards into an N-type buffer layer (42), and the leading-out end of a third groove grid polycrystalline silicon layer (92) is short with a collector; the collector grooved gate is composed of a second grooved dielectric layer (93) and a fourth grooved gate polycrystalline silicon layer (94) positioned in the second grooved dielectric layer (93), the collector grooved gate extends downwards to the N-type buffer layer (42) from the middle of the discontinuously distributed N + collector regions (72), each collector grooved gate corresponds to one section of the N + collector region (72), and the leading-out end of the fourth grooved gate polycrystalline silicon layer (94) is short with a collector; the collector groove grid forms a dense channel in an intermittent or interconnected mode.
2. A high speed low loss multiple trench gate high voltage power device as claimed in claim 1 wherein said emitter trench structure has a P-type buried layer (53) underneath.
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| CN111276537A (en) * | 2020-02-14 | 2020-06-12 | 电子科技大学 | Reverse conducting RC-LIGBT device with polycrystalline silicon voltage-resistant layer |
| CN111933687B (en) * | 2020-07-07 | 2023-04-18 | 电子科技大学 | Lateral power device with high safety working area |
| CN111834450B (en) * | 2020-08-31 | 2021-05-14 | 电子科技大学 | SOI LIGBT device integrated with Zener diode |
| CN111816699B (en) * | 2020-08-31 | 2021-05-14 | 电子科技大学 | SOI LIGBT device with self-adaptability |
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| CN105977302A (en) * | 2016-07-06 | 2016-09-28 | 电子科技大学 | Grooved gate MOS having buried layer structure |
| JP6620889B2 (en) * | 2016-08-10 | 2019-12-18 | 日産自動車株式会社 | Semiconductor device |
| CN106876455A (en) * | 2017-02-28 | 2017-06-20 | 电子科技大学 | A kind of double trench gate SOI LIGBT device architectures of low turn-off power loss |
| CN107768436A (en) * | 2017-10-20 | 2018-03-06 | 电子科技大学 | A kind of trench gate electric charge memory type IGBT and its manufacture method |
| CN108389900B (en) * | 2018-03-19 | 2020-05-26 | 电子科技大学 | SOI LIGBT with short-circuit anode of groove grid |
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