Embodiment
Below, with reference to accompanying drawing a plurality of embodiments of the present invention are described.Wherein, in the following description, for each key element of having added same-sign, except situation about mentioning especially, effect, function are identical.
<A: first embodiment 〉
Fig. 1 is the block diagram of the light-emitting device that relates to of first embodiment of the present invention.Light-emitting device 100 is equipped on electronic equipment as the display body of display image.As shown in Figure 1, light-emitting device 100 possesses: be arranged with the element portion 10 of a plurality of image element circuit U and drive the driving circuit 30 of each image element circuit U.Driving circuit 30 comprises: scan line drive circuit 32, signal-line driving circuit 34 and potential control circuit 36.Driving circuit 30 for example disperses to be mounted to a plurality of integrated circuit.Wherein, at least a portion of driving circuit 30 can be made of the thin film transistor (TFT) that forms on substrate.
In element portion 10, the n root signal wire 14 (m, n are natural numbers) that is formed with the m root sweep trace 12 that extends along directions X and extends along the Y direction of reporting to the leadship after accomplishing a task with directions X.A plurality of image element circuit U are configured in the place of reporting to the leadship after accomplishing a task of each sweep trace 12 and each signal wire 14, be arranged in vertical m capable * that horizontal n is listed as is rectangular.And, in element portion 10, be formed with the m root supply lines 16 that on directions X, extends with sweep trace 12.
Scan line drive circuit 32 is by becoming the sweep signal GA (GA[1]~GA[m]) of significant level (high level) to 12 outputs of each sweep trace successively with the order of regulation, and selects each image element circuit U successively with the unit of going.Potential control circuit 36 generation current potential VEL (VEL[1]~VEL[m]), and to each supply lines 16 output.
The signal S that signal-line driving circuit 34 generations are stipulated the action of image element circuit U (S[1]~S[n]), and to each signal wire 14 output.As shown in Figure 1, signal-line driving circuit 34 possesses n the unit circuit 40 corresponding with each signal wire 14.J (unit circuit 40 of j=1~n) is to j root signal wire 14 output signal S[j].For example, unit circuit 40 is with signal S[j] set the current potential corresponding (hereinafter referred to as " gradation potential ") VDATA for gray-scale value D, described gray-scale value D is to the j row image element circuit U appointment of the row of being selected by scan line drive circuit 32.
Fig. 2 is the circuit diagram of image element circuit U.In Fig. 2, only capable (1 image element circuit U of the j row of i=1~m) is that representative illustrates to belong to i.As shown in Figure 2, image element circuit U comprises light-emitting element E, driving transistors TDR, selector switch TSL and keeps capacitor C 1.Light-emitting element E and driving transistors TDR are connected in series on supply lines 16 and the path that supply lines 18 is connected.Supply with the current potential VCT of regulation to supply lines 18 (ground wire) from power circuit (omitting diagram).Light-emitting element E is organic EL (Electroluminescence) element that folder has been established the luminescent layer of organic EL Material between opposed anode and negative electrode.As shown in Figure 2, light-emitting element E is attached capacitor C 2 (capacitance cp2).
Driving transistors TDR is the N channel transistor (for example thin film transistor (TFT)) that drain electrode is connected with supply lines 16 and source electrode is connected with the anode of light-emitting element E.Keep capacitor C 1 (capacitance cp1) to be folded between the grid and source electrode of driving transistors TDR.Selector switch TSL is folded between the grid of signal wire 14 and driving transistors TDR, and both electrical connections (conduction/non-conduction) are controlled.The grid of selector switch TSL is connected with sweep trace 12.
Then,, be conceived to belong to the capable j row image element circuit U of I, the action of driving circuit 30 (driving the method for image element circuit U) is described with reference to Fig. 3.As shown in Figure 3, scan line drive circuit 32 in vertical scanning period i is selected among the period P SL, with sweep signal GA[i] set significant level for.If sweep signal GA[i] be set as significant level, the selector switch TSL that then belongs to the capable n of an i image element circuit U is varied to conducting state simultaneously.
As shown in Figure 3, select that period P SL comprises initialization period P RS, PCP and write period P WR between the amortization period.Voltage between the gate-to-source of driving transistors TDR (promptly keeping the voltage between the two ends of capacitor C 1) VGS, in initialization period P RS, be initialized to the voltage of regulation, among the PCP, asymptotic is the threshold voltage VTH of driving transistors TDR between through the amortization period after the initialization period P RS.Through writing among the period P WR after the PCP between the amortization period, the voltage VGS of driving transistors TDR is configured to and the corresponding voltage of gray-scale value D to image element circuit U appointment.In through the driving period P DR after selecting period P SL, the drive current IDR corresponding with the voltage VGS of driving transistors TDR is provided for light-emitting element E from supply lines 16 via driving transistors TDR.Light-emitting element E is luminous with the brightness corresponding with drive current IDR.Below, be divided into initialization period P RS, PCP between the amortization period, write period P WR and drive period P DR, the concrete action of image element circuit U is described.
[1] initialization period P RS (Fig. 4)
As shown in Figures 3 and 4, in initialization period P RS, signal-line driving circuit 34 is with signal S[j] set reference potential VREF1 for, potential control circuit 36 is with current potential VEL[i] set current potential V2 for.Because selector switch TSL is conducting state, so the grid potential VG of driving transistors TDR is configured to signal S[j by signal wire 14 and selector switch T SL] reference potential VREF1.And the source potential VS of driving transistors TDR is configured to current potential V2.That is, the voltage VGS of driving transistors TDR (keeping the voltages between the two ends of capacitor C 1) is initialized to the voltage VGS1 (VGS1=VREF1-V2) of the difference of reference potential VREF1 and current potential V2.
Reference potential VREF1 and current potential V2 are such shown in following mathematical expression (1), the voltage VGS1 that is configured to both differences fully is higher than the threshold voltage VTH of driving transistors TDR, and shown in mathematical expression (2), like that, be configured to the threshold voltage VTH_OLED that voltage (V2-VCT) between the two ends of light-emitting element E fully is lower than light-emitting element E.Therefore, in initialization period P RS, driving transistors TDR becomes conducting state, and light-emitting element E becomes cut-off state (non-luminance).
VGS1=VREF1-V2》VTH ……(1)
V2-VCT《VTH_OLED……(2)
[2] PCP (Fig. 5, Fig. 6) between the amortization period
As shown in Figure 3, PCP is divided into action period P CP1 and keeps period P CP2 between the amortization period.Action period P CP1 be from PCP between the amortization period starting point (terminal point of initialization period P RS) elapsed time length t1 during, keeping period P CP2 is the remaining period (till from the terminal point of action period P CP1 to the terminal point of PCP the amortization period during) of PCP between the amortization period.The time span t1 of action period P CP1 according to the gray-scale value D of image element circuit U appointment by variable setting.That is, as shown in Figure 3, gray-scale value D specifies the time span t1 of the situation of high gray scale (high brightness), specifies the time span t1 weak point of the situation of low gray scale (low-light level) than gray-scale value D.Wherein, the setting of the time span t1 of action period P CP1 will be narrated in the back.
As Fig. 3 and shown in Figure 5, when action period P CP1 began, potential control circuit 36 made the current potential VEL[i of supply lines 16] (drain potential of driving transistors TDR) be varied to current potential V1.As shown in Figure 3, current potential V1 fully is higher than current potential V2, reference potential VREF1.On the other hand, signal-line driving circuit 34 is same with initialization period P RS, with signal S[j] be maintained reference potential VREF1.Even if because selector switch TSL also keeps conducting state among the PCP between the amortization period, so the grid potential VG of driving transistors TDR is maintained in reference potential VREF1.Because driving transistors TDR move in initialization period P RS to conducting state, so on the basis of above state, as shown in Figure 5,, mobile between the drain electrode of driving transistors TDR and source electrode by the electric current I ds of following mathematical expression (3) statement.The μ of mathematical expression (3) is the mobility of driving transistors TDR.And W/L be the channel width W of driving transistors TDR with respect to the comparing of channel length L, Cox is the electric capacity of unit area of the gate insulating film of driving transistors TDR.
Ids=1/2·μ·W/L·Cox·(VGS-VTH)
2……(3)
Owing to by flowing through electric current I ds via driving transistors TDR, make to keep capacitor C 1 and capacitor C 2 to be recharged that so as shown in Figure 3, the source potential VS of driving transistors TDR slowly rises from supply lines 16.Because the grid potential VG of driving transistors TDR is fixed to reference potential VREF1, so the voltage VGS between the gate-to-source of driving transistors TDR reduces along with the rising of source potential VS.As understanding according to mathematical expression (3) like that, voltage VGS reduces more and near threshold voltage VTH, electric current I ds is minimizing more.Therefore, between the amortization period among the action period P CP1 of PCP, the voltage VGS of driving transistors TDR from the voltage VGS1 (VGS1=VREF1-V2) that among initialization period P RS, is set through the time reduce and be gradually to threshold voltage VTH.
As mentioned above, make voltage VGS be gradually to the action (hereinafter referred to as " compensating movement ") of threshold voltage VTH, before voltage VGS reaches threshold voltage VTH, stop in the starting point (having passed through the time point of time span t1 from the starting point of PCP between the amortization period) that keeps period P CP2.Voltage VGS between the gate-to-source of driving transistors TDR is configured to keep the voltage VGS2 of the time point that the starting point of period P CP2 arrives.The stopping and to describe in detail below of compensating movement.
As Fig. 3 and shown in Figure 6, if keep period P CP2 to begin, then signal-line driving circuit 34 makes signal S[j] be varied to reference potential VREF2.Reference potential VREF2 is lower than reference potential VREF1.Because selector switch TSL continues to keep conducting state after action period P CP1, so grid potential VG of driving transistors TDR, in the beginning that keeps period P CP2, the reference potential VREF1 from action period P CP1 changes (reduction) and becomes reference potential VREF2.
Keep capacitor C 1 owing between the grid of driving transistors TDR and source electrode, be folded with, so as shown in Figure 3, the source potential VS of driving transistors TDR and grid potential VG interlock variation (reduction).The variable quantity of the current potential VS at the starting point place of maintenance period P CP2 is equivalent to according to keeping the capacitor C 1 and the capacity ratio of capacitor C 2 the variation delta V REF (Δ V REF=VREF1-VREF2) of current potential VG to be cut apart the voltage (Δ VREFcp1/ (cp1+cp2)) that obtains.Therefore, keep the voltage VGS3 of period P CP2 after just having begun, can utilize the voltage VGS2 between the gate-to-source of driving transistors TDR of destination county of action period P CP1, as following mathematical expression (4), explain.
VGS3=VGS2-ΔVREF·cp2/(cp1+cp2)……(4)
The voltage VGS3 that reference potential VREF2 is configured to mathematical expression (4) is lower than the threshold voltage V TH of driving transistors TDR.Therefore, by in keeping period P CP2, making the grid potential VG of driving transistors TDR be varied to reference potential VREF2, make driving transistors TDR migration be cut-off state.Promptly, make voltage VGS be gradually to the compensating movement of threshold voltage VTH by in driving transistors TDR, flowing through electric current I ds, stop in the beginning that keeps period P CP2, the voltage VGS of driving transistors TDR is retained the voltage VGS3 of mathematical expression (4) till the terminal point that keeps period P CP2.
[3] write period P WR (Fig. 7)
As Fig. 3 and shown in Figure 7, begin if write period P WR, then signal-line driving circuit 34 makes signal S[j] be varied to gradation potential VDATA.Gradation potential VDATA is according to the gray-scale value D of image element circuit U (light-emitting element E) appointment and by variable setting.Even if because selector switch TSL also keeps conducting state in writing period P WR, so the grid potential VG of driving transistors TDR is varied to gradation potential VDATA from the reference potential VREF2 that is set during keeping period P CP2.Then, the source potential VS of driving transistors TDR and current potential VG interlock change.Write the variable quantity that period P WR has just begun current potential VS afterwards, be equivalent to according to keeping the capacitor C 1 and the capacity ratio of capacitor C 2 the variation delta V (Δ V=VDATA-VREF2) of current potential VG to be cut apart the voltage (Δ Vcp1/ (cp1+cp2)) that obtains.
Therefore, follow the voltage VGS4 that (keeps between the two ends of capacitor C 1) between the gate-to-source that writes period P WR driving transistors TDR afterwards closely, stated as following mathematical expression (5).As noted above, be set according to gradation potential VDATA (more specifically being the difference of gradation potential VDATA and reference potential VREF1) by voltage VGS4, make driving transistors TDR become conducting state.
VGS4=VGS3+ΔV·cp2/(cp1+cp2)
={VGS2-ΔVREF·cp2/(cp1+cp2)}+ΔV·cp2/(cp1+cp2)
=VGS2+{-(VREF1-VREF2)+(VDATA-VREF2)}·cp2/(cp1+cp2)
=VGS2+(VDATA-VREF1)·cp2/(cp1+cp2)……(5)
[4] drive period P DR (Fig. 8)
As Fig. 3 and shown in Figure 8, begin if drive period P DR, then scan line drive circuit 32 makes sweep signal GA[i] be varied to inactive level (low level).Therefore, the selector switch TSL of each image element circuit U that i is capable is changed to cut-off state.That is, the grid of driving transistors TDR becomes electric quick condition (that is, supply with at the current potential of the grid of driving transistors TDR stop).On the other hand, by in writing period P WR, flowing through the electric current I ds of mathematical expression (3) between the drain electrode-source electrode of migration, make capacitor C 2 be recharged for the driving transistors TDR of conducting state.Therefore, be maintained at the voltage VGS of driving transistors TDR under the state of voltage VGS4 of formula (5), the voltage between the two ends of capacitor C 2 (the source potential VS of driving transistors TDR) slowly increases.Then, the voltage between the two ends of capacitor C 2 has reached the time point of the threshold voltage VTH_OLED of light-emitting element E, and electric current I ds is provided for light-emitting element E as drive current IDR.Therefore, drive current IDR is stated as following mathematical expression (6).
IDR=1/2·μ·W/L·Cox·(VGS4-VTH)
2……(6)
As mentioned above, owing to drive current IDR is controlled so as to and the corresponding magnitude of current of voltage VGS4 that has reflected gradation potential VDATA, so light-emitting element E is luminous with the brightness corresponding with gradation potential VDATA (being gray-scale value D).The luminous sweep signal GA[i that continues to of light-emitting element E] next become till the beginning of selection period P SL of significant level.It more than is the action of image element circuit U.
Then, Fig. 9 is the relevant curve map that time span t1 that expression continues compensating movement is fixed as gradation potential VDATA and the error of the magnitude of current of drive current IDR in the formation (hereinafter referred to as " Comparative Examples ") of setting.The transverse axis of Fig. 9 represents with reference potential VREF1 to be the magnitude of voltage of the gradation potential VDATA of reference value (0.0), compare (the maximum error ratio) of the maximal value of the magnitude of current of the drive current IDR the when longitudinal axis of Fig. 9 has represented to specify same grayscale value D and minimum value.The voltage VGS that time span t1 in the Comparative Examples is configured to driving transistors TDR reaches the required enough time spans of threshold voltage VTH.
According to Fig. 9 as can be known, be made as at the time span t1 with compensating movement under the situation of fixed value, when gradation potential VDATA was set as setting VD0, the error of drive current IDR was lowered really, but gradation potential VDATA is more away from setting VD0, and the error of drive current IDR increases more.That is, in Comparative Examples, exist this problem of error that the broad range that is difficult to spread all over gradation potential VDATA is eliminated drive current IDR.
Figure 10 is that (VD1<VD2<VD3<VD4<VD5) illustrates the curve map of relation of the error (maximum error than) of the time span t1 of action period P CP1 and the drive current IDR of the manner at a plurality of situations that gradation potential VDATA is changed.The error of drive current IDR is the time span t1 of the minimum trend different according to gradation potential VDATA, can be as can be seen from Figure 10.That is, gradation potential VDATA is high more, and the error of drive current IDR is that the time span t1 of minimum is just short more.
According to above viewpoint, in the manner,, come the error of controlling and driving electric current I DR and irrelevant with gradation potential VDATA by set the time span t1 of action period P CP1 changeably according to gray-scale value D (gradation potential VDATA).Figure 11 is expression gradation potential VDATA and the curve map of the relation of the time span t1 of action period P CP1.As shown in figure 11, high more (promptly according to gradation potential VDATA, the variable quantity of grid potential VG that writes the driving transistors TDR of period P WR after just having begun is big more), the short more mode of time span t1 of action period P CP1 is according to gradation potential VDATA setting-up time length t1.For example, when in writing period P WR, gradation potential VDATA being set at the current potential VD1 of Figure 10, action period P CP1 is set as time span T1, being set as at gradation potential VDATA under the situation of the current potential VD2 that is higher than current potential VD1, is the situation that action period P CP1 is set as the time span T2 shorter than time span T1.
But, because gradation potential VDATA is low more, be used to make the time span t1 of error minimize of drive current IDR long more, so, if under the enough low situation of gradation potential VDATA (for example designated the situation of minimum gray scale), also the error of drive current IDR will be minimized fully, then needs to set time span t1 for long time.Therefore, as shown in figure 11, the signal-line driving circuit 34 of the manner (the time adjustment part 46 of unit circuit 40) is set the setting t max that (clip) becomes not rely on gray-scale value D with the time span t1 of action period P CP1 under the designated situation (gradation potential VDATA is lower than the situation of the current potential VD_th of Figure 11) that is lower than the gray-scale value D of setting.The voltage VGS that maximal value t max is constrained to than driving transistors TDR is reduced to the short time of the required time span of threshold voltage VTH by compensating movement.According to above formation, can shorten PCP between the amortization period (and then shorten and select period P SL).
As described with reference to Figure 3, the compensating movement among the action period P CP1 is by signal S[j] (the grid potential VG of driving transistors TDR) be changed to reference potential VREF2 from reference potential VREF1 and finish.Therefore, the constituent parts circuit 40 of signal-line driving circuit 34 by according to gray-scale value D to making signal S[j] adjust from the time that reference potential VREF1 is changed to reference potential VREF2, come the time span t1 of control action period P CP1 changeably.
Figure 12 is the block diagram of the unit circuit 40 of signal-line driving circuit 34.In Figure 12, only illustrate typically generate and output signal S[j] 1 unit circuit 40.As shown in figure 12, unit circuit 40 comprises: current potential generating unit 42, current potential selection portion 44 and time adjustment part 46.The gray-scale value D of j image element circuit U is provided for current potential generating unit 42 and time adjustment part 46.
Current potential generating unit 42 generates the gradation potential VDATA corresponding with gray-scale value D.For example, the D/A converter of voltage output type is used as current potential generating unit 42.The gradation potential VDATA that current potential selection portion 44 is supplied to the reference potential VREF1 that generated by power circuit (diagram slightly) and reference potential VREF2 and is generated by current potential generating unit 42.Current potential selection portion 44 optionally with any one of reference potential VREF1, reference potential VREF2 and gradation potential VDATA as signal S[j] to signal wire 14 outputs.If be described in further detail, then current potential selection portion 44 is at initialization period P RS and output reference current potential VREF1 among the action period P CP1 of PCP between the amortization period, output reference current potential VREF2 among the maintenance period P CP2 of PCP between the amortization period, output gray level current potential VDATA in writing period P WR.
Time adjustment part 46 according to gray-scale value D changeably CONTROLLED POTENTIAL selection portion 44 make signal S[j] current potential be altered to period (being the action period P CP1 and the border that keeps period P CP2 of PCP between the amortization period) of reference potential VREF2 from reference potential VREF1.For example, the starting point of PCP begins to count and has reached time point (having begun to pass through the time point of time span t1 from counting) with gray-scale value D value corresponding in count value between the amortization period, (counter of indication of VREF1 → VREF2) is used as time adjustment part 46 to the switching of current potential selection portion 44 output potentials.Set maximal value t max the higher limit this point of time span t1 for about time adjustment part 46, as previously mentioned.
The time span t1 of action period P CP1 is on the basis of above formation, according to gray-scale value D (gradation potential VDATA) Be Controlled.Because it is short that time span t1 is configured to be reduced to the required time of threshold voltage VTH than the voltage VGS of driving transistors TDR from the voltage VGS1 of the destination county of initialization period P RS, so the voltage VGS2 between the gate-to-source of the driving transistors TDR of the destination county of action period P CP1 does not reach threshold voltage VTH and changes corresponding to time span t1.Therefore, the action of the time span t1 of action period P CP1 being controlled according to gray-scale value D, also as according to gray-scale value D changeably the action of the voltage VGS2 of the destination county of control action period P CP1 held.Wherein, the time span of the integral body of PCP is fixed between the amortization period.Therefore, CP1 is long more for the action period P, keeps period P CP2 just short more.
Need to prove that the main cause of the error of drive current IDR is the threshold voltage VTH of driving transistors TDR and the error of mobility [mu].At present,, need as disclosure described in Patent Document 1, make the voltage VGS of driving transistors TDR consistent among the PCP between the amortization period with threshold voltage VTH in order only to compensate the error of threshold voltage VTH.In the manner, though between the amortization period in the PCP voltage VGS of driving transistors TDR do not reach threshold voltage VTH, as shown in figure 10, the error of drive current IDR is suppressed really by the adjustment of time span t1.And voltage VGS between the amortization period, do not reach among the PCP threshold voltage VTH irrespectively the error of drive current IDR be suppressed, this be because, except the error of threshold voltage VTH, the error of mobility [mu] also can be compensated by the adjustment of time span t1.That is, in the manner, the mode that is compensated according to threshold voltage VTH and the mobility [mu] both sides of driving transistors TDR, control time length t1 changeably.
Figure 13 is the gradation potential VDATA of expression in the manner and the curve map of the relation (solid line) of the error of drive current IDR.In Figure 13, with dashed lines has been represented relevant (Fig. 9) with the error of drive current IDR of the gradation potential VDATA in the Comparative Examples in the lump.As shown in figure 13, according to the manner, the formation of the patent documentation 1 that is fixed with the time span of compensating movement is compared, and the error with the broad range drive current IDR that spreads all over gradation potential VDATA is suppressed this advantage.
Wherein, the zone of the low level side of the gradation potential VDATA in Figure 13, the error of drive current IDR increase a little, can consider it is that the restriction of the upper limit of time span t1 is the influence of maximal value t max.As mentioned above, if drive current IDR produces error in low gray scale side, then for example specify under the minimum gray scale situation of (the black demonstration) at gray-scale value D, the magnitude of current of drive current IDR should be set at zero haveing nothing to do with former, have and drive current IDR may take place be provided for this phenomenon of light-emitting element E (then, light-emitting element E is luminous).Consider above situation, in the manner, the gradation potential VDATA during designated minimum gray scale is set to the current potential Vmin (with reference to Figure 11) that is lower than reference potential VREF1.According to above formation, designated under the situation of minimum gray scale, because the voltage VGS of driving transistors TDR is lower than threshold voltage VTH really, so the time span t1 restriction of period P CP1 is irrelevant for the formation of maximal value t max with moving, have can infalliblely will be designated the magnitude of current of drive current IDR during minimum gray scale be set at zero this advantage.
<B: second embodiment 〉
Then, second embodiment of the present invention is described.If when writing period P WR and beginning, the voltage VGS between the gate-to-source of driving transistors TDR is configured to the voltage VGS4 of mathematical expression (5), then flows through the electric current I ds of mathematical expression (3) between drain electrode-source electrode of driving transistors TDR.Be accompanied by the maintenance capacitor C 1 based on electric current I ds, the charging of capacitor C 2, the source potential VS of driving transistors TDR (voltages between the two ends of capacitor C 2) rises.In the first embodiment, supposed to write the degree that period P WR is short to the rising that can ignore the current potential VS that is caused by the charging that writes in the period P WR.In the manner, consider to write the rising of the current potential VS among the period P WR.
As shown in figure 14, if writing the voltage VGS4 that voltage VGS that period P WR just begun rear drive transistor T DR is configured to mathematical expression (5), then in the charging based on electric current I ds, the source potential VS of driving transistors TDR slowly rises.Because the grid potential VG of driving transistors TDR is maintained in gradation potential VDATA, so the voltage VGS between the gate-to-source of driving transistors TDR reduces in the rising of source potential VS.That is, as shown in figure 14, make voltage VGS be gradually to the compensating movement of threshold voltage VTH, except action period P CP1, in writing period P WR, also be performed.
Consider action period P CP1 and write compensating movement among the period P WR both sides, in the manner, based on the time span t1 and the summation T that writes the time span t2 of period P WR of action period P CP1, decision and gradation potential VDATA time corresponding length t1.If be described in further detail, then for each of a plurality of gradation potential VDATA, by experiment or calculate (simulation) and determine the summation T of the error of drive current IDR for minimum, the difference of summation T and time span t2 (fixed value) is determined as moving the time span t1 of period P CP1.
Figure 15 is the gradation potential VDATA of expression in the manner and the curve map of the relation of the error of drive current IDR.In Figure 15, with dashed lines has been represented relevant (Figure 13) of gradation potential VDATA and the error of drive current IDR in first embodiment in the lump.In the manner, change owing to the voltage VGS that also considers to cause by the compensating movement that writes in the period P WR, set the time span t1 of action period P CP1, so as shown in figure 15, compare with first embodiment of having ignored the compensating movement that writes among the period P WR, can reduce the error of drive current IDR.
<C: the 3rd embodiment 〉
Figure 16 is the circuit diagram of the image element circuit U in the 3rd embodiment of the present invention.As shown in figure 16, the image element circuit U of the manner is the formation of having appended gauge tap T CR in the image element circuit U of first embodiment.Gauge tap T CR is configured on the path of the electric current I ds (drive current IDR) between drain electrode-source electrode of driving transistors TDR.For example, as shown in figure 16, the N channel transistor that folder is established between the drain electrode of driving transistors TDR and supply lines 16, TCR is utilized as gauge tap.If gauge tap TCR migration is conducting state, then the path of electric current I ds is established, if gauge tap TCR migration is cut-off state, then the path of electric current I ds is blocked.
In element portion 10, be formed with the m root control line 52 that together extends with sweep trace 12 along directions X.As shown in figure 16, the control line 52 that the grid of the gauge tap TCR among each image element circuit U that i is capable and i are capable is connected.Supply with control signal GB (GB[1]~GB[m]) from driving circuit 30 (for example scan line drive circuit 32) to each control line 52.
Figure 17 is used for sequential chart that the action that belongs to the capable j row image element circuit U of i is described.As shown in figure 17, control signal GB[i] writing in the capable selection period P SL of i be configured to inactive level (low level) among the period P WR, in (initialization period P RS, PCP, driving period P DR between the amortization period), be configured to significant level (high level) during beyond this writes period P WR.Therefore, by at initialization period P RS, PCP and drive among the period P DR gauge tap TCR is maintained in conducting state between the amortization period, the path of electric current I ds is established, and by set gauge tap TCR for cut-off state in writing period P WR, electric current I ds is blocked.
As mentioned above, because electric current I ds is blocked (promptly keeping capacitor C 1, capacitor C 2 not to be recharged) in writing period P WR, so writing the voltage VGS4 that voltage VGS between the gate-to-source that period P WR just begun rear drive transistor T DR is configured to mathematical expression (5), then, the source potential VS of driving transistors TDR does not change.That is, compensating movement stops fully in writing period P WR.
In above mode, be restricted to the action period P CP1 of PCP between the amortization period during the execution compensating movement.Therefore, if only set the time span t1 of action period P CP1 according to gradation potential VDATA, so that the error of drive current IDR reduces (desirable minimizes), then irrelevant (for example with the time span that writes period P WR, if the formation of first embodiment, then time span length is to the situation of the degree of the change that can ignore the current potential VS that writes among the period P WR), same with Figure 13, can reduce the error of drive current IDR accurately.
<D: the 4th embodiment 〉
Figure 18 is the block diagram of the light-emitting device that relates to of the 4th embodiment of the present invention.In the present embodiment, be that potential control circuit 36 generates current potential VCT (VCT[1]~VCT[m]) and to each supply lines 16 output with above-mentioned each embodiment difference.
Figure 19 is the circuit diagram of the image element circuit U that relates to of present embodiment.In Figure 19, only illustrate typically and belong to capable (1 the image element circuit U of the j of i=1~m) row of i.As shown in figure 19, in element portion 10, along first control line 20 and second control line 22 and the 12 corresponding one to one settings of m root sweep trace of directions X extension.From the every piece signal of supplying with regulation of driving circuit 30 (for example scan line drive circuit 32) to first control line 20 and second control line 22.More specifically, supply with initializing signal Grst[i to first control line 20], supply with control signal GC[i to second control line 22].And, as shown in figure 19, in element portion 10, be provided with the initialization line 24 that extends along the Y direction accordingly with signal wire 14.Never illustrated power circuit is supplied with initialization current potential Vrst to initialization line 24.
As shown in figure 19, image element circuit U comprises: light-emitting element E, driving transistors TDR, the first on-off element Tr1, second switch elements T r2, the 3rd on-off element Tr3, capacity cell C0 (capacitance cp0) and maintenance capacitor C 1 (capacitance cp1).Light-emitting element E and driving transistors TDR are connected in series on supply lines 18 and the path that supply lines 16 is connected.Supply with the current potential VEL of regulation to supply lines 18 from power circuit (omitting diagram).Light-emitting element E is the organic EL that folder has been established the luminescent layer of organic EL Material between opposed anode and negative electrode.As shown in figure 19, the anode of light-emitting element E is connected with driving transistors TDR, and negative electrode is connected with supply lines 16.As shown in figure 19, subsidiary on the light-emitting element E have a capacitor C 2 (capacitance cp2).
As shown in figure 19, driving transistors TDR is the P channel transistor (for example thin film transistor (TFT)) that source electrode is connected with supply lines 18 and drain electrode is connected with the anode of light-emitting element E.Capacity cell C0 has the first electrode L1 and the second electrode L2, and the second electrode L2 is connected with the grid of driving transistors TDR.Between the first electrode L1 and signal wire 14, be folded with the first on-off element Tr1 as the P channel transistor.The grid of the first on-off element Tr1 is connected with sweep trace 12.If sweep signal GA[i] move into low level, then the first on-off element Tr1 becomes conducting state, the first electrode L1 and signal wire 14 conductings, on the other hand, if sweep signal GA[i] move into high level, then the first on-off element Tr1 becomes cut-off state, the first electrode L1 and signal wire 14 not conductings.
As shown in figure 19, between the grid and initialization line 24 of driving transistors TDR, be folded with second switch elements T r2 as the P channel transistor.The grid of second switch elements T r2 is connected with first control line 20.If initializing signal Grst[i] move into low level, then second switch elements T r2 becomes conducting state, the grid of driving transistors TDR and 24 conductings of initialization line, on the other hand, if initializing signal Grst[i] move into high level, then second switch elements T r2 becomes cut-off state, the grid of driving transistors TDR and the 24 not conductings of initialization line.
As shown in figure 19, between the grid and drain electrode of driving transistors TDR, be folded with the 3rd on-off element Tr3 as the P channel transistor.The grid of the 3rd on-off element Tr3 is connected with second control line 22.If control signal GC[i] move into low level, then the 3rd on-off element Tr3 becomes conducting state, the grid of driving transistors TDR and drain electrode conducting, on the other hand, if control signal GC[i] move into high level, then the 3rd on-off element Tr3 becomes cut-off state, the grid of driving transistors TDR and the not conducting that drains.
As shown in figure 19, between the grid and source electrode of driving transistors TDR, be folded with maintenance capacitor C 1.Keeping capacitor C 1 is to be used for mechanism that the voltage between the gate-to-source of driving transistors TDR is kept, keeps an electrode of capacitor C 1 to be connected with the grid of driving transistors TDR, and another electrode is connected with supply lines 18.
Then,, be conceived to belong to the image element circuit U of the capable j row of i, the action (driving the method for image element circuit U) of driving circuit 30 is described with reference to Figure 20.As shown in figure 20, scan line drive circuit 32 in vertical scanning period i is selected among the period P SL sweep signal GA[i] set low level for.If sweep signal GA[i] be configured to low level, the first on-off element Tr1 that then belongs to the capable n of an i image element circuit U moves simultaneously and is conducting state.
As shown in figure 20, select period P SL to comprise: initialization period P RS, PCP and write period P WR between the amortization period.In initialization period P RS, make driving transistors TDR conducting by grid potential VG initialization with driving transistors TDR.Between through the amortization period after the initialization period P RS among the PCP,, make voltage VGS between the gate-to-source of driving transistors TDR be gradually to the threshold voltage VTH of driving transistors TDR thus by making the connection of driving transistors TDR diode.Through writing among the period P WR after the PCP between the amortization period, make the voltage VGS of driving transistors TDR, the change in voltage of from PCP between the amortization period, setting one-tenth and the corresponding voltage of gray-scale value D at image element circuit U appointment.In through the driving period P DR after selecting period P SL, the drive current IDR corresponding with the voltage VGS of driving transistors TDR offered light-emitting element E.Light-emitting element E is luminous with the brightness corresponding with drive current IDR.Below, be divided into initialization period P RS, PCP between the amortization period, write period P WR and drive period P DR, the concrete action of image element circuit U is described.
[1] initialization period P RS (Figure 21)
As shown in figure 20, driving circuit 30 (for example scan line drive circuit 32) is with initializing signal Grst[i] set low level for.Therefore, as shown in figure 21, second switch elements T r2 migration is conducting state, and the grid of driving transistors TDR is by second switch elements T r2 and 24 conductings of initialization line.Thus, the grid potential VG of driving transistors TDR is configured to initialization current potential Vrst.And, the source potential VS of driving transistors TDR be maintained in certain current potential VEL (>Vrst).Therefore, the voltage VGS between the gate-to-source of driving transistors TDR, be initialized to the difference of constant potential VEL and initialization current potential Vrst voltage VGS1 (=VEL-Vrst).
Initialization current potential Vrst is configured to voltage VGS1 between the gate-to-source of driving transistors TDR fully greater than the threshold voltage VTH of driving transistors TDR shown in following mathematical expression (1).Therefore, in initialization period P RS, driving transistors TDR becomes conducting state.
VGS1=VEL-Vrst》VTH?……(1)
As shown in figure 21, potential control circuit 36 will be to the current potential VCT[i of supply lines 16 output] set the first current potential VCT1 for.The first current potential VCT1 shown in following mathematical expression (2), be configured to the difference of the current potential VEL of supply lines 18 and this VCT1 voltage (=VEL-VCT1) fully be lower than the threshold voltage VTH_OLED of light-emitting element E.Therefore, in initialization period P RS, light-emitting element E becomes cut-off state (non-luminance).
VEL-VCT1《VTH_OLED……(2)
And as shown in figure 20, driving circuit 30 is with control signal GC[i] set low level for.Therefore, as shown in figure 21, the 3rd on-off element Tr3 migration is conducting state, and the drain and gate of driving transistors TDR connects (diode connection) by the 3rd on-off element Tr3.Such as described above, because the grid of driving transistors TDR is by second switch elements T r2 and 24 conductings of initialization line, so the drain electrode of driving transistors TDR is by the 3rd on-off element Tr3 and second switch elements T r2 and 24 conductings of initialization line.Thus, the drain potential of driving transistors TDR is set (resetting) one-tenth initialization current potential Vrst.
As described above, because driving transistors TDR is a conducting state, light-emitting element E is a cut-off state, so electric current I ds that between the source electrode of driving transistors TDR and drain electrode, flows through, by the 3rd on-off element Tr3 and second switch elements T r2, flow to initialization line 24 from the drain electrode of driving transistors TDR.Electric current I ds explains with following mathematical expression (3).The μ of mathematical expression (3) is the mobility of driving transistors TDR.And W/L be the channel width W of driving transistors TDR with respect to the comparing of channel length L, Cox is the electric capacity of unit area of the gate insulating film of driving transistors TDR.
Ids=1/2·μ·W/L·Cox·(VGS-VTH)
2……(3)
And as Figure 20 and shown in Figure 21, signal-line driving circuit 34 is with signal S[j] set the first reference potential VREF1 for.In initialization period P RS, the first on-off element Tr1 becomes conducting state, and the first electrode L1 among the capacity cell C0 is by the first on-off element Tr1 and signal wire 14 conductings.Therefore, the current potential of the first electrode L1 is configured to the first reference potential VREF1.On the other hand, because the current potential (the grid potential VG of driving transistors TDR) of the second electrode L2 among the capacity cell C0 is configured to initialization current potential Vrst, so the voltage between the two ends of capacity cell C0 is retained VREF1-Vrst.
[2] PCP (Figure 22, Figure 23) between the amortization period
As shown in figure 20, PCP is divided into action period P CP1 and keeps period P CP2 between the amortization period.Action period P CP1 be till starting point (terminal point of initialization period P RS) the elapsed time length t1 from PCP between the amortization period during, keeping period P CP2 is the remaining period (till from the terminal point of action period P CP1 to the terminal point of PCP the amortization period during) of PCP between the amortization period.The time span t1 of action period P CP1 is set changeably according to the gray-scale value D to image element circuit U appointment.More specifically, as shown in figure 20, the time span t1 when gray-scale value D specifies high gray scale (high brightness), the time span t1 when hanging down gray scale (low-light level) than gray-scale value D appointment is short.Wherein, the setting of the time span t1 of action period P CP1 will be narrated in the back.
As shown in figure 20, if action period P CP1 begins, then driving circuit 30 is with initializing signal Grst[i] set high level for.Therefore, as shown in figure 22, second switch elements T r2 migration is cut-off state.On the other hand, by with control signal GC[i] being maintained in low level, driving transistors TDR continues to be connected by diode.And potential control circuit 36 is with current potential VCT[i] be maintained the first current potential VCT1, signal-line driving circuit 34 is with signal S[j] be maintained the first reference potential VREF1.
Therefore, the electric current I ds of mathematical expression (3) flows to the grid of driving transistors TDR by the 3rd on-off element Tr3.Thus, capacity cell C0, maintenance capacitor C 1 are recharged, and as shown in figure 20, the grid potential VG of driving transistors TDR slowly rises.Because the source potential VS of driving transistors TDR is fixed to the current potential VEL of supply lines 18, so the voltage VGS between the gate-to-source of driving transistors TDR reduces along with the rising of grid potential VG.As from mathematical expression (3) as can be known, voltage VGS reduces more and near threshold voltage VTH, electric current I ds reduces more.Therefore, between the amortization period among the action period P CP1 of PCP, the voltage VGS of driving transistors TDR from the voltage VGS1 (VGS1=VEL-Vrst) that among initialization period P RS, sets through the time reduce, be gradually to threshold voltage VTH.
As mentioned above, make voltage VGS be gradually to the action (hereinafter referred to as " first compensating movement ") of threshold voltage VTH, before voltage VGS reaches threshold voltage VTH, stop in the starting point (having passed through the time point of time span t1 from the starting point of PCP between the amortization period) that keeps period P CP2.Voltage VGS between the gate-to-source of driving transistors TDR is configured to keep the voltage VGS2 of the time point that the starting point of period P CP2 arrived.Stopping of first compensating movement below is described in detail in detail.
As Figure 20 and shown in Figure 23, if keep period P CP2 to begin, then signal-line driving circuit 34 makes signal S[j] be varied to the second reference potential VREF2.In the present embodiment, the second reference potential VREF2 is higher than the first reference potential VREF1 (with reference to Figure 20).Because the first on-off element Tr1 continues to keep conducting state after action period P CP1, so the current potential of the first electrode L1 among the capacity cell C0 is varied to the second reference potential VREF2 from the first reference potential VREF1.And the grid potential VG of driving transistors TDR changes (rising) corresponding to the variation delta V1 (Δ V1=VREF2-VREF1) of the current potential of the first electrode L 1.The variable quantity that keeps the VG after period P CP2 has just begun is equivalent to the variation delta V1 of the current potential of the first electrode L1 be cut apart and the voltage (Δ V1cp0/ (cp0+cp1+cp2)) that obtains according to capacity cell C0, the capacity ratio that keeps capacitor C 1 and capacitor C 2.Therefore, voltage VGS3 between the gate-to-source of the driving transistors TDR after maintenance period P CP2 has just begun, voltage VGS2 between the gate-to-source of the driving transistors TDR of the destination county of utilization action period P CP1 explains as following mathematical expression (4).
VGS3=VGS2-ΔV1·cp0/(cp0+cp1+cp2)……(4)
The voltage VGS3 that the second reference potential VREF2 is configured to mathematical expression (4) is lower than the threshold voltage VTH of driving transistors TDR.Therefore, in keeping period P CP2, the current potential of the first electrode L1 by making capacity cell C0 changes to the second reference potential VREF2 from the first reference potential VREF1, makes that driving transistors TDR migration is a cut-off state.Promptly, make voltage VGS between the gate-to-source of driving transistors TDR be gradually to first compensating movement of threshold voltage VTH, when keeping period P CP2 begins, stop, the voltage VGS of driving transistors TDR is retained the voltage VGS3 of mathematical expression (4) till the terminal point that keeps period P CP2 arrives.
[3] write period P WR (Figure 24)
As shown in figure 20, begin if write period P WR, then driving circuit 30 is with control signal GC[i] set high level for.Therefore, as shown in figure 24, the 3rd on-off element Tr3 moves into cut-off state, and the diode connection of driving transistors TDR is disengaged.That is, the grid of driving transistors TDR becomes electric quick condition.
As shown in figure 24, signal-line driving circuit 34 makes signal S[j] be varied to gradation potential VDATA.Gradation potential VDATA is set changeably according to the gray-scale value D to image element circuit U (light-emitting element E) appointment.Because the first on-off element Tr1 also keeps conducting state in writing period P WR, so the current potential of the first electrode L1 among the capacity cell C0 is varied to gradation potential VDATA from the second reference potential VREF2 that is set during keeping period P CP2.And the grid potential VG of driving transistors TDR changes corresponding to the variation delta V2 (Δ V2=VDATA-VREF2) of the current potential of the first electrode L 1.Write the variable quantity of the VG after period P WR has just begun, be equivalent to according to capacity cell C0 and keep the capacity ratio of capacitor C 1 that the variation delta V2 of the current potential of the first electrode L1 is cut apart and the voltage (Δ V2cp0/ (cp0+cp1)) that obtains.
Therefore, the voltage VGS4 between the gate-to-source of the driving transistors TDR after writing period P WR and just having begun is stated as following mathematical expression (5).As mentioned above, set corresponding to gradation potential VDATA, make driving transistors TDR be varied to conducting state by voltage VGS4.
VGS4=VGS3-ΔV2·cp0/(cp0+cp1)
=(VGS2-ΔV1·cp0/(cp0+cp1+cp3)}-ΔV2·cp0/(cp0+cp1)
=VGS2-(VREF2-VREF1)·c?p0/(cp0+cp1+cp3)-(VDATA-VREF2)·cp0/(cp0+cp1)……(5)
[4] drive period P DR (Figure 25)
As shown in figure 20, begin if drive period P DR, then driving circuit 30 makes sweep signal GA[i] be varied to high level (inactive level).Therefore, as shown in figure 25, the first on-off element Tr1 of each image element circuit U that i is capable is varied to cut-off state, supplies with at the current potential of the first electrode L1 of capacity cell C0 to stop.
And as Figure 20 and shown in Figure 25, potential control circuit 36 will be to the current potential VCT[i of supply lines 16 output] set the second current potential VCT2 for.The second current potential VCT2 shown in following mathematical expression (6), be configured to and the voltage of the difference of the current potential VEL of the bit line 18 of powering (=VEL-VCT2) fully be higher than the threshold voltage VTH_OLED of light-emitting element E.
VEL-VCT2》VTH_OLED……(6)
So the electric current I ds of mathematical expression (3) flows to light-emitting element E, capacitor C 2 is recharged.Therefore, be maintained at the voltage VGS between the gate-to-source of driving transistors TDR under the state of voltage VGS4 of mathematical expression (5), the voltage between the two ends of capacitor C 2 (current potential of the drain electrode of driving transistors TDR) slowly increases.Then, the voltage between the two ends of capacitor C 2 has reached the time point of the threshold voltage VTH_OLED of light-emitting element E, and electric current I ds is provided for light-emitting element E as drive current IDR.Drive current IDR explains with following mathematical expression (7).
IDR=1/2·μ·W/L·Cox·(VGS4-VTH)
2……(7)
As mentioned above, owing to drive current IDR is controlled so as to and the corresponding magnitude of current of voltage VGS4 that has reflected gradation potential VDATA, so light-emitting element E is luminous with the brightness corresponding with gradation potential VDATA (being gray-scale value D).The luminous sweep signal GA[i that continues to of light-emitting element E] till the selection period P SL that next becomes significant level begins.It more than is the action of image element circuit U.
Then, Figure 26 is the relevant curve map that time span t1 that expression is continued compensating movement is fixed into gradation potential VDATA and the error of the magnitude of current of drive current IDR in the formation (hereinafter referred to as " Comparative Examples ") of setting.The transverse axis of Figure 26 represents with the first reference potential VREF1 to be the magnitude of voltage of the gradation potential VDATA of reference value, the maximal value of the magnitude of current of the drive current IDR the when longitudinal axis of Figure 26 has represented same grayscale value D designated and the contrast of minimum value (maximum error than).The voltage VGS that time span t1 in the Comparative Examples is configured to driving transistors TDR reaches the required time enough length of threshold voltage VTH.
As shown in Figure 26, at the time span t1 that makes compensating movement is under the situation of fixed value, and when gradation potential VDATA was configured to setting VD0, the error of drive current IDR was lowered really, but gradation potential VDATA is more away from setting VD0, and the error of drive current IDR increases more.That is, in Comparative Examples, exist the broad range be difficult to spread all over gradation potential VDATA to eliminate this problem of error of drive current IDR.
Figure 27 is that (VD1<VD2<VD3<VD4<VD5) illustrates the curve map of relation of the error (maximum error than) of the time span t1 of action period P CP1 and the drive current IDR of the manner at a plurality of situations that gradation potential VDATA is changed.The error of drive current IDR is the time span t1 of the minimum trend different according to gradation potential VDATA, can be as can be seen from Figure 27.That is, gradation potential VDATA is low more, and the error of drive current IDR is that the time span t1 of minimum is short more.
From above viewpoint, in the manner, by setting the time span t1 of action period P CP1 changeably according to gray-scale value D (gradation potential VDATA), with the gradation potential VDATA error of controlling and driving electric current I DR irrespectively.Figure 28 is expression gradation potential VDATA and the curve map of the relation of the time span t1 of action period P CP1.As shown in figure 28, low more (promptly according to gradation potential VDATA, the variable quantity of the grid potential VG of driving transistors TDR after writing period P WR and just having begun is big more), the short more mode of time span t1 of action period P CP1 is come setting-up time length t1 corresponding to gradation potential VDATA.For example, when in writing period P WR, gradation potential VDATA being set for the current potential VD1 of Figure 27, action period P CP1 is set to time span T1, when gradation potential VDATA was configured to be higher than the current potential VD2 of current potential VD1, action period P CP1 was set to the time span T2 longer than time span T1.
Wherein, because gradation potential VDATA is high more, be used for the time span t1 of the error minimize of drive current IDR long more, so, if under the sufficiently high situation of gradation potential VDATA (for example designated the situation of minimum gray scale), also want the error of drive current IDR is minimized fully, then need to set time span t1 for long time.Therefore, as shown in figure 28, the signal-line driving circuit 34 of the manner (the time adjustment part 46 of unit circuit 40), be lower than under the situation (gradation potential VDATA is higher than the situation of the current potential VD_th of Figure 28) of the gray-scale value D of setting designated, the time span t1 of action period P CP1 is set the setting t max that (clip) becomes not rely on gray-scale value D.The voltage VGS that maximal value t max is constrained to than driving transistors TDR is reduced to the short time of the required time span of threshold voltage VTH by compensating movement.According to above formation, can shorten PCP between the amortization period (and then shorten and select period P SL).
As described with reference to Figure 20, first compensating movement among the action period P CP1 is by signal S[j] be varied to the second reference potential VREF2 from the first reference potential VREF1 and finish.Therefore, the constituent parts circuit 40 of signal-line driving circuit 34, by according to gray-scale value D to signal S[j] adjust from the period that the first reference potential VREF1 is varied to the second reference potential VREF2, come the time span t1 of control action period P CP1 changeably.
Figure 29 is the block diagram of the unit circuit 40 of signal-line driving circuit 34.In Figure 29, only illustrate typically generate and output signal S[j] 1 unit circuit 40.As shown in figure 29, unit circuit 40 comprises current potential generating unit 42, current potential selection portion 44 and time adjustment part 46.The gray-scale value D of j image element circuit U is provided for current potential generating unit 42 and time adjustment part 46.
Current potential generating unit 42 generates the gradation potential VDATA corresponding with gray-scale value D.For example, the D/A converter of voltage output type is utilized as current potential generating unit 42.The gradation potential VDATA that supplies with the first reference potential VREF1 that generates by power circuit (omitting diagram) and the second reference potential VREF2 and generate to current potential selection portion 44 by current potential generating unit 42.Current potential selection portion 44 optionally with any one of the first reference potential VREF1, the second reference potential VREF2 and gradation potential VDATA as signal S[j] to signal wire 14 outputs.If be described in further detail, then current potential selection portion 44 is at initialization period P RS and the output first reference potential VREF1 among the action period P CP1 of PCP between the amortization period, the output second reference potential VREF2 among the maintenance period P CP2 of PCP between the amortization period, output gray level current potential VDATA in writing period P WR.
Time adjustment part 46 makes signal S[j to current potential selection portion 44 changeably according to gray-scale value D] current potential control from the period (being the action period P CP1 and the border that keeps period P CP2 of PCP between the amortization period) that the first reference potential VREF1 is altered to the second reference potential VREF2.For example, the starting point of PCP begins to count and count value has reached time point (from beginning to count the time point that has passed through time span t1) with gray-scale value D value corresponding between the amortization period, (counter of indication of VREF1 → VREF2) is used as time adjustment part 46 to the switching of current potential selection portion 44 output potentials.Time adjustment part 46 is set at the higher limit this point of time span t1 with maximal value t max, as previously mentioned.
The time span t1 of action period P CP1 is on the basis of above formation, according to gray-scale value D (gradation potential VDATA) Be Controlled.Because it is short that time span t1 is configured to be reduced to the required time of threshold voltage VTH than the voltage VGS of driving transistors TDR from the voltage VGS1 of the destination county of initialization period P RS, so the voltage VGS2 between the gate-to-source of the driving transistors TDR of the destination county of action period P CP1 does not reach threshold voltage VTH and changes corresponding to time span t1.Therefore, according to the action of the time span t1 of gray-scale value D control action period P CP1, also as according to gray-scale value D changeably the voltage VGS2 of the destination county of control action period P CP1 action and held.Wherein, the whole time span of PCP is fixed between the amortization period.Therefore, CP1 is long more for the action period P, keeps period P CP2 short more.
Need to prove that the main cause of the error of drive current IDR is the threshold voltage VTH of driving transistors TDR and the error of mobility [mu].At present, in order only to compensate the error of threshold voltage VTH, as patent documentation 1 is disclosed, need make the voltage VGS of driving transistors TDR consistent among the PCP between the amortization period with threshold voltage VTH.In the manner, though the voltage VGS of driving transistors TDR does not reach threshold voltage VTH in the PCP between the amortization period, as Figure 27 illustrated, the error of drive current IDR was reliably suppressed by the adjustment of time span t1.And voltage VGS between the amortization period, do not reach among the PCP threshold voltage VTH irrespectively the error of drive current IDR be suppressed, this be because, except the error of threshold voltage VTH, the error of mobility [mu] is also compensated by the adjustment of time span t1.That is, in the manner, the mode that is compensated according to threshold voltage VTH and the mobility [mu] both sides of driving transistors TDR, control time length t1 changeably.
Figure 30 is the gradation potential VDATA of expression in the manner and the curve map of the relation (solid line) of the error of drive current IDR.In Figure 30, with dashed lines has been represented relevant (Figure 26) with the error of drive current IDR of the gradation potential VDATA in the Comparative Examples in the lump.As shown in figure 30, according to the manner, the formation of the patent documentation 1 that is fixed with the time span of compensating movement is compared, and exists the error of the broad range drive current IDR that spreads all over gradation potential VDATA to be suppressed this advantage.
Wherein, for the zone of the high-order side of the gradation potential VDATA in Figure 30, the error of drive current IDR increases slightly, thinks the upper limit restriction of time span t1 is the influence of maximal value t max.As noted above, if drive current IDR produces error in low gray scale side, then for example specify under the minimum gray scale situation of (the black demonstration) at gray-scale value D, the magnitude of current of drive current IDR should be set for zero haveing nothing to do with former, all the phenomenon that drive current IDR is provided for light-emitting element E (then, light-emitting element E is luminous) might take place.Consider above situation, in the manner, the gradation potential VDATA during designated minimum gray scale is configured to be higher than the current potential Vmax (with reference to Figure 28) of the first reference potential VREF1.Because being configured to the voltage VGS of driving transistors TDR, current potential Vmax is lower than threshold voltage VTH, so to restrict into the formation of maximal value tmax irrelevant with moving the time span t1 of period P CP1, have can infalliblely will be designated the magnitude of current of drive current IDR during minimum gray scale be set at zero this advantage.
<E: the 5th embodiment 〉
Then, the 5th embodiment of the present invention is described.Present embodiment the 4th embodiment difference is that driving transistors TDR writing among the period P WR after PCP continue between the amortization period also connected by diode.Other aspects are identical with the 4th embodiment.
Figure 31 is the sequential chart of the action of the light-emitting device that relates to of expression present embodiment.As shown in figure 31, in writing period P WR, driving circuit 30 continued after the PCP control signal GC[i between the amortization period] set low level for.Therefore, the 3rd on-off element Tr3 is maintained in conducting state, and driving transistors TDR continues to be connected by diode.
Such as described above, begin if write period P WR, then the current potential of the first electrode L1 is varied to gradation potential VDATA from the second reference potential VREF2.And, the grid potential VG of driving transistors TDR corresponding to the variation delta V2 of the current potential of the first electrode L1 (=VDATA-VREF2) change.In the present embodiment, because driving transistors TDR writing among the period P WR after PCP continue between the amortization period also connected by diode, the grid of driving transistors TDR and drain electrode conducting, so write the variable quantity of the VG after period P WR has just begun, be equivalent to according to capacity cell C0, keep the capacity ratio of capacitor C 2 subsidiary on capacitor C 1 and the light-emitting element E, the variation delta V2 of the current potential of the first electrode L1 is cut apart and the voltage (Δ V2cp0/ (cp0+cp1+cp2)) that obtains.
Therefore, the voltage VGS4 between the gate-to-source of the driving transistors TDR after writing period P WR and just having begun replaces mathematical expression (5) to explain with following mathematical expression (8).As mentioned above, voltage VGS4 sets corresponding to gradation potential VDATA (further detailed difference for the gradation potential VDATA and the first reference potential VREF1), and driving transistors TDR is varied to conducting state.
VGS4=VGS3-ΔV2·cp0/(cp0+cp1+cp2)
={VGS2-ΔV1·cp0/(cp0+cp1+cp2)}-ΔV2·cp0/(cp0+cp1+cp2)
=VGS2+(VREF1-VDATA)·cp0/(cp0+cp1+cp2)……(8)
As previously mentioned, because in writing period P WR, driving transistors TDR is connected by diode, so the electric current I ds of mathematical expression (3) flow into the grid of driving transistors TDR by the 3rd on-off element Tr3.Thus, as shown in figure 31, the grid potential VG of driving transistors TDR slowly rises.Because the source potential VS of driving transistors TDR is fixed to current potential VEL, so the voltage VGS between the gate-to-source of driving transistors TDR reduces when grid potential VG rises.That is, as shown in figure 31, make voltage VGS between the gate-to-source of driving transistors TDR be gradually to second compensating movement of threshold voltage VTH, in writing period P WR, also be performed.
As shown in figure 31, begin if drive period P DR, then driving circuit 30 is with control signal GC[i] set high level for.Therefore, the 3rd on-off element Tr3 moves into cut-off state, and the diode connection of driving transistors TDR is disengaged.In driving period P DR, be maintained at the voltage VGS between the gate-to-source of driving transistors TDR under the state of voltage VGS4 ' at the starting point place that drives period P DR, the electric current I ds of mathematical expression (3) flows to light-emitting element E.And if the voltage between the two ends of the capacitor C 2 of attaching on the light-emitting element E has reached the threshold voltage VTH_OLED of light-emitting element E, then above-mentioned electric current I ds is provided for light-emitting element E as drive current IDR.
In the present embodiment, consider action period P CP1 and write compensating movement among the period P WR both sides, time span t1 and the summation T that writes the time span t2 of period P WR according to action period P CP1 decide and gradation potential VDATA time corresponding length t1.If be described in further detail, then for each of a plurality of gradation potential VDATA, by experiment or calculate (simulation) and determined that the error of drive current IDR is minimum summation T, the difference of summation T and time span t2 (fixed value) is determined as moving the time span t1 of period P CP1.
At present, the time span of having supposed should to compensate for the error of eliminating drive current IDR action is T, and the time span that writes period P WR is the situation of fixed value t2.With respect to the formation that in writing period P WR, does not compensate action, the time span of action period P CP1 need be made as T, in the present embodiment, owing to not only in action period P CP1, carry out compensating movement, and also carry out compensating movement in writing period P WR, so the time span of action period P CP1 is that T-t2 gets final product.Therefore, according to present embodiment, even if in action period P CP1, can't guarantee to make under the situation of the required sufficient time length of the error minimize of drive current IDR, also have this advantage of error that to utilize the compensating movement (second compensating movement) that writes among the period P WR to suppress drive current IDR.
<F: the 6th embodiment 〉
Figure 32 is the circuit diagram of the image element circuit U that relates to of the 6th embodiment of the present invention.In Figure 32, only illustrate 1 the image element circuit U that belongs to the capable j row of i typically.Shown in figure 32, in element portion 10, along the 3rd control line 26 and the 12 corresponding one to one settings of m root sweep trace of directions X extension.Supply with led control signal GEL[i from driving circuit 30 (for example scan line drive circuit 32) to the 3rd control line 26].
Shown in figure 32, image element circuit U also possesses the 4th on-off element Tr4 on the path that is folded in drive current IDR.Shown in figure 32, as the 4th on-off element Tr4 of P channel transistor, be folded between the drain electrode and light-emitting element E of driving transistors TDR, the grid of the 4th on-off element Tr4 is connected with the 3rd control line 26.If led control signal GEL[i] migration is for low level, then the 4th on-off element Tr4 becomes conducting state, the anode conducting of the drain electrode of driving transistors TDR and light-emitting element E, on the other hand, if led control signal GEL[i] migration is for high level, then the 4th on-off element Tr4 becomes cut-off state, the not conducting of anode of the drain electrode of driving transistors TDR and light-emitting element E.
Figure 33 is the sequential chart of the action of the light-emitting device that relates to of expression present embodiment.In the present embodiment, led control signal GEL[i] and current potential VCT[i] control beyond control action, identical with first embodiment.As shown in figure 33, in initialization period P RS, driving circuit 30 is with led control signal GEL[i] set low level for.Therefore, the 4th on-off element Tr4 migration shown in Figure 32 is conducting state, and the drain electrode of driving transistors TDR is by the anode conducting of the 4th on-off element Tr4 and light-emitting element E.As previously mentioned, because in initialization period P RS, the drain electrode of driving transistors TDR is by the 3rd on-off element Tr3 and second switch elements T r2 and 24 conductings of initialization line, so the anode of light-emitting element E is by the 4th on-off element Tr4, the 3rd on-off element Tr3 and second switch elements T r2 and 24 conductings of initialization line.Therefore, as shown in figure 33, the current potential VA of the anode of light-emitting element E together is set (resetting) with the drain electrode of driving transistors TDR and becomes initialization current potential Vrst.
As shown in figure 33, potential control circuit 36 spread all over whole during (initialization period P RS, PCP between the amortization period, write period P WR, drive period P DR) will be to the current potential VCT[i of supply lines 16 outputs] set the second current potential VCT2 for.And, like that, the voltage (being the voltage between the two ends of the light-emitting element E among the initialization period P RS) that is configured to both differences fully is lower than the threshold voltage VTH_OLED of light-emitting element E shown in following mathematical expression (9) for the second current potential VCT2 and initialization current potential Vrst.Therefore, in initialization period P RS, light-emitting element E becomes cut-off state (non-luminance).
Vrst-VCT2《VTH_0LED……(9)
As shown in figure 33, among the PCP, driving circuit 30 is with led control signal GEL[i between the amortization period] set high level for.Therefore, because the 4th on-off element Tr4 moves into cut-off state, so the not conducting of anode of the drain electrode of driving transistors TDR and light-emitting element E, light-emitting element E is maintained in cut-off state (non-luminance).
As previously mentioned, if by way of compensation in the period P CP during maintenance period P CP2 begin, then the current potential of the first electrode L1 is varied to the second reference potential VREF2 from the first reference potential VREF1.In the present embodiment, because between the amortization period among the PCP, the 4th on-off element Tr4 moves into cut-off state, so the not conducting of anode of the drain electrode of driving transistors TDR and light-emitting element E, the variable quantity of the VG after maintenance period P CP2 has just begun does not rely on the capacitance (cp2) of capacitor C 2 subsidiary on the light-emitting element E.Therefore, the variable quantity that keeps the VG after period P CP2 has just begun, be equivalent to according to capacity cell C0 and the capacity ratio that keeps capacitor C 1 to the variation delta V1 of the current potential of the first electrode L1 (=VREF2-VREF1) cut apart and the voltage (Δ V1cp0/ (cp0+cp1)) that obtains.Voltage VGS3 between the gate-to-source of the driving transistors TDR after maintenance period P CP2 has just begun is with following mathematical expression (10) statement and replace using mathematical expression (4) statement.
VGS3=VGS2-ΔV1·cp0/(cp0+cp1)……(10)
According to mathematical expression (10) and mathematical expression (4) as can be known, for being used for setting voltage VGS3 the desirable value of the threshold voltage VTH that is lower than driving transistors TDR for and for the variation delta V1 of the current potential of the first electrode L1 of needs, present embodiment is littler than first embodiment.Therefore, according to present embodiment, have can make the signal S[j among the PCP between the amortization period] the amplitude of variation advantage littler than first embodiment.And, according to mathematical expression (10) as can be known, in the present embodiment, because with the capacitance (cp2) of capacitor C 2 subsidiary on light-emitting element E setting voltage VGS3 irrespectively, so, even if the capacitance generation deviation of the capacitor C 2 among each image element circuit U is not influenced by it can yet, the value of each voltage VGS3 can deviation.Therefore, according to present embodiment, have the deviation that can suppress and make the current value of drive current IDR the advantage of error occur because of the capacitance of capacitor C 2 (cp2).
As shown in figure 33, in writing period P WR, driving circuit 30 is with led control signal GEL[i] be maintained in high level.Therefore, the 4th on-off element Tr4 is maintained in cut-off state, and light-emitting element E is maintained in cut-off state (non-luminance).
As described above, if writing period P WR begins, then the current potential of the first electrode L1 is varied to gradation potential VDATA from the second reference potential VREF2, write the variable quantity of the VG after period P WR has just begun, be equivalent to according to capacity cell C0 and the capacity ratio that keeps capacitor C 1 to the variation delta V2 of the current potential of the first electrode L1 (=VDATA-VREF2) cut apart and the voltage (Δ V2cp0/ (cp0+cp1)) that obtains.In the present embodiment, the formula that voltage VGS4 between the gate-to-source of the driving transistors TDR after writing period P WR and just having begun is represented becomes the form of the capacitance (cp2) that does not rely on capacitor C 2 subsidiary on the light-emitting element E with following mathematical expression (11) statement.
VGS4=VGS3-ΔV2·cp0/(cp0+cp1)
={VGS2-ΔV1·cp0/(cp0+cp1)}-ΔV2·cp0/(cp0+cp1)
=VGS2+(VREF1-VDATA)·cp0/(cp0+cp1)……(11)
According to mathematical expression (11) and mathematical expression (8) as can be known, has following advantage, promptly, set voltage VGS4 for the desirable value corresponding with gray-scale value D and first reference potential VREF1 of needs and the amplitude of variation of gradation potential VDATA to being used for, present embodiment can be littler than second embodiment.
As shown in figure 33, in driving period P DR, driving circuit 30 is with led control signal GEL[i] set low level for.Therefore, the 4th on-off element Tr4 migration is conducting state, and the drain electrode of driving transistors TDR and the anode of light-emitting element E are by the 4th on-off element Tr4 conducting.And, flow to the anode of light-emitting element E by the 4th on-off element Tr4 by the electric current I ds of mathematical expression (3), as shown in figure 16, current potential VA rises, when the voltage between the two ends of light-emitting element E (=when VA-VCT2) arriving the threshold voltage VTH_OLED of light-emitting element E, above-mentioned electric current I ds is provided for light-emitting element E as drive current IDR.
Yet, if between the amortization period PCP, write among the period P WR, light-emitting element E is luminous, has in the pixel problem that contrast reduces that takes place.In each above-mentioned embodiment (first~the 3rd embodiment), because PCP and writing among the period P WR between the amortization period, light-emitting element E is maintained in cut-off state (non-luminance) reliably, so have the advantage that can suppress the reduction of contrast in the pixel.And, according to present embodiment, as shown in figure 33, even if do not make the current potential VCT[i of supply lines 16] change, because light-emitting element E luminous PCP and writing among the period P WR between the amortization period also can stop, so, compare with first embodiment and second embodiment, have the advantage of the control that can simplify potential control circuit 36.
In addition, according to the 4th above-mentioned embodiment and the 5th embodiment, because by making the current potential VCT[i of supply lines 16] (current potential that provides to another electrode of light-emitting element E) change, can switch the conducting state and the cut-off state of light-emitting element E, so can on the path of drive current IDR, not be provided for determining to supply with to light-emitting element E the on-off element (for example the 4th on-off element Tr4) of drive current IDR.Therefore, the advantage that has the formation that to simplify image element circuit U.
<G: variation 〉
Each above mode can realize various distortion.Below with the concrete mode of illustration at the distortion of each mode.In addition, can from following illustration, select the mode more than 2 to make up arbitrarily.
(1) variation 1
In each above-mentioned embodiment, the conductivity type that is arranged on each switch in the image element circuit U is arbitrarily.In first embodiment~the 3rd embodiment, for example as shown in figure 34, also can adopt and make driving transistors TDR, selector switch TSL is the formation of P channel-type.In the image element circuit U of Figure 34, the anode of light-emitting element E is connected with supply lines 18 (current potential VCT), and the drain electrode of driving transistors TDR and supply lines 16 (current potential VEL[i]) be connected, source electrode is connected with the negative electrode of light-emitting element E simultaneously.Being folded with the formation that keeps capacitor C 1 between the grid of driving transistors TDR and the source electrode, between the grid of driving transistors TDR and signal wire 14, being folded with the formation of selector switch TSL, same with Fig. 2.As mentioned above, adopted P channel-type driving transistors TDR situation, compare with the situation that has adopted N channel-type driving transistors TDR, the relation of voltage (just) is put upside down, but because the action of essence is the same with Fig. 3, so the detailed description of omit moving.Wherein, the same with the 3rd embodiment, (for example between the drain electrode of driving transistors TDR and the supply lines 18) disposes the formation of gauge tap TCR configuration on the path of the electric current I ds that also adopts at the driving transistors TDR that flows through Figure 34.
And, in the 4th embodiment~the 6th embodiment, for example also can constitute all or part of of the first on-off element Tr1~the 4th on-off element Tr4 by the N channel transistor.
(2) variation 2
Be used for gradation potential VDATA is offered the signal wire 14 of image element circuit U, be used for the formation that the action of the image element circuit U among PCP between the amortization period, the initialization period P RS is stipulated, also nonessential in the present invention.If it is be described in further detail, then as follows.
In each above-mentioned embodiment, by making the signal S[j of signal wire 14] be varied to VREF2 from VREF1, stopped compensating movement, but the method that is used to compensating movement is stopped can to change suitably.In first embodiment~the 3rd embodiment, for example, also can adopt at the starting point place that keeps period P CP2 to make selector switch TSL migration the formation that the wiring that is supplied to reference potential VREF2 is connected with the grid of driving transistors TDR on the basis of cut-off state.In the 4th embodiment~the 6th embodiment, for example, also can adopt at the starting point place that keeps period P CP2 to make the first on-off element Tr1 migration formation that the wiring that is supplied to the second reference potential VREF2 is connected with the first electrode L1 of capacity cell C0 on the basis of cut-off state.
And, in first embodiment~the 3rd embodiment, in the implementation of the compensating movement of action period P CP1, supplied with reference potential VREF1 (signal S[j]) from signal wire 14 to the grid of driving transistors TDR, but the method for in the implementation of compensating movement the grid potential of driving transistors TDR being kept can change suitably.For example, also can adopt following formation, promptly making selector switch TSL migration in action period P CP1 is on the basis of cut-off state, and the wiring that is supplied to reference potential VREF1 is connected with the grid of driving transistors TDR.For the action of the reference potential VREF1 of the grid of in initialization period P RS, supplying with driving transistors TDR too, for example, can adopt following formation, promptly in initialization period P RS, make selector switch TSL migration on the basis of cut-off state, the wiring that is supplied to reference potential VREF1 is connected with the grid of driving transistors TDR.
And, in the 4th embodiment~the 6th embodiment, in the implementation of first compensating movement of action period P CP1, supplied with the first reference potential VREF1 (signal S[j]) from signal wire 14 to the first electrode L 1, but the method for keeping the current potential of the first electrode L1 in the implementation of first compensating movement can change suitably.For example, also can adopt following formation, promptly making first on-off element Tr1 migration in action period P CP1 is on the basis of cut-off state, and the wiring that is supplied to the first reference potential VREF1 is connected with the first electrode L1.
But, as each above-mentioned embodiment, according to signal wire 14 (signal S[j]) being used for initialization period P RS, the formation of driving of image element circuit U between the amortization period among the PCP, be used for comparing with having formed independently, realized that element portion 10 constitutes the special result that is simplified in initialization period P RS, PCP drives the wiring of image element circuit U between the amortization period formation with signal wire 14.
(3) variation 3
In the 6th embodiment, making the 4th on-off element Tr4 in initialization period P RS is conducting state, but for example also can make the 4th on-off element Tr4 in initialization period P RS is cut-off state, and only making the 4th on-off element Tr4 in driving period P DR is conducting state.
(4) variation 4
In the 6th embodiment, as shown in figure 33, the diode of having removed driving transistors TDR in writing period P WR connects, but also can be same with second embodiment, by make driving transistors TDR in writing period P WR is that diode connects, and carries out second compensating movement.
(5) variation 5
As each above mode, be arranged on the basis of rectangular formation at a plurality of image element circuit U, when with the unit of going, during each image element circuit U of division driving, in each image element circuit U, need selector switch TSL, the first on-off element Tr1.But, for example only be arranged in along directions X in the formation of 1 row at a plurality of image element circuit U and since do not need by the time multirow cut apart the selection This move, so do not need selector switch TSL, the first on-off element Tr1 in the image element circuit U.A plurality of image element circuit U only are arranged in the light-emitting device 100 of 1 row, for example are suitable as the exposure device that in the image processing system (printing equipment) of electrofax mode image carriers such as photosensitive drums is exposed.
(6) variation 6
In each above mode, utilized the capacitor C 2 of attaching on the light-emitting element E, but as shown in figure 35, also preferably with the formation of capacitor C X with capacitor C 2 utilizations.The electrode e1 of capacitor C X links to each other with the path that driving transistors TDR is connected with light-emitting element E (drain electrode of driving transistors TDR or source electrode).The electrode e2 of capacitor C X connects with the wiring (in first embodiment~the 3rd embodiment, for example being supplied to the supply lines 18 of current potential VCT) that is supplied to the regulation current potential.In above formation, the capacitance cp2 in mathematical expression (4), the mathematical expression (5) becomes the aggregate values of the capacitor C 2 of capacitor C X and light-emitting element E.Therefore, can adjust the voltage VGS3 of mathematical expression (4), the voltage VGS4 of mathematical expression (5) corresponding to capacitor C X.
(7) variation 7
Organic EL only is the illustration of light-emitting component.For example, for the light-emitting device that is arranged with light-emitting components such as inorganic EL element, LED (Light Emitting Diode) element, also can similarly use the present invention with each above mode.Light-emitting component among the present invention is the key element that gray scale (brightness) changes by the supply of electric current.
<H: application examples 〉
Then, the electronic equipment that has utilized the light-emitting device 100 that above each mode relates to is described.In Figure 36~Figure 38, illustrate the embodiment of light-emitting device 100 as the electronic equipment of display device.
Figure 36 is the stereographic map of formation that the pocket pc of light-emitting device 100 has been adopted in expression.PC 2000 possesses: show the light-emitting device 100 of various images and be provided with the main part 2010 of power switch 2001, keyboard 2002.Since light-emitting device 100 with organic EL as light-emitting element E, so but display view angle greatly and the picture of watching easily.
Figure 37 is the stereographic map of formation that the mobile phone of light-emitting device 100 has been used in expression.Mobile phone 3000 possesses: a plurality of action buttons 3001 and scroll button 3002 and show the light-emitting device 100 of various images.By operation scroll button 3002, picture displayed is rolled on light-emitting device 100.
Figure 38 is the stereographic map of formation that the portable information terminal (PD A:PersonalDigital Assistants) of light-emitting device 100 has been used in expression.Information portable terminal device 4000 possesses: a plurality of action buttons 4001 and power switch 4002 and show the light-emitting device 100 of various images.If operating power switch 4002, then various information such as address book, schedule are shown in light-emitting device 100.
In addition, as the electronic equipment that can use the light-emitting device that the present invention relates to, except illustrative equipment in Figure 36~Figure 38, can also enumerate digital camera, televisor, video camera, automobile navigation apparatus, pager, electronic notebook, electronic paper, desk-top electronic calculator, word processor, workstation, videophone, POS terminal, printer, scanner, duplicating machine, player, have the equipment of touch panel etc.And the purposes of light-emitting device of the present invention is not limited to the demonstration of image.For example, in the image processing system of electrofax mode, the exposure device as form sub-image on photosensitive drums by exposure also can utilize light-emitting device of the present invention.