CN101609804B - 集成电路结构的形成方法 - Google Patents
集成电路结构的形成方法 Download PDFInfo
- Publication number
- CN101609804B CN101609804B CN200810170436XA CN200810170436A CN101609804B CN 101609804 B CN101609804 B CN 101609804B CN 200810170436X A CN200810170436X A CN 200810170436XA CN 200810170436 A CN200810170436 A CN 200810170436A CN 101609804 B CN101609804 B CN 101609804B
- Authority
- CN
- China
- Prior art keywords
- protective material
- integrated circuit
- circuit structure
- nude film
- formation method
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000000034 method Methods 0.000 title claims abstract description 38
- 239000000463 material Substances 0.000 claims abstract description 66
- 239000004065 semiconductor Substances 0.000 claims abstract description 50
- 230000001681 protective effect Effects 0.000 claims description 55
- 229910052710 silicon Inorganic materials 0.000 claims description 28
- 239000010703 silicon Substances 0.000 claims description 28
- 230000015572 biosynthetic process Effects 0.000 claims description 22
- 239000010949 copper Substances 0.000 claims description 17
- 229910052802 copper Inorganic materials 0.000 claims description 17
- 150000001879 copper Chemical class 0.000 claims description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 8
- 238000000227 grinding Methods 0.000 claims description 7
- 238000010422 painting Methods 0.000 claims 1
- 238000000576 coating method Methods 0.000 abstract description 9
- 239000011248 coating agent Substances 0.000 abstract description 7
- 230000000694 effects Effects 0.000 abstract 1
- 235000012431 wafers Nutrition 0.000 description 46
- 239000010410 layer Substances 0.000 description 34
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 24
- 229910052751 metal Inorganic materials 0.000 description 17
- 239000002184 metal Substances 0.000 description 17
- 239000004642 Polyimide Substances 0.000 description 6
- 229920001721 polyimide Polymers 0.000 description 6
- 239000000758 substrate Substances 0.000 description 6
- 230000008901 benefit Effects 0.000 description 4
- 229920002521 macromolecule Polymers 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 239000005368 silicate glass Substances 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 208000027418 Wounds and injury Diseases 0.000 description 1
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 208000014674 injury Diseases 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 150000004760 silicates Chemical class 0.000 description 1
- 238000001228 spectrum Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06524—Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01019—Potassium [K]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01075—Rhenium [Re]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19043—Component type being a resistor
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
本发明涉及一种集成电路结构的形成方法,包括:提供一底部晶片,包括多个底部半导体芯片;提供多个上裸片,所述多个裸片接合至所述多个底部半导体芯片;形成一包围环于该底部晶片之上,且靠近该底部晶片的一***;涂覆一保护材料以填充所述多个上裸片的间隙,其中该保护材料的上表面、所述多个上裸片的上表面与该包围环的上表面等高;形成一平坦介电层于所述多个上裸片与该保护材料之上;以及形成一导电特征于该平坦介电层中,其中该导电特征电性连接到所述多个上裸片与所述多个底部半导体芯片至少之一,且该导电特征的上表面与该平坦介电层的上表面等高。本发明可达到降低电阻、降低工艺成本以及改善可靠度的效果。
Description
技术领域
本发明涉及一种集成电路结构,且特别是涉及一种裸片对晶片(die-to-wafer)的接合方法。
背景技术
从集成电路的发明以来,由于各种电子元件(例如晶体管,二极管,电阻等等)的整合密度不断的提升,使得半导体工业连续快速地成长。对大多数元件而言,整合密度的提升来自于不断地降低特征尺寸,以允许更多的元件整合于既定面积之中。
这些整合在本质上属于二维(2D)的提升,其中集成元件所占的体积实质上位于半导体晶片的表面上。虽然光刻技术的显著提升造成2D集成电路在形成时相当多的改进,然而对于2D空间可达到的密度仍有物理上的限制。其中之一的限制在于需要微小尺寸以构成这些元件。此外,当越多元件置于一芯片时,需要越复杂的设计。
另外一项额外的限制在于,当元件数目增加时,元件间的内连线数目与长度会显著的增加。当内连线数目与长度增加时,电路RC延迟与功率消耗两者皆会增加。为了解决上述的限制,因此衍生出三维(3D)集成电路(ICs)。于一般3D IC形成过程中,会形成两个晶片,其中两者皆包含具有集成电路的多个半导体芯片。接着将上述两晶片接合在一起。之后形成深的孔洞用以连接两个晶片中的集成电路。
公知形成3D IC的方法也包括裸片对晶片的接合,其中多个裸片接合到一晶片上。裸片对晶片接合的优点在于裸片的尺寸可以小于晶片上芯片的尺寸。典型的裸片对晶片接合工艺的过程,裸片之间会留下间隙。图1与图2显示一公知的裸片对晶片接合工艺的中间步骤剖面图。请参见图1,裸片100堆叠于包含半导体芯片104的晶片102之上。半导体芯片104大于(或等于)裸片100,且裸片100之间留下间隙(或切割道)106。于后续工艺步骤期间,如图2所示,裸片100被薄化,例如厚度降至约30μm,所以位于裸片100之上的硅通孔(through-silicon vias,TSV)110暴露出来。接合垫(图中未显示)可以形成于裸片100的表面上且连接到硅通孔110。
上述的裸片对晶片接合工艺存在许多缺点。在薄化裸片100的过程中,会有不想要的物质(例如水气、薄化过程产生的粒子、以及有害化学物质)可能掉入间隙106,也可能降低半导体芯片104的效率。目前,尚未有有效的方法能移除不想要的物质。再者,如图2所示,现有的结构具有受限的输入/输出数目。部分的原因是因为硅通孔100(或可能连接到接合垫的其他导电特征)需要足够大的间距以容纳接合垫。另外,很难于裸片100之上形成金属化层。对于形成介电层的设备,例如化学气相沉积设备,化学气相沉积会拒绝在图2的结构表面上形成薄膜,因为其上表面对该设备而言太粗糙。为解决上述问题,需要一种新的裸片对晶片堆叠方法。
发明内容
为克服现有技术的缺陷,本发明提供一种集成电路结构,包括:一底部半导体芯片;一上裸片接合至该底部半导体芯片上;一保护材料包围该底部裸片与位于该底部半导体芯片之上;以及一平坦介电层位于该上裸片与该保护材料之上。该保护材料的上表面与该上裸片的上表面等高。
本发明提供另一种半导体电路结构,包括一包含多个底部半导体芯片的底部晶片;多个上裸片接合至所述多个底部半导体芯片之一;一保护材料填充上裸片的间隙;一包围环位于该底部晶片之上,且靠近该底部晶片的***,其中该保护材料的上表面、所述多个上裸片的上表面与该包围环的上表面等高;一平坦介电层位于所述多个上裸片与该保护材料之上,其中该平坦介电层延伸覆盖实质上所有的所述多个上裸片与该保护材料;以及一导电特征位于该平坦介电层中。该导电特征电性连接至所述多个上裸片与所述多个底部半导体晶片至少之一。
本发明提供另一种集成电路结构,包括一底部晶片,其包括多个底部半导体芯片;多个上裸片接合至所述多个底部半导体芯片;一保护材料填充所述多个上裸片的间隙;一包围环位于该底部晶片之上,且靠近该底部晶片的***,其中该保护材料的上表面、所述多个裸片的上表面与该包围环的上表面实质上等高;一平坦介电层位于所述多个上裸片与该保护材料之上,其中该平坦介电层实质上延伸至整个底部晶片上;以及一铜线位于该平坦介电层中,其中该铜线电性连接至所述多个上裸片与所述多个底部半导体芯片至少之一,且该铜线的一上表面与该平坦介电层的上表面等高。
本发明提供另一集成电路的形成方法,包括:提供一底部晶片,包括多个底部半导体芯片;提供多个上裸片,所述多个裸片接合至所述多个底部半导体芯片;形成一包围环于该底部晶片之上,且靠近该底部晶片的一***;涂覆一保护材料以填充所述多个上裸片的间隙,其中该保护材料的上表面、所述多个上裸片的上表面与该包围环的上表面等高;形成一平坦介电层于所述多个上裸片与该保护材料之上;以及形成一导电特征于该平坦介电层中,其中该导电特征电性连接到所述多个上裸片与所述多个底部半导体芯片至少之一,且该导电特征的上表面与该平坦介电层的上表面等高。
本发明又提供另一集成电路的形成方法,包括:提供一底部晶片,包括多个底部半导体芯片;接合多个上裸片至所述多个底部半导体芯片;形成一包围环于该底部晶片之上,且靠近该底部晶片的一***;涂覆一保护材料以填充所述多个上裸片的间隙,其中该保护材料被该包围环包围;固化该保护材料;研磨以平坦化该保护材料、所述多个上裸片与该包围环;形成一平坦介电层于所述多个上裸片、该保护材料与该包围环之上;以及形成一铜线于该平坦介电层中。该铜线电性连接到所述多个上裸片与所述多个底部半导体芯片至少之一,且该铜线的上表面与该平坦介电层的上表面等高。
本发明的优点包括降低电阻、降低工艺成本以及改善可靠度。
为让本发明的上述和其他目的、特征、和优点能更明显易懂,下文特举出优选实施例,并配合附图,作详细说明如下。
附图说明
图1和图2为一系列中间步骤的剖面图,用以说明公知的裸片到晶片的接合工艺。
图3~9为一系列中间步骤的剖面图,用以说明本发明一优选实施例的工艺;
并且,上述附图中的附图标记说明如下:
100~裸片
102~晶片
104~半导体芯片
106~间隙
110~硅通孔
10~晶片
12~裸片
14~裸片的前表面
16~裸片的背表面
18~半导体基材
20~硅通孔
30~半导体芯片
32~半导体芯片的前表面
34~半导体芯片的背表面
35~间隙
36~包围环
38~***
40~保护材料
42~掩模
44~开口
48~平坦上表面
50~接点
51~接合垫
54~介电层
56~金属线
60~金属化层
62~金属化层
66~接合垫
T1~包围环厚度
T2~裸片厚度
T3~保护材料厚度
T4~薄化后裸片厚度
具体实施方式
下文特举出本发明的优选实施例。须了解本发明提供了许多可实施的发明概念,可依各种变化方式据以实施。此处的实施例仅为揭露本发明使用的特定方式,其并非用以限定本发明。
堆叠裸片于晶片上的方法的中间步骤显示于图3至图9。以下讨论优选的实施例。各种图式与实施例中类似的元件将用类似的元件符号标出。
请参见图3,裸片12接合到晶片10之上。每一裸片12具有前表面14与背表面16。每一个裸片包括半导体基材18,其中裸片12的背表面16也是个别半导体基材18的背表面。于一实施例中,裸片12包括硅通孔(through-silicon vias,TSV)20从前表面14延伸入半导体基材18,其中硅通孔20连接到半导体芯片30上。于另一实施例,不预先形成硅通孔20于裸片12,硅通孔20形成于薄化裸片12之后,于下文中作详细讨论。
晶片10包括多个半导体芯片30。于一实施例中,每一裸片12接合至一个半导体芯片30。此外,一个半导体芯片30可能有超过一个裸片12接合于其上。于此例中,接合至相同的半导体芯片30的裸片12可能具有相同或不同的电路设计,及/或尺寸。本文中裸片12本意指上裸片12,而半导体芯片30意指底部芯片30。
晶片10具有前表面32与背表面34,其中接合垫14及/或其他连接结构靠近前表面32,而背表面34则为半导体基材的背表面。集成电路(未显示)包括主动与被动元件,例如晶体管、电阻、电容,以及类似的元件,形成于上裸片12的半导体基材的前表面与底部芯片30上。
上裸片12与底部晶片30优选为面对面接合,其中接合的方法包括一般公知的方法,例如氧化物对氧化物接合,氧化物对硅接合、铜对铜的接合,以及类似的方法。由于底部芯片30大于(或等于)其上方的上裸片12,因此上裸片12之间会留下间隙(或切割道)35。
图4A显示形成包围环36的方法。包围环36优选包围裸片12,且靠近晶片10的***38。包围环36的***稍微远离该晶片10的***38以留下边缘。图4B显示图4A的俯视图。于一实施例中,于晶片10上涂覆具有高粘度的可固化材料(例如高分子)以形成包围环36,当晶片10旋转时,涂覆该高分子。于一实施例中,包围环36由聚酰亚胺(polyimide)或其他耐热的高分子涂料组成,例如苯环丁烯(benzocyclobuenes,BCB)、SilkTM(Dow chemical)或其他类似的高分子。于另一实施例中,包围环36由干膜组成,例如聚酰亚胺(polyimide)干膜或ETERTEC HT-100(Eternal)干膜,且压合于晶片10之上。于一优选实施例,如图4A所示,包围环36的厚度T1大于上裸片12薄化之后的残余厚度T4(请参见图6,约30μm),但是小于上裸片12薄化前的厚度T2(请参见图4)。于另一实施例,厚度T1实质上等于厚度T2。当包围环36由可固化材料所组成时,需进行预烘烤以固化该包围环36。
图5A显示涂布保护材料40于间隙35中。于一实施例中,类似包围环36,保护材料40由一可固化材料所组成,例如高分子,可使用与包围环36相同或不同的材料。于一示范实施例中,保护材料40由聚酰亚胺(polyimide)组成。保护材料40的厚度T3可大于薄化后的裸片12厚度T4(请参见图6),但小于裸片12的厚度T2。据此,如图5B所示,保护材料40可以用网版涂覆(screen coating),其中掩模42用于遮蔽裸片12,所以保护材料40不会涂布到裸片12的上和包围环36的外的晶片10部分。掩模42包括开口44用以对应到间隙35。于另一实施例中,如图5C所示,保护材料40利用孔版涂布(stencil coating)涂覆进入间隙35,其中保护材料40是毯覆式涂布,于裸片12的上的过量保护材料40被刮除。于此例中,包围环36的厚度T1需要实质上接近裸片12的厚度T2。
包围环36能防止保护材料40弄脏晶片12及/或晶片12的底部,否则不但有害地影响后续光刻工艺,也会造成产生更多不想要的粒子。涂布保护材料40之后,进行烘烤以固化保护材料40以及进一步固化包围环36。
请参见图6,研磨上裸片12、保护材料40以及包围环38,例如利用化学机械研磨(CMP)。例如上裸片12的残余厚度T4大约30μm。然而,最佳的厚度可以大于或小于30μm。研磨之后形成一平坦的上表面48,若是硅通孔20预先形成时,经由上表面48露出所述多个硅通孔20。
图7显示接触插塞50的形成,若硅通孔20未预先形成时,也可能是在此时形成硅通孔20。于此例中,硅通孔20未预先形成,形成的硅通孔20用以连接底部芯片30的集成电路,例如借由蚀刻或激光钻孔进入裸片12以形成开口,以及利用导电材料(例如铜、钨、铝、银或上述的组合)填充此开口。未填充开口前,阻障层与绝缘层可先(图中未显示)形成于开口的侧壁。若硅通孔20已经预先形成,则可省略形成硅通孔。硅通孔20可以连接到上裸片12及/或底部芯片30。当底部芯片30大于上裸片12,可以于保护材料40之中形成接点50,用以连接底部芯片30的集成电路(或内连线结构,如金属线、金属垫片或其他类似的结构)。于此例中,接点50可以连接底部芯片30的表面上的接合垫51,或穿过底部芯片30表面上的保护层直达底下的导电垫。
图8显示于上裸片12与保护材料40之上形成介电层54。若需要时,一蚀刻停止层(图中未显示)可形成于介电层54和上裸片12之间。金属线/垫片56(之后称为金属线56)形成于介电层54间且电性连接到硅通孔20及/或接点50。可利用一般公知方法形成介电层54和金属线56,例如单镶嵌工艺。另外地,可利用毯覆式地沉积金属薄膜形成金属线56,图案化此金属薄膜,以及填充介电层54于金属线56的间隙。金属线56可由铜、铝、钨、银或上述的组合而组成。介电层54可由氧化物、氮化物、未掺杂的硅酸盐玻璃、氟化硅酸盐玻璃、低介电(low-k)材料或其他类似材料所组成。
图9显示形成更多层的内连线层,例如金属化层60和62。视需要可以形成更多层。每一金属化层包括一介电层与介于介电层之间的导电特征,其中导电特征(例如,铜或铜合金组成的金属线)可借由双镶嵌工艺而得。于金属化层60和62的导电特征连接到金属线56。此处须注意的是,图8的结构类似公知的晶片(除了公知晶片不包含封装于内的裸片)。因此,这些方法和结构可应用于公知晶片上制备内连线结构。于形成内连线层之后,形成接合垫66。接着,堆叠的裸片沿着虚线被切开。切割后之裸片12中,保护材料40包围并保护上裸片12的侧壁,且保护材料40的***垂直对应到个别底部芯片30的***。
本发明的实施例具有许多优点。借由填充保护材料40于上裸片12的间隙以形成一平坦表面,可使用一般公知的方法形成内连线结构。此点显著地扩大上裸片12与底部芯片30的设计上的弹性。例如,于上裸片12的上形成较小间距的硅通孔20,其中硅通孔20的连接线路可重新被改变,经由形成于上裸片12的上的内连线结构到位于其上的接合垫66(请参见图9),使接合垫的间距大于硅通孔20的间距。接点/硅通孔可形成于保护材料中,用以连接上裸片12及/或底部芯片30。甚至于,借由填充保护材料40于上裸片12的间隙,能实质上消除水气或其他有害物质造成对上裸片12与底部芯片30的伤害。
虽然本发明已用数个优选实施例揭示如上,然其并非用以限定本发明,任何本领域普通技术人员,在不脱离本发明的精神和范围内,当可作任意的更动与润饰,因此本发明的保护范围当视所附的权利要求所界定范围为准。
Claims (15)
1.一种集成电路结构的形成方法,包括下列步骤:
提供一底部晶片,包括多个底部半导体芯片;
提供多个上裸片,所述多个上裸片接合至所述多个底部半导体芯片;
形成一包围环于该底部晶片之上,且靠近该底部晶片的一***;
涂覆一保护材料以填充所述多个上裸片的间隙,其中该保护材料的上表面、所述多个上裸片的上表面与该包围环的上表面等高;
形成一平坦介电层于所述多个上裸片与该保护材料之上;以及
形成一导电特征于该平坦介电层中,其中该导电特征电性连接到所述多个上裸片与所述多个底部半导体芯片至少之一。
2.如权利要求1所述的集成电路结构的形成方法,其中形成该包围环的步骤包括:
涂覆一高分子环;以及
在涂覆该保护材料步骤之前,预烘烤该高分子环。
3.如权利要求1所述的集成电路结构的形成方法,其中形成该包围环的步骤包括压合一干膜作为该包围环。
4.如权利要求1所述的集成电路结构的形成方法,其中在形成该包围环与涂覆该保护材料步骤之后,进行一平坦化,以平整该保护材料、所述多个上裸片的上表面以及该包围环的上表面。
5.如权利要求4所述的集成电路结构的形成方法,还包括:平坦化步骤之后,形成一TSV于所述多个上裸片之一中,其中该导电特征连接到该TSV。
6.如权利要求4所述的集成电路结构的形成方法,还包括:平坦化步骤之后,形成一接触插塞穿过该保护材料,其中该接触插塞连接到该导电特征以及所述多个底部半导体芯片。
7.如权利要求1所述的集成电路结构的形成方法,其中涂覆该保护材料的步骤包括孔版印刷。
8.如权利要求1所述的集成电路结构的形成方法,其中涂覆该保护材料的步骤包括利用一掩模进行网版印刷,该掩模具有开口对应到所述多个上裸片的间隙。
9.如权利要求1所述的集成电路结构的形成方法,其中该导电特征的上表面与该平坦介电层的上表面等高。
10.一种集成电路结构的形成方法,包括下列步骤:
提供一底部晶片,包括多个底部半导体芯片;
接合多个上裸片至所述多个底部半导体芯片;
形成一包围环于该底部晶片之上,且靠近该底部晶片的一***;
涂覆一保护材料以填充所述多个上裸片的间隙,其中该保护材料被该包围环包围;
固化该保护材料;
研磨以平坦化该保护材料、所述多个上裸片与该包围环;
形成一平坦介电层于所述多个上裸片、该保护材料与该包围环之上;以及
形成一铜线于该平坦介电层中,其中该铜线电性连接到所述多个底部半导体芯片与所述多个上裸片至少之一。
11.如权利要求10所述的集成电路结构的形成方法,其中所述多个上裸片与所述多个底部半导体芯片是面对面接合。
12.如权利要求10所述的集成电路结构的形成方法,其中研磨之后,露出所述多个上裸片中的多个硅通孔,且其中该铜线连接到所述多个硅通孔之一。
13.如权利要求10所述的集成电路结构的形成方法,还包括:研磨之后,形成一TSV于所述多个上裸片之一中,其中该铜线连接到该TSV。
14.如权利要求10所述的集成电路结构的形成方法,还包括:研磨之后,形成一接触插塞穿过该保护材料,其中该接触插塞连接该铜线与所述多个底部半导体芯片。
15.如权利要求10所述的集成电路结构的形成方法,其中该铜线的上表面与该平坦介电层的上表面等高。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/140,695 US7951647B2 (en) | 2008-06-17 | 2008-06-17 | Performing die-to-wafer stacking by filling gaps between dies |
US12/140,695 | 2008-06-17 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN101609804A CN101609804A (zh) | 2009-12-23 |
CN101609804B true CN101609804B (zh) | 2011-11-09 |
Family
ID=41415169
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN200810170436XA Expired - Fee Related CN101609804B (zh) | 2008-06-17 | 2008-11-03 | 集成电路结构的形成方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US7951647B2 (zh) |
CN (1) | CN101609804B (zh) |
TW (1) | TWI367532B (zh) |
Families Citing this family (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5352220B2 (ja) * | 2008-12-17 | 2013-11-27 | ラピスセミコンダクタ株式会社 | 半導体装置の製造方法 |
US7979813B2 (en) * | 2009-01-15 | 2011-07-12 | Micrel, Inc. | Chip-scale package conversion technique for dies |
US8378480B2 (en) * | 2010-03-04 | 2013-02-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Dummy wafers in 3DIC package assemblies |
US9141157B2 (en) * | 2011-10-13 | 2015-09-22 | Texas Instruments Incorporated | Molded power supply system having a thermally insulated component |
US9082764B2 (en) | 2012-03-05 | 2015-07-14 | Corning Incorporated | Three-dimensional integrated circuit which incorporates a glass interposer and method for fabricating the same |
US10049964B2 (en) | 2012-03-23 | 2018-08-14 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming a fan-out PoP device with PWB vertical interconnect units |
US9842798B2 (en) | 2012-03-23 | 2017-12-12 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming a PoP device with embedded vertical interconnect units |
US8810024B2 (en) * | 2012-03-23 | 2014-08-19 | Stats Chippac Ltd. | Semiconductor method and device of forming a fan-out PoP device with PWB vertical interconnect units |
US20130249101A1 (en) * | 2012-03-23 | 2013-09-26 | Stats Chippac, Ltd. | Semiconductor Method of Device of Forming a Fan-Out PoP Device with PWB Vertical Interconnect Units |
US8697542B2 (en) | 2012-04-12 | 2014-04-15 | The Research Foundation Of State University Of New York | Method for thin die-to-wafer bonding |
US9406577B2 (en) * | 2013-03-13 | 2016-08-02 | Globalfoundries Singapore Pte. Ltd. | Wafer stack protection seal |
US9768089B2 (en) * | 2013-03-13 | 2017-09-19 | Globalfoundries Singapore Pte. Ltd. | Wafer stack protection seal |
CN105023877B (zh) | 2014-04-28 | 2019-12-24 | 联华电子股份有限公司 | 半导体晶片、封装结构与其制作方法 |
US10283496B2 (en) * | 2016-06-30 | 2019-05-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrated circuit filler and method thereof |
CN108336037B (zh) * | 2017-09-30 | 2022-02-11 | 中芯集成电路(宁波)有限公司 | 一种晶圆级***封装结构和电子装置 |
CN111133576A (zh) | 2018-01-03 | 2020-05-08 | 英特尔公司 | 具有多层的解聚集的堆叠的半导体管芯架构 |
US10734285B2 (en) * | 2018-06-28 | 2020-08-04 | Taiwan Semiconductor Manufacturing Co., Ltd. | Bonding support structure (and related process) for wafer stacking |
CN112005249A (zh) * | 2019-03-05 | 2020-11-27 | 华为技术有限公司 | 一种用于裸片保护的电路、裸片及集成电路 |
US20210035918A1 (en) * | 2019-07-31 | 2021-02-04 | Nanya Technology Corporation | Semiconductor structure and fabrication method thereof |
US11682652B2 (en) * | 2021-03-10 | 2023-06-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Notched wafer and bonding support structure to improve wafer stacking |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5629835A (en) * | 1994-07-19 | 1997-05-13 | Olin Corporation | Metal ball grid array package with improved thermal conductivity |
US6383893B1 (en) * | 2000-12-28 | 2002-05-07 | International Business Machines Corporation | Method of forming a crack stop structure and diffusion barrier in integrated circuits |
CN1452217A (zh) * | 2002-04-15 | 2003-10-29 | 裕沛科技股份有限公司 | 晶圆型态封装及其制作方法 |
CN1627490A (zh) * | 2003-11-20 | 2005-06-15 | 台湾积体电路制造股份有限公司 | 集成电路晶片封装及其封装方法 |
CN1926681A (zh) * | 2004-01-06 | 2007-03-07 | 国际商业机器公司 | 用于低-k的互连结构的柔顺的钝化边缘密封 |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4518992B2 (ja) * | 2005-03-31 | 2010-08-04 | Okiセミコンダクタ株式会社 | 半導体チップパッケージ及びその製造方法 |
KR100714566B1 (ko) * | 2005-08-24 | 2007-05-07 | 삼성전기주식회사 | Fbar 소자의 제조 방법 |
-
2008
- 2008-06-17 US US12/140,695 patent/US7951647B2/en not_active Expired - Fee Related
- 2008-10-20 TW TW097140151A patent/TWI367532B/zh not_active IP Right Cessation
- 2008-11-03 CN CN200810170436XA patent/CN101609804B/zh not_active Expired - Fee Related
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5629835A (en) * | 1994-07-19 | 1997-05-13 | Olin Corporation | Metal ball grid array package with improved thermal conductivity |
US6383893B1 (en) * | 2000-12-28 | 2002-05-07 | International Business Machines Corporation | Method of forming a crack stop structure and diffusion barrier in integrated circuits |
CN1452217A (zh) * | 2002-04-15 | 2003-10-29 | 裕沛科技股份有限公司 | 晶圆型态封装及其制作方法 |
CN1627490A (zh) * | 2003-11-20 | 2005-06-15 | 台湾积体电路制造股份有限公司 | 集成电路晶片封装及其封装方法 |
CN1926681A (zh) * | 2004-01-06 | 2007-03-07 | 国际商业机器公司 | 用于低-k的互连结构的柔顺的钝化边缘密封 |
Also Published As
Publication number | Publication date |
---|---|
TWI367532B (en) | 2012-07-01 |
TW201001567A (en) | 2010-01-01 |
US20090311829A1 (en) | 2009-12-17 |
CN101609804A (zh) | 2009-12-23 |
US7951647B2 (en) | 2011-05-31 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN101609804B (zh) | 集成电路结构的形成方法 | |
TWI664685B (zh) | 具有無矽基底的中介層的封裝及其形成方法 | |
CN101740484B (zh) | 形成穿透硅通孔的方法 | |
US9960129B2 (en) | Hybrid bonding mechanisms for semiconductor wafers | |
KR102026537B1 (ko) | 실리콘 기판이 없는 인터포저를 구비한 패키지와 그 형성 방법 | |
US8405225B2 (en) | Three-dimensional integrated circuits with protection layers | |
US8436448B2 (en) | Through-silicon via with air gap | |
KR20210144931A (ko) | 기판의 직접 접합의 준비에서 프로브 패드의 표면 손상을 경감시키는 방법 | |
CN107039380A (zh) | 接合结构及其形成方法 | |
TWI418000B (zh) | 半導體結構及其形成方法 | |
JP2010166052A (ja) | 低k誘電体ライナーを有するシリコン貫通ビア | |
US11302662B2 (en) | Semiconductor package with air gap and manufacturing method thereof | |
US11908838B2 (en) | Three-dimensional device structure including embedded integrated passive device and methods of making the same | |
US11855130B2 (en) | Three-dimensional device structure including substrate-embedded integrated passive device and methods for making the same | |
TW201308542A (zh) | 凸塊接墊結構 | |
US20230369157A1 (en) | Semiconductor die, manufacturing method thereof, and semiconductor package | |
US20220059468A1 (en) | Method for manufacturing semiconductor package with air gap | |
US11682642B2 (en) | Integrated circuit (IC) device including a force mitigation system for reducing under-pad damage caused by wire bond | |
US20230377968A1 (en) | Redistribution layer metallic structure and method | |
US20230360946A1 (en) | Method for forming semiconductor structure |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20111109 |
|
CF01 | Termination of patent right due to non-payment of annual fee |