CN101536314B - 用于直接数字插值合成的方法和设备 - Google Patents
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- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
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Abstract
一种时钟合成电路,包括Δ‑∑调制器,该Δ‑∑调制器接收分频比并产生整数部分和数字量化误差(分数部分)。分数‑N分频器根据对应于该整数部分的分频控制值对所接收的信号进行分频,并产生已分频信号。相位内插器根据该数字量化误差调整该已分频信号的相位,由此降低与该分数‑N分频器相关的噪声。
Description
技术领域
本发明涉及产生用于电子设备的时钟信号。
背景技术
时钟合成器产生多种电子产品所采用的时钟信号。典型的合成器采用被供有来自如晶体振荡器之类的源的基准信号的锁相环(PLL)。合成器所提供的信号的输出频率可以由PLL中的反馈分频器的分频值来确定。因此,提供给PLL的基准频率是基于分频值“倍增的”,从而产生合成的时钟频率。
在PLL中,已经采用了几种类型的分频器电路。一种分频器是对输入信号进行整数分频的整数-N分频器。例如,图1A示出包括二分频、三分频和四分频的几种整数分频的时序图。被分频的信号为CLKin。注意到在分频过程中,除了来自非理想化电路的噪声,没有引入任何波动。图1B示出由D触发器(DFF)101提供的简单的2分频。
另一种类型的PLL结构采用分数-N分频器。图2和图3示出分数-N分频。分数-N分频改变整数分频值以匹配所需要的比。因此,提供接近所需要的比的整数流。例如,图2示出2.25分频的时序图。输入时钟(CLKin)由具有一个单位时间(UI)周期的波形201示出。分数-N分频器的输出由波形203示出。如波形203所示,假定采用一阶Δ-∑调制器控制分数-N分频器,通过三个周期的2分频和一个周期的3分频的序列实现2.25分频。波形205示出2.25分频的理想波形。在分数-N分频器的输出位置,以在207、209和211处的波形203所示的分数-N分频器的实际输出和波形205所示的2.25分频的理想输出之间的差别示出调制器的量化噪声。
图3示出具有分数-N反馈分频器303的PLL300。Δ-∑调制器301向分数-N反馈分频器303提供分频序列。分数-N分频器303接收对应于需要的分频器值的分频值序列。分数-N分频器303向相位检波器305提供伴有与分数-N分频器的性质相关联的噪声的已分频信号。在分数-N合成中,分数-N噪声可由PLL环过滤掉。此外,可采用相位误差校正以处理由分频器通过在PLL中引入偏移量而引入的波动,其中该偏移量对应于由该分数-N分频器产生的波动。
然而,以上所述的时钟合成器可具有有限的频率范围(整数分频器)和/或要求复杂的环形滤波器和复杂的VCO控制,这将增加设计工作的成本和芯片面积,从而形成时钟合成器的主要部分在成本或不动产上过高的更贵的产品。
因此,希望提供一种低成本、灵活的时钟合成器方案。
发明内容
因此,在一个实施例中,提供一种设备,其包括分数-N分频器,该分数-N分频器配置为接收信号并且根据Δ-∑调制器所供给的分频控制信号提供已分频信号。该Δ-∑调制器配置为接收分频比,并产生整数部分和数字量化误差。对应于该整数部分的分频控制信号被提供给该分数-N分频器用于控制分频。相位内插器耦合至该分数-N分频器并耦合至该Δ-∑调制器以根据该Δ-∑调制器所提供的该数字量化误差调整该已分频信号的相位,从而降低与该分数-N分频器相关的噪声。
在另一实施例中,提供一种方法,该方法包括接收Δ-∑调制器中的分频值,并且将该Δ-∑调制器所产生的整数值作为控制值提供给分数-N分频器。该分数-N分频器根据对应于该整数部分的控制值对信号进行分频并产生已分频信号。相位内插器根据该Δ-∑调制器的数字量化误差调整该已分频信号,从而降低与该分数-N分频器相关的噪声。
附图说明
参照附图,本发明会更好理解,且对本领域技术人员来说,它的多个目标、特征和优点是显然的。
图1A示出整数分频。
图1B示出提供简单分频电路以提供二分频的电路。
图2示出示例性分数-N分频操作的时序图。
图3示出具有分数-N反馈分频器的PLL。
图4示出合并多个插值分频器以产生多个独立输出的插值时钟合成器的实施例。
图5示出插值分频器的实施例。
图6示出插值分频器的实施例的附加细节。
图7示出插值分频器的实施例的附加细节。
图8示出示例性插值分频操作的时序图。
图9示出提供四个可用于插值分频中的相位内插器的时钟相位的环形振荡器。
图10示出用来产生可被相位内插器使用的信号的四个时钟相位的应用。
图11示出图10中的电路所产生的可被相位内插器使用的四个时钟相位。
图12A示出可***值分频器使用的相位内插器的实施例。
图12B示出提供供给相位内插器的相位的时序图。
图13示出利用自激振荡器和插值分频器的时钟合成器的实施例。
在不同的附图中使用相同的附图标记表示相似或等同的部分。.
具体实施方式
参照图4,其示出插值时钟合成器400的示例性结构。该结构包括具有相位/频率检测器(PFD)403、环形滤波器405和压控振荡器(VCO)407的PLL 401。该环形滤波器可采用数字环形滤波器以避免需要芯片外电容器。该VCO可采用环形振荡器或LC振荡器。也可采用其它的振荡器结构。PFD 403接收基准时钟信号,该基准时钟信号可来自诸如晶体振荡器或微机电结构(MEMS)振荡器的固定源409。
PLL 401还包括分频器411。非易失性存储器415向分频器411提供分频比。此外,提供一个或多个插值分频器417,其接收VCO 407输出信号420。应当指出,分频器411也可采用插值分频器。出于灵活性考虑,还可提供整数分频器419。分频器417和419供给输出驱动器421。插值分频器417接收来自NVM 415的分频比422。
参照图5,其示出示例性插值分频器417。该分频器包括分数-N分频器501,该分数-N分频器501接收VCO时钟420。一阶Δ-∑调制器接收非易失性存储器或其它存储单元所存储的数字分频比(M/N)。例如,集成电路上的编程接口向可编程寄存器提供分频比。该数字分频比的整数部分作为整数流中的分频控制信号506供给分数-N分频器501,以接近实际分频比。对应于该分频比的分数部分的数字量化误差提供给数控相位内插器507。通过基于Δ-∑调制器505所提供的数字量化误差的相位内插器507中的插值,由分数-N分频器501引入的波动被消除。因此,根据由Δ-∑调制器505提供的控制信息,VCOCLK由分数-N分频器下分频。相位内插器507用于消除分数-N分频器501的输出中的量化误差。
图6示出Δ-∑调制器505的附加细节。此外,示出了一个实施例,其中数字相位内插器接收用于插值的两个信号601(CLKA)和603(CLKB)。从分数-N分频器501供给信号603。锁存器605也接收来自分数-N分频器的输出603并将信号601提供给数字相位内插器。锁存器使分频器的输出延迟VCO的一个半时钟周期,允许该内插器在这两个信号之间进行插值。
图7示出一个实施例,其中提供给相位内插器706的信号来自D触发器701和锁存器703。触发器701耦接至分频器的输出。提供给相位内插器706的两个信号702和704间隔VCO时钟的一个半周期。
图8示出2.25分频的内插器的操作。VCO供给波形801中示出的CLKin。分数-N分频器接收2,2,2,3,2,2,2,3,...,的分频值流,其产生如波形803所示的分频输出(Divout)。理想的波形如理想输出805所示。通过基于Δ-∑调制器所提供的量化误差508在信号601和603(或者702和704)之间进行插值,从而示出消除波动的内插器输出信号。
在一个实施例中,除了基于将被提供给内插器的仅有的两个信号(例如601和603)的插值,图9所示的VCO电路产生VCO时钟的四个相等间隔的相位。CLKO作为VCO时钟提供给分数-N分频器。在图10中,所述四个相位用来产生图11所示的波形。随后,根据数字量化误差,内插器可采用四个相位中的合适的相位产生适当地插值的波形。将环形振荡器的多个时钟相位提供给数字相位内插器能够改善其线性,由此减小输出波动。相位内插器线性最终将由环形振荡器各级的延迟失配所限制。延迟 线也可用于产生VCO时钟的多个相位,该VCO时钟的所述多个相位将被用来产生用于相位插值的分频器输出的多个相位。
应当指出,环形振荡器的多个时钟相位也可用于提供给分数-N分频器以降低量化噪声。然而,降低的量化噪声增加了用来确定利用哪个时钟相位来最小化量化误差的转换复杂性。
在一个实施例中,内插器在基于数字量化误差的数字控制和用于分数-N分频器的输出信号的相位调节之间提供线性关系。图12A示出示例性内插器507。CLKA、CLKA、CLKB和CLKB提供给内插器507。图12B示出CLKA、CLKA、CLKB和CLKB的示例性波形。CLKA和CLKB对应于图6中以601和603示出的CLKA和CLKB,且CLKA和CLKB是它们的反向。应当指出,虽然为了便于理解,图6示出为单向终止电路(single-endedcircuit),但差分电路是优选的。在图12A的实施例中,四个电流源1205、1207、1209和1211耦合以确定在节点1215供给的插值的差分输出时钟信号CLKOUT。数字量化误差用于控制电流源1205、1207、1209和1211的工作。例如,假定Δ-∑调制器的数字量化误差是8位。两位用于选择使用图12中所示的哪个电流源。采用两位,可以选择多达四对不同的电流源。例如,参照图12A和图12B,如果量化误差表示适当插值的波形应当在区域1230中,则内插器利用CLKA和CLKB并选择电流源1205和1207用于插值。类似地,如果量化误差表示适当插值的波形应当在区域1232中,则内插器可以利用电流源1207和1209在CLKB和CLKA之间进行插值。类似地,内插器也可根据量化误差采用其它合适的电流源对。基于诸如所要求的精度、功耗考虑、设计复杂度、可利用的芯片面积和用来表示数字量化误差的位数等因素,可采用许多其它的内插器实施方式。
对于基于数字量化误差的各种电流源,假定8位量化误差中的两位用来选择电流源对,6位可用来产生用于CTL0、CTL1、CTL2和CTL3的合适的控制值,以提供合适的数模转换(DAC)控制,如电流强度。这样的技术在本领域是公知的。
应当指出,图8示出的波形小于50%占空比。通过采用伴随插值块(interpolationblock)的2分频或修改上升和下降沿的相位内插器,能够实现50%占空比。
还参照图6,在一个实施例中,通过经过求和块617供给数字偏斜控制615,能够提供扩展频谱时钟调制(spread spectrum clock modulation)。由数字偏斜控制/扩展频谱调制状态机617供给的数字偏斜确保由时钟合成器产生的频率在中心频率附近扩展,这例如有助于确保满足关于RF发射的需求。
参照图13,示出一个利用自激振荡器(free running oscillator)1301的实施例。使用伴随自激振荡器的插值分频器允许使用具有很窄或没有调谐范围(tuning range)的振荡器,例如具有固定电容器的LC振荡器或基于MEMS的振荡器。而且,采用自激振荡器消除了用于LC或环形振荡器或其它振荡器结构的变容二极管控制的需要。对于LC振荡器电路而言,消除变容二极管并采用固定电容器降低了与变容二极管相关的噪声。
自激振荡器1301向插值分频器1305供给振荡器输出信号1303。在一个实施例中,在1304向相位和频率检测器(PFD)1307供给校正时钟。该PFD 1307向环形滤波器提供所检测的来自插值分频器1305的反馈信号和1304上的校正时钟之间的差别。环形滤波器1309向插值分频器1305供给过滤的相位差。该过滤的相位差用来调节插值分频器1305的分频比M1和分频比M2。在校正期间,频率测量环1306测量自由摆动VCO1301的输出和校正时钟之间的频率关系。
自激振荡器1301还供给按分频比M2分频的插值分频器1311。例如根据所需要的输出频率和M1的值确定M2。例如,如果所需要的输出频率为75MHz,且校正时钟的频率为25MHz,则M2=M1/3。根据由插值分频器1305向插值分频器1311供给的反映PFD1309所检测的相位差的控制信号1312调整M2的值。
基于该校正操作,经调整的M2的值可存储在NVM中。在正常工作期间,可关闭频率测量环,使自激振荡器1301和插值分频器1311在开环的配置中工作。因此,图13示出的实施例可用作少源(source-less)时钟合成器,例如具有还提供宽范围输出频率的固定自激振荡器的少晶体时钟源(crystal-less clock source)。应当指出,可能需要温度补偿来调整分频比M2,以解决由温度变化引起的自激振荡器中的变化。因此,在一个实施例中,温度补偿电路1320采用温度传感器感测温度。温度补偿电路1320 还包括用于将所感测的温度转换为数字值的模数转换器(ADC)电路,然后该数字值可与所存储的M2的值相加,以根据所检测的温度调整插值分频器。由于温度补偿电路在本领域是公知的,所以不再描述其细节。
在此所阐述的本发明的描述是说明性的,并不限制后文的权利要求所阐述的本发明的保护范围。例如,在不偏离后文的权利要求所阐述的本发明的保护范围的前提下,基于在此进行的描述,可对在此公开的各实施例进行变化和修改。
Claims (17)
1.一种时钟合成设备,包括:
分数-N分频器,该分数-N分频器配置为接收信号,并供给根据分频控制信号进行分频的已分频信号;
Δ-∑调制器,该Δ-∑调制器耦合为接收分频比且产生整数部分和数字量化误差,并且将该整数部分作为分频控制信号提供给该分数-N分频器;及
相位内插器,该相位内插器耦合至该分数-N分频器并耦合至Δ-∑调制器,以根据该数字量化误差调整已分频信号的相位,从而降低已分频信号中的误差,
其中相位内插器被配置成至少接收第一信号和第二信号,所述第一信号具有第一相位且所述第二信号具有不同于第一相位的第二相位,所述第一信号和第二信号是以所述已分频信号为基础的,该相位内插器被配置成根据数字量化误差在所述第一相和所述第二相之间进行插值,从而调整已分频信号的相位。
2.根据权利要求1所述的时钟合成设备,进一步包括:
压控振荡器,该压控振荡器被耦合以产生所述信号;和
被耦合以接收所述信号的多个内插分频器,每个内插分频器包括分数-N分频器、Δ-∑调制器和相位内插器,其中压控振荡器被耦合为向每个内插分频器的分数-N分频器供给所述信号。
3.根据权利要求1所述的时钟合成设备,进一步包括供给数字偏斜控制信号的数字偏斜控制逻辑电路,该数字偏斜控制信号提供给该Δ-∑调制器用于提供已分频信号的扩展频谱调制。
4.根据权利要求2所述的时钟合成设备,进一步包括包含该压控振荡器的锁相环。
5.根据权利要求4所述的时钟合成设备,其中该锁相环包括:
反馈分频器,该反馈分频器是插值分频器。
6.根据权利要求4所述的时钟合成设备,进一步包括耦合为向该锁相环进行供给的固定频率源。
7.根据权利要求6所述的时钟合成设备,其中该固定频率源是晶体振荡器和MEMS振荡器中的一个。
8.根据权利要求1至7中的任一项所述的时钟合成设备,进一步包括耦合至该Δ-∑调制器以供给该分频比的非易失性存储器。
9.根据权利要求1所述的时钟合成设备,还包括向该分数-N分频器供给信号的自激振荡器。
10.根据权利要求9所述的时钟合成设备,还包括温度补偿电路,该温度补偿电路耦合为与存储的分频比的值相加,以根据所检测的温度调整该分频比。
11.一种插值合成方法,包括:
在Δ-∑调制器中接收分频比,并产生对应于该分频比的整数部分和数字量化误差,并且将该整数部分作为分频值供给分数-N分频器;
在该分数-N分频器中,根据该分频值对信号进行分频,并产生已分频信号;以及
在耦合到该分数-N分频器的相位内插器中,根据该数字量化误差来调整已分频信号的相位,从而降低已分频信号中的误差,
其中调整已分频信号的相位的步骤还包括:
在相位内插器处接收具有不同相位的至少两个信号,这两个信号是以所述已分频信号为基础的;以及
由相位内插器根据数字量化误差在两个相位之间进行插值,从而调整已分频信号的相位。
12.根据权利要求11所述的插值合成方法,进一步包括从压控振荡器将所述信号供给该分数-N分频器。
13.根据权利要求11所述的插值合成方法,进一步包括向该Δ-∑调制器供给数字偏斜控制信号,以提供扩展频谱调制。
14.根据权利要求12所述的插值合成方法,进一步包括:
从包括压控振荡器的锁相环供给所述信号;及
在该锁相环的分频器电路中,对来自所述压控振荡器的反馈信号进行分频。
15.根据权利要求14所述的插值合成方法,进一步包括向该锁相环的相位和频率检测器供给信号,该信号来自与该锁相环耦合的固定频率源。
16.根据权利要求11所述的插值合成方法,进一步包括从耦合到该Δ-∑调制器的非易失性存储器供给该分频比。
17.一种时钟合成设备,包括:
用于提供对应于分频比的整数部分的已分频信号的分数-N分频器;
Δ-∑调制器,该Δ-∑调制器耦合为接收分频比且产生整数部分和数字量化误差,并且将该整数部分作为分频控制信号提供给该分数-N分频器;及
用于根据对应于该分频比的分数部分的数字量化误差来调整已分频信号的相位的相位内插器。
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Also Published As
Publication number | Publication date |
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US8531246B2 (en) | 2013-09-10 |
US20110057693A1 (en) | 2011-03-10 |
US7417510B2 (en) | 2008-08-26 |
WO2008039766A2 (en) | 2008-04-03 |
EP2092646B1 (en) | 2014-10-29 |
EP2092646A4 (en) | 2010-10-13 |
CN101536314A (zh) | 2009-09-16 |
US7839225B2 (en) | 2010-11-23 |
US20080315963A1 (en) | 2008-12-25 |
EP2092646A2 (en) | 2009-08-26 |
US20080079502A1 (en) | 2008-04-03 |
WO2008039766A3 (en) | 2009-02-12 |
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