SE0301005D0 - Method and system of jitter compensation - Google Patents
Method and system of jitter compensationInfo
- Publication number
- SE0301005D0 SE0301005D0 SE0301005A SE0301005A SE0301005D0 SE 0301005 D0 SE0301005 D0 SE 0301005D0 SE 0301005 A SE0301005 A SE 0301005A SE 0301005 A SE0301005 A SE 0301005A SE 0301005 D0 SE0301005 D0 SE 0301005D0
- Authority
- SE
- Sweden
- Prior art keywords
- jitter
- fractional
- integer
- jitter compensation
- storing
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
- H03L7/1974—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division
- H03L7/1976—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division using a phase accumulator for controlling the counter or frequency divider
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Dc Digital Transmission (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
- Pulse Circuits (AREA)
Priority Applications (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
SE0301005A SE0301005D0 (sv) | 2003-04-03 | 2003-04-03 | Method and system of jitter compensation |
US10/550,568 US7907016B2 (en) | 2003-04-03 | 2004-03-12 | Method and system of jitter compensation |
DE602004005689T DE602004005689T2 (de) | 2003-04-03 | 2004-03-12 | Verfahren und system zur jitter-kompensation |
EP04720312A EP1609243B1 (en) | 2003-04-03 | 2004-03-12 | Method and system of jitter compensation |
AT04720312T ATE358911T1 (de) | 2003-04-03 | 2004-03-12 | Verfahren und system zur jitter-kompensation |
PCT/SE2004/000369 WO2004088846A1 (en) | 2003-04-03 | 2004-03-12 | Method and system of jitter compensation |
CN200480009020.XA CN1768479B (zh) | 2003-04-03 | 2004-03-12 | 用于抖动补偿的方法和*** |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
SE0301005A SE0301005D0 (sv) | 2003-04-03 | 2003-04-03 | Method and system of jitter compensation |
Publications (1)
Publication Number | Publication Date |
---|---|
SE0301005D0 true SE0301005D0 (sv) | 2003-04-03 |
Family
ID=20290944
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SE0301005A SE0301005D0 (sv) | 2003-04-03 | 2003-04-03 | Method and system of jitter compensation |
Country Status (7)
Country | Link |
---|---|
US (1) | US7907016B2 (sv) |
EP (1) | EP1609243B1 (sv) |
CN (1) | CN1768479B (sv) |
AT (1) | ATE358911T1 (sv) |
DE (1) | DE602004005689T2 (sv) |
SE (1) | SE0301005D0 (sv) |
WO (1) | WO2004088846A1 (sv) |
Families Citing this family (42)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102005060470A1 (de) * | 2005-12-17 | 2007-06-21 | Atmel Germany Gmbh | PLL-Frequenzgenerator |
DE102005060472B3 (de) * | 2005-12-17 | 2007-04-26 | Atmel Germany Gmbh | PLL-Frequenzgenerator |
US7315215B2 (en) * | 2006-03-08 | 2008-01-01 | Motorola,, Inc. | Direct digital synthesizer with variable reference for improved spurious performance |
US7417510B2 (en) * | 2006-09-28 | 2008-08-26 | Silicon Laboratories Inc. | Direct digital interpolative synthesis |
US8149022B2 (en) | 2007-02-09 | 2012-04-03 | Mediatek Inc. | Digital delay line based frequency synthesizer |
US7764134B2 (en) | 2007-06-14 | 2010-07-27 | Silicon Laboratories Inc. | Fractional divider |
US8379787B2 (en) * | 2007-11-15 | 2013-02-19 | Mediatek Inc. | Spread spectrum clock generators |
US8644441B2 (en) | 2007-11-15 | 2014-02-04 | Mediatek Inc. | Clock generators and clock generation methods thereof |
WO2009062953A1 (en) * | 2007-11-16 | 2009-05-22 | Nxp B.V. | Jitter compensation |
CN101217277B (zh) * | 2008-01-15 | 2010-12-29 | 凌阳科技股份有限公司 | 非整数除频器以及可产生非整数时脉信号的锁相回路 |
JP2009250807A (ja) * | 2008-04-07 | 2009-10-29 | Seiko Epson Corp | 周波数測定装置及び測定方法 |
CN101262225B (zh) * | 2008-04-11 | 2011-02-16 | 湖南大学 | 锁相环频率合成器 |
US8076978B2 (en) * | 2008-11-13 | 2011-12-13 | Infineon Technologies Ag | Circuit with noise shaper |
US8138840B2 (en) * | 2009-01-23 | 2012-03-20 | International Business Machines Corporation | Optimal dithering of a digitally controlled oscillator with clock dithering for gain and bandwidth control |
JP2010271091A (ja) * | 2009-05-20 | 2010-12-02 | Seiko Epson Corp | 周波数測定装置 |
JP5517033B2 (ja) * | 2009-05-22 | 2014-06-11 | セイコーエプソン株式会社 | 周波数測定装置 |
JP5440999B2 (ja) * | 2009-05-22 | 2014-03-12 | セイコーエプソン株式会社 | 周波数測定装置 |
JP5582447B2 (ja) * | 2009-08-27 | 2014-09-03 | セイコーエプソン株式会社 | 電気回路、同電気回路を備えたセンサーシステム、及び同電気回路を備えたセンサーデバイス |
JP5815918B2 (ja) * | 2009-10-06 | 2015-11-17 | セイコーエプソン株式会社 | 周波数測定方法、周波数測定装置及び周波数測定装置を備えた装置 |
JP5876975B2 (ja) * | 2009-10-08 | 2016-03-02 | セイコーエプソン株式会社 | 周波数測定装置及び周波数測定装置における変速分周信号の生成方法 |
TW201121246A (en) * | 2009-12-14 | 2011-06-16 | Univ Nat Taiwan | Frequency synthesizers |
US8588720B2 (en) * | 2009-12-15 | 2013-11-19 | Qualcomm Incorproated | Signal decimation techniques |
JP5883558B2 (ja) | 2010-08-31 | 2016-03-15 | セイコーエプソン株式会社 | 周波数測定装置及び電子機器 |
GB2483898B (en) * | 2010-09-24 | 2015-07-22 | Cambridge Silicon Radio Ltd | Injection-locked oscillator |
US8248175B2 (en) | 2010-12-30 | 2012-08-21 | Silicon Laboratories Inc. | Oscillator with external voltage control and interpolative divider in the output path |
US8497716B2 (en) * | 2011-08-05 | 2013-07-30 | Qualcomm Incorporated | Phase locked loop with phase correction in the feedback loop |
CN103368567B (zh) * | 2012-04-06 | 2016-03-30 | 联咏科技股份有限公司 | 频率合成器 |
US9474492B2 (en) | 2012-05-22 | 2016-10-25 | Siemens Medical Solutions Usa, Inc. | Adaptive ECG trigger signal jitter detection and compensation for imaging systems |
JP6094730B2 (ja) * | 2012-11-07 | 2017-03-15 | セイコーエプソン株式会社 | 周波数変換回路、原子発振器、電子機器及び周波数変換回路の制御方法 |
US8866519B1 (en) * | 2013-02-28 | 2014-10-21 | Pmc-Sierra Us, Inc. | System and method for reducing spectral pollution in a signal |
CN105322962B (zh) * | 2014-07-03 | 2019-01-29 | 清华大学 | 频率振荡器稳定度优化装置及方法 |
CN104506190B (zh) | 2014-12-18 | 2017-03-08 | 华为技术有限公司 | 数字小数分频锁相环控制方法及锁相环 |
US9838026B2 (en) | 2015-09-24 | 2017-12-05 | Analog Devices, Inc. | Apparatus and methods for fractional-N phase-locked loops with multi-phase oscillators |
US9985639B2 (en) | 2016-01-05 | 2018-05-29 | Infineon Technologies Ag | Detection and mitigation of non-linearity of phase interpolator |
CN105959003B (zh) | 2016-04-25 | 2019-02-26 | 华为技术有限公司 | 数字分频锁相环 |
US9806880B1 (en) | 2016-06-15 | 2017-10-31 | Qualcomm Incorporated | Dynamic adjustment of a response characteristic of a phase-locked loop digital filter |
WO2018160569A1 (en) | 2017-03-01 | 2018-09-07 | Analog Devices Global Unlimited Company | Feedforward phase noise compensation |
US10680624B2 (en) * | 2018-03-07 | 2020-06-09 | Analog Devices Global Unlimited Company | Phase-locked loop with filtered quantization noise |
US10707881B1 (en) * | 2019-06-13 | 2020-07-07 | Globalfoundries Inc. | Adaptive noise cancellation |
CN111934681B (zh) * | 2020-08-02 | 2024-07-05 | 珠海一微半导体股份有限公司 | 一种微展频小数分频器、锁相环、芯片及微展频控制方法 |
US11387833B1 (en) * | 2021-09-03 | 2022-07-12 | Qualcomm Incorporated | Differential digital-to-time converter for even-order INL cancellation and supply noise/disturbance rejection |
CN117969978A (zh) * | 2022-10-25 | 2024-05-03 | 华为技术有限公司 | 电源噪声检测电路及工作方法、抖动限幅电路、电子设备 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5642082A (en) * | 1996-06-20 | 1997-06-24 | Altera Corporation | Loop filter level detection circuit and method |
US6011815A (en) * | 1997-09-16 | 2000-01-04 | Telefonaktiebolaget Lm Ericsson | Compensated ΔΣ controlled phase locked loop modulator |
US5907253A (en) * | 1997-11-24 | 1999-05-25 | National Semiconductor Corporation | Fractional-N phase-lock loop with delay line loop having self-calibrating fractional delay element |
US6064272A (en) * | 1998-07-01 | 2000-05-16 | Conexant Systems, Inc. | Phase interpolated fractional-N frequency synthesizer with on-chip tuning |
CA2281522C (en) * | 1999-09-10 | 2004-12-07 | Philsar Electronics Inc. | Delta-sigma based two-point angle modulation scheme |
US6346838B1 (en) * | 2001-01-05 | 2002-02-12 | Taiwan Semiconductor Manufacturing Corporation | Internal offset-canceled phase locked loop-based deskew buffer |
-
2003
- 2003-04-03 SE SE0301005A patent/SE0301005D0/sv unknown
-
2004
- 2004-03-12 US US10/550,568 patent/US7907016B2/en active Active
- 2004-03-12 WO PCT/SE2004/000369 patent/WO2004088846A1/en active Application Filing
- 2004-03-12 AT AT04720312T patent/ATE358911T1/de not_active IP Right Cessation
- 2004-03-12 DE DE602004005689T patent/DE602004005689T2/de not_active Expired - Lifetime
- 2004-03-12 EP EP04720312A patent/EP1609243B1/en not_active Expired - Lifetime
- 2004-03-12 CN CN200480009020.XA patent/CN1768479B/zh not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US20090072913A1 (en) | 2009-03-19 |
US7907016B2 (en) | 2011-03-15 |
ATE358911T1 (de) | 2007-04-15 |
CN1768479B (zh) | 2011-08-31 |
CN1768479A (zh) | 2006-05-03 |
WO2004088846A1 (en) | 2004-10-14 |
EP1609243A1 (en) | 2005-12-28 |
EP1609243B1 (en) | 2007-04-04 |
DE602004005689D1 (de) | 2007-05-16 |
DE602004005689T2 (de) | 2007-12-27 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
SE0301005D0 (sv) | Method and system of jitter compensation | |
US9548750B2 (en) | Circuit, a time-to-digital converter, an integrated circuit, a transmitter, a receiver and a transceiver | |
DE60020742D1 (de) | Frequenzteilung/vervielfachung mit minimierung des jitters | |
US8138840B2 (en) | Optimal dithering of a digitally controlled oscillator with clock dithering for gain and bandwidth control | |
WO2007079098A3 (en) | A novel method of frequency synthesis for fast switching | |
WO2008021810A3 (en) | Reference signal generation for multiple communication systems | |
TW200718024A (en) | Delay-locked loop system and related method | |
WO2007104010A3 (en) | Direct digital synthesizer with variable reference for improved spurious performance | |
US20110095830A1 (en) | Direct digital synthesizer for reference frequency generation | |
GB2483898A (en) | Injection-locked oscillator capable of non-integer frequency multiplication | |
GR3030223T3 (en) | Digital controlled xtal osc | |
ATE553532T1 (de) | Digitaler phasendetektor für einen phasenregelkreis | |
KR102123901B1 (ko) | 완전 디지털 위상 고정 루프 회로, 반도체 장치 및 휴대 정보 기기 | |
WO2007130750A3 (en) | Phase-slipping phase-locked loop | |
MY126186A (en) | Digital frequency multiplier | |
GB0906418D0 (en) | Digital phase-locked loop architecture | |
TW200709571A (en) | Fractional frequency synthesizer and phase-locked loop utilizing fractional frequency synthesizer and method thereof | |
US20140072077A1 (en) | Transmitter | |
TW200633392A (en) | Sigma-delta based phase lock loop | |
EP1889366A4 (en) | SCALE GENERATOR FOR A N-FRACTIONAL SYNTHESIZER | |
US10429882B2 (en) | Clock generator and processor system | |
TW200718019A (en) | Fractional-n frequency synthesizer with sigma-delta modulator for variable reference frequencies and related method thereof | |
GB2436984A (en) | Phase persistent agile signal source method,apparatus,and computer program product | |
WO2007067631A3 (en) | Skew correction system eliminating phase ambiguity by using reference multiplication | |
TW200505166A (en) | Phase locked loop system capable of deskewing and method therefor |