CN101506965B - 半导体芯片、半导体安装模块、移动装置通信设备、半导体芯片的制造方法 - Google Patents
半导体芯片、半导体安装模块、移动装置通信设备、半导体芯片的制造方法 Download PDFInfo
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- CN101506965B CN101506965B CN2007800307732A CN200780030773A CN101506965B CN 101506965 B CN101506965 B CN 101506965B CN 2007800307732 A CN2007800307732 A CN 2007800307732A CN 200780030773 A CN200780030773 A CN 200780030773A CN 101506965 B CN101506965 B CN 101506965B
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Abstract
本发明提供一种具有可有效抑制LSI的电压下降的电容器的半导体芯片。在半导体基板上,设置至少其表面是由铝电极形成的元件电极。对所述铝电极的表面进行粗面化。在所述铝电极上设置氧化膜。在所述氧化膜上设置导电膜。由所述铝电极、所述氧化膜、和所述导电膜形成电容器。
Description
技术领域
本发明涉及半导体芯片,特别是涉及在电极上形成电容器的半导体芯片。本发明还涉及具备如此的半导体芯片的半导体安装模块以及电容器的形成方法。
背景技术
在半导体集成电路(以下,称为「LSI」)中若施加急速变化的负载,则由在电源和LSI之间的布线上存在的寄生电阻或寄生电感产生电压下降。此时,寄生电阻或寄生电感大且负载电流的变动时间越短,电压下降得越大。近年来,LSI的工作频率成为从数百MHz到GHz程度,由于时钟的启动时间变得非常短,电压下降也越来越大,易于引起LSI的误动作(例如,参照专利文献1)。
为了减小如此的电压下降,在LSI的电源线与地线之间并列地配置电容器是有效的。这样的电容器,一般地称为去耦电容器(decouplingcapacitor)或旁路电容器(bypass capacitor)。
为了抑制LSI的电压下降,去耦电容器优选尽可能地在LSI的近旁进行配置。这样,若离开LSI而配置电容器,则布线长变长,由此L成分(电感成分)变大而会产生延迟。因此,如图1所示,多数情况为接近于安装在印刷基板11上的半导体芯片(LSI)12的周围来配置去耦电容器13。
[专利文献1]特开2002-33453号公报
然而,在图1表示的配置例中,在印刷基板上的安装面积变大,不利于电子设备的小型轻量化。即,伴随电子设备的小型化·薄型化、高性能化,安装于印刷基板的电子零件的安装面积受到进一步制约,例如搭载于手机的印刷基板的情况,即使作为经验知道优选在接近LSI的周围来配置去耦电容器,但在布线基板上确保安装它的区域是困难的。或者,安装去耦电容器比安装其它零件的区域要受到更进一步大的限制。
此外,专利文献1中虽公开了在半导体设备(LSI)的最上层形成了薄膜电容器的技术,但对用于抑制LSI的电压下降的去耦电容器需要电容较大的电容器,在专利文献1中所公开的薄膜电容器的构造上,电容不足以来抑制LSI的电压下降。
如此,在以往的技术中,难于解决为了抑制LSI的电压下降而确保电容器所需要的电容与安装面积之间的问题。
发明内容
本发明鉴于上述的问题点而提出,其主要目的在于,提供形成用于抑制LSI电压下降的合适的电容器的半导体芯片。
本发明的半导体芯片,是在具有半导体集成电路的半导体基板上,设置至少其表面是由铝电极形成且与所述半导体集成电路连接的元件电极,
对所述铝电极的表面进行粗面化,
在所述铝电极上设置氧化膜,
在所述氧化膜上设置导电膜,
由所述铝电极、所述氧化膜、和所述导电膜形成电容器。
在优选的实施方式中,对所述铝电极的表面进行粗面化,直到具有50倍以上的扩面率的状态。
在优选的实施方式中,将所述铝电极的表面粗面化到具有50倍-120倍的扩面率的状态。
在优选的实施方式中,将所述铝电极的表面粗面化到具有100倍的扩面率的状态。
在优选的实施方式中,所述导电膜由导电性高分子构成。
在优选的实施方式中,所述元件电极的一部分由钝化膜覆盖。
在优选的实施方式中,所述元件电极,由多个金属层构成,
多个金属层的最下层,形成在半导体基板上,
在所述最下层上,经由基底电极而形成所述铝电极。
本发明的半导体安装模块,具备所述半导体芯片和安装所述半导体芯 片的安装基板。
在优选的实施方式中,具备本发明的半导体安装模块而构成便携式移动通信设备。
本发明的电容器的形成方法,包括:
对具有半导体集成电路和与所述半导体集成电路连接的多个元件电极的半导体芯片进行准备的工序;
覆盖所述多个元件电极而在所述半导体芯片的元件电极形成面形成基底电极的工序;
在位于各个所述元件电极的上方的所述基底电极表面部位,选择性地形成铝电极的工序;
在对所述基底电极施加了电压的状态下,使所述铝电极进行阳极氧化,对该铝电极的表面进行粗面化,并且在该铝电极上形成氧化膜的工序;和
在所述氧化膜上形成导电膜的工序。
根据本发明,通过在半导体芯片的铝电极上形成电容器,能够在半导体芯片的极近的位置上配置去耦电容器,并且该电容器,由于具有在粗面化了的表面所形成的表面积大的氧化膜(电介质),所以电容比较大。由此,可有效抑制半导体芯片(LSI)的电压下降,此外,可解决安装面积的问题。
附图说明
图1是表示在半导体芯片的周围配置了去耦电容器的结构例的俯视图。
图2A是模式化表示本发明的实施方式的半导体安装模块200的结构的剖视图。
图2B是模式化表示本发明的实施方式的半导体芯片100的结构的剖视图。
图3A是模式化表示本发明的实施方式的电容器50的主要部分的结构的剖视图。
图3B是进一步模式化表示本发明的实施方式的电容器50的主要部分的结构的剖视图。
图4A是用于说明电容器50的制造方法的工序图(1)。
图4B是用于说明电容器50的制造方法的工序图(2)。
图4C是用于说明电容器50的制造方法的工序图(3)。
图4D是用于说明电容器50的制造方法的工序图(4)。
图5A是用于说明电容器50的制造方法的工序图(5)。
图5B是用于说明电容器50的制造方法的工序图(6)。
图6A是用于说明电容器50的制造方法的工序图(7)。
图6B是用于说明电容器50的制造方法的工序图(8)。
图6C是用于说明电容器50的制造方法的工序图(9)。
图7是模式化表示本发明的实施方式的移动装置通信设备的结构的立体图。
图中:10-基板(半导体基板),11-印刷基板,13-去耦电容器,20-铝电极(元件电极),20A-铝电极(上部电极),22-氧化膜,24-导电膜(固体电解质),26-碳糊,27-银膏,28-镀Ni/Au电极(阻障金属),30-钝化膜,40-基底电极(供电层),42-光刻胶,43-开口部,50-电容器,100-半导体芯片,200-半导体安装模块,300-移动装置通信设备。
具体实施方式
本发明的发明者,探讨了在对安装面积有严格限制的电子设备(例如便携移动通信设备)的印刷基板上,优选将去耦电容器(或者旁路电容器)进行什么样的配置。去耦电容器,如果越接近半导体芯片来进行配置,则越能够排除L成分的影响,但实际上,在要求高密度安装的印刷基板上,只为了去耦电容器优先来确保安装区域是困难的。其中,本发明的发明者,虽然想出在半导体芯片的元件电极(铝电极)上直接形成电容器的想法,但若只是在半导体芯片上仅形成电容器,则与在专利文献1(特开2002-33453号公报)中所公开的发明相同,难于确保为了抑制LSI的电压下降所需要的电容。
立足于此,本发明的发明者,对在铝电极上形成能够确保较大电容的去耦电容器(电容器)的方法进行专心探讨研究而作出本发明。
以下,一边参照附图,一边对本发明的实施方式进行说明。在以下的附图中,为了简化说明,将具有实质上相同的功能的结构要素用相同的参照符号来表示。并且,本发明不限定于以下的实施方式。
一边参照图2A、图2B以及图3A、图3B,一边对本发明的实施方式的半导体安装模块进行说明。
图2A是模式化表示半导体安装模块200的整体结构,图2B是模式化表示本发明的实施方式的半导体芯片100的主要部分的截面结构,图3A、图3B是模式化表示形成于半导体芯片100的元件电极上的电容器50的结构。
本实施方式的半导体安装模块200,如图2A所示,具有安装基板210和半导体芯片(半导体集成电路)100。半导体芯片100安装于安装基板210的表面(图中,上面)。在安装基板210的表面设置了基板电极220。在半导体芯片100的底面(图中,下面),设置了铝电极(元件电极)20。基板电极220与铝电极(元件电极)20相对应,若半导体芯片100被安装于安装基板210上,则两电极220、20是相互对置的。在相对置的基板电极220与铝电极(元件电极)20之间设置了焊锡230,基板电极220和铝电极(元件电极)20通过焊锡230分别电连接。半导体芯片100和安装基板210的连接部位,是由密封树脂240来密封的。
半导体芯片100,如图2B所示,具有基板(半导体基板)10。在基板10上制成由硅等形成的半导体集成电路(LSI;未图示)。铝电极(元件电极)20与半导体集成电路电连接。在至少1个铝电极(元件电极)20上形成电容器即电容器50。
图3A是对电容器50进行了放大的示意图,图3B是进一步对图3A的电容器50的主要部分进行了放大的示意图。如图3A、图3B所示,铝电极(元件电极)20的表面被粗面化。在本发明中所谓粗面化,称为提高其表面的扩面率,具体而言,将表面的扩面率提高到50倍以上的状态定义为粗面化状态。进而在本发明中,将50~120倍当作优选的扩面率,最佳值是100倍左右。此外,如图3B所示,粗面化了的铝电极(元件电极)20的表面成为树状分支的复杂的形状,即,成为海绵状态。
在粗面化了的表面上形成氧化膜22。氧化膜22是构成铝电极(元件 电极)20的铝的氧化膜。即氧化膜22是对铝电极(元件电极)20的表面进行了粗面化后,通过氧化其表面而形成的。在氧化膜22上,形成导电膜(固定电解质)24,本实施方式的导电膜(固定电解质)24,例如由固体电解质、导电性高分子等(例如,聚吡咯(polyprrole)、聚噻吩(polythiophene)、聚苯胺(polyaniline))所构成。
在本实施方式的结构中,电容器50由铝电极(元件电极)20、氧化膜22和导电膜(固体电解质)24所构成。即,铝电极(元件电极)20形成下层电极,导电膜(固体电解质)24形成上层电极,其间的氧化膜22成为电介质。在图示的示例中,在导电膜(固体电解质)24上堆积了碳糊26,在其之上,形成镀Ni/Au电极(阻障金属(barrier metal))28。
并且,在本实施方式中,铝电极(元件电极)20的一部分,由形成于基板(半导体基板)10上的钝化(passivation)膜30所覆盖。钝化膜30,例如是由氮化物形成的膜(SiN膜等)或由聚酰亚胺(polyimide)膜形成,保护基板(半导体基板)10的表面。此外,基板(半导体基板)10不限于硅基板,也可以是由其它半导体材料所构成的基板(例如,SiC基板、GaN基板),而且,也可以如SOI基板那样由至少在表面形成半导体层的基板构成。
在本实施方式的半导体芯片100中,对铝电极(元件电极)20的表面进行粗面化,并且在该粗面化了的表面上形成铝的氧化膜22来形成电容器50。通过在半导体芯片100的铝电极(元件电极)20上形成电容器50,从而成为在LSI等的半导体芯片100的极近的位置上配置去耦电容器,即可形成实质上为零的L成分(电感成分)。此外,构成本实施方式的电容器50的电介质(氧化膜22),由于形成于粗面化了的铝电极(元件电极)20的表面,所以易于增加电容器的电容,其结果,能够实现可有效抑制半导体芯片100的电压下降的电容器50。例如,若在以50~120倍左右的扩面率来粗面化0.1mm2的铝电极(元件电极)20后,配备该铝电极20而形成电容器50,则该电容为0.1μF(或该值以上),对去耦电容器而言成为足够的值。
并且,本实施方式的电容器50,由于形成于半导体芯片100的铝电极(元件电极)20上,与在半导体芯片的周围另外配置电容部件(电容 器)的情况相比较,可避免印刷基板的安装面积的问题。即在本实施方式的半导体芯片100中,在铝电极(元件电极)20上形成了电容器50,所以在安装基板(印刷基板)上安装本实施方式的半导体芯片100来形成半导体安装模块时,在图1表示的示例中,不再需要位于半导体芯片12周围的去耦电容器13的区域。并且,用于安装半导体芯片100的安装基板(印刷基板),既可以是刚性基板,也可以是挠性基板或刚挠性基板。
此处,对图2A、图2B、以及图3A、图3B中表示的结构例的尺寸等举例表示如下。基板(半导体基板)10是厚度100μm的硅基板,铝电极(元件电极)20是厚度为40μm、长0.1mm×宽0.1mm的铝电极。并且,铝电极(元件电极)20的形状,不限于矩形,也可是其它的形状(例如圆形)。导电膜(固体电解质)24由聚吡咯形成,碳糊26的厚度是3μm作为镀Ni/Au电极(阻障金属)28,可使用Ni/Au镀层。
接着,一边参照图4A~图4D、图5A、图5B、图6A~图6C,一边对本实施方式的电容器50的制造方法进行说明。
首先,如图4A所示,准备形成了作为元件电极的铝电极(元件电极)20的半导体芯片。铝电极(元件电极)20形成于基板(半导体基板)10上,在图示的示例中,铝电极(元件电极)20的一部分(外缘部),虽由形成于基板(半导体基板)10上的钝化膜30所覆盖,但铝电极(元件电极)20的中央是露出的。
并且此处表示的半导体芯片,虽表示了在基板(半导体基板)上形成了铝电极(元件电极)20的半导体设备,但也可以将封装了裸芯片的半导体封装(例如芯片尺寸封装(CSP)等)作为半导体芯片来使用,也可以在该半导体封装的铝电极(元件电极)20上同样地形成铝电极20。
接着,如图4B所示,在基板(半导体基板)10或钝化膜30之上形成基底电极40以使覆盖铝电极(元件电极)20。基底电极40是在后面工序的阳极氧化时用于作为供电层发挥功能的电极。基底电极(供电层)40例如由Cr/Cu形成。基底电极(供电层)40的厚度,例如是0.05~2μm程度。
接着,如图4C所示,在基底电极(供电层)40上形成规定图案的光刻胶42。进而,在光刻胶42上,在与铝电极(元件电极)20同样的位置 上形成开口部。开口部43通过所周知的照相平版(Photolithography)技术而形成。
接着,如图4D所示,利用光刻胶42的开口部43,通过在基底电极(供电层)40上成膜铝,形成铝电极(上部电极)20A。铝电极(上部电极)20A,例如形成10~80μm程度的厚度。并且,如该示例,在元件电极由多个层所构成的情况下,铝电极(上部电极)20A可由铝构成,所以其下层的铝电极(元件电极)20也可由其它金属(例如铜)构成。
此后,如图5A所示,将基底电极(供电层)40作为供电层来施加交流电流,并在将盐酸作为主体的电解液中进行电解蚀刻来粗面化表面。此处,作为粗面化状态,称为增大基底电极40的表面的扩面率。此后,在中性的电解液中对基底电极(供电层)40施加电压,进行铝电极(上部电极)20A的阳极氧化。通过此阳极氧化,铝电极(上部电极)20A的表面进一步粗面化,并如图3B所示,扩面率增加至50~120倍左右,进而在其表面形成氧化膜22。施加的电压,例如是30~100V左右,并且,氧化膜22的厚度,例如是20~120nm左右。
在阳极氧化处理之后,如图5B所示,在基板(半导体基板)10或钝化膜30上形成导电膜(固体电解质)24,以使覆盖形成了氧化膜22的铝电极(上部电极)20A。导电膜(固体电解质)24,由于覆盖粗面化了的铝电极(上部电极)20A的表面,所以可在粗面化后的凹凸的间隙中进行填充。在此阶段,由于夹持成为电介质层的氧化膜22而形成导电层(20A、24),所以形成电容器50。并且,导电膜(固体电解质)24的厚度例如是1~3μm左右。
此后,如图6A所示,在覆盖铝电极(上部电极)20A的导电膜(固体电解质)24上层叠碳糊26。碳糊26的厚度,例如是0.1~5μm左右,银膏27的厚度,例如是3~15μm左右。
接着,如图6B所示,在银膏27的表面,形成镀Ni/Au电极(阻障金属)28。由此,得到在铝电极(上部电极)20A上形成了电容器50的半导体芯片100。
根据需要,如图6C所示,对光刻胶42和基底电极(供电层)40的无用的部分进行去除。该去除,例如可实施由碱溶液剥离光刻胶42,进 而由适于基底电极(供电层)40的材质的公知的蚀刻液来蚀刻基底电极(供电层)40的无用部分。此处,也可以残留光刻胶42的一部分(例如构成电容器50的层的下方),或者在去除了光刻胶42之后,为了保护电容器50也可提供新的其它材料(例如树脂)。
并且,在本实施方式中,虽然设置铝电极(上部电极)20A并在其上形成电容器50,但也可将基板(半导体基板)10上的铝电极(元件电极)20进行阳极氧化,来形成电容器50。此外,当替代Al电极而由钽或铌(niobium)构成电极时,也可以由该材料的氧化膜构筑电容器,但若考虑量产性·产品成本等,则使用Al电极技术意义更大。
此外,电容器50的形成之处,除了半导体裸芯片的元件电极之外,半导体裸芯片安装于***机构(interposer),在该***机构的电极安装于布线基板(印刷基板)上时,在该***机构的电极(即包括***机构的半导体封装的电极,或者包括***机构的半导体安装模块(例如,多片组件(multichip module)的电极)上,也可形成本实施方式的电容器50。
若是具备了本实施方式的电容器50的半导体芯片100,则如图7所示,即使在手机等对安装面积有严格制约的电子设备(例如便携式移动通信设备)300中所收纳的印刷基板310上,也能够容易地配置去耦电容器(或旁路电容器),并且该电容器50形成于半导体芯片的铝电极(元件电极)20上,所以实质上能够以零距离进行配置,可有效地排除L成分的影响。并且,若是本实施方式电容器50的结构,则可易于实现为了抑制LSI的电压下降确保所需要的电容。
并且,作为便携式移动通信设备,除了手机,虽然可列举安装面积的制约严格的PDA或笔记本计算机,但除此之外,即使针对数字照相机、数字摄像机、平板显示器(flat-panel display)等的电子设备,本实施方式的半导体芯片100也可广泛适用。
以上,虽通过优选的实施方式对本发明进行了说明,但此记述不是限定事项,当然,可有各种改变。
工业上利用的可能性
根据本发明,可提供形成了能够有效抑制LSI的电压下降的电容器的半导体芯片。
Claims (14)
1.一种半导体芯片,在具有半导体集成电路的半导体基板上,设置至少其表面是由铝电极形成且与所述半导体集成电路连接的多个元件电极,
对所述铝电极的表面进行粗面化,
在所述铝电极上设置氧化膜,
在所述氧化膜上设置导电膜,
由所述铝电极、所述氧化膜、和所述导电膜形成电容器。
2.根据权利要求1所述的半导体芯片,其特征在于,
对所述铝电极的表面进行粗面化,直到具有50倍以上的扩面率的状态。
3.根据权利要求1所述的半导体芯片,其特征在于,
将所述铝电极的表面粗面化到具有50倍-120倍的扩面率的状态。
4.根据权利要求1所述的半导体芯片,其特征在于,
将所述铝电极的表面粗面化到具有100倍的扩面率的状态。
5.根据权利要求1所述的半导体芯片,其特征在于,
所述导电膜由导电性高分子构成。
6.根据权利要求1所述的半导体芯片,其特征在于,
所述元件电极的一部分由钝化膜覆盖。
7.根据权利要求1所述的半导体芯片,其特征在于,
所述元件电极,由多个金属层构成,
多个金属层的最下层,形成在半导体基板上,
在所述最下层上,经由基底电极而形成所述铝电极。
8.一种半导体安装模块,具备:
权利要求1的半导体芯片;和
安装所述半导体芯片的安装基板。
9.一种便携式移动通信设备,具备:
权利要求8的半导体安装模块。
10.一种半导体芯片中的电容器的制造方法,包括:
对具有半导体集成电路和与所述半导体集成电路连接的多个元件电极的半导体芯片进行准备的工序;
覆盖所述多个元件电极而在所述半导体芯片的元件电极形成面形成基底电极的工序;
在位于各个所述元件电极的上方的所述基底电极表面部位,选择性地形成铝电极的工序;
在对所述基底电极施加了电压的状态下,使所述铝电极进行阳极氧化,对该铝电极的表面进行粗面化,并且在该铝电极上形成氧化膜的工序;和
在所述氧化膜上形成导电膜的工序。
11.根据权利要求10所述的半导体芯片的制造方法,其特征在于,
在对所述铝电极进行阳极氧化之前,由电解蚀刻预先对该铝电极的表面进行粗面化。
12.根据权利要求10所述的半导体芯片的制造方法,其特征在于,
对所述铝电极的表面进行粗面化,直到具有50倍以上的扩面率的状态。
13.根据权利要求10所述的半导体芯片的制造方法,其特征在于,
将所述铝电极的表面粗面化到具有50-120倍的扩面率的状态。
14.根据权利要求10所述的半导体芯片的制造方法,其特征在于,
将所述铝电极的表面粗面化到具有100倍的扩面率的状态。
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US (2) | US7943518B2 (zh) |
JP (1) | JP5094726B2 (zh) |
CN (1) | CN101506965B (zh) |
WO (1) | WO2008035536A1 (zh) |
Families Citing this family (4)
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KR101055501B1 (ko) * | 2010-02-12 | 2011-08-08 | 삼성전기주식회사 | 인쇄회로기판 및 인쇄회로기판의 제조방법 |
JP2013093405A (ja) * | 2011-10-25 | 2013-05-16 | Ngk Spark Plug Co Ltd | 配線基板及びその製造方法 |
KR102460748B1 (ko) * | 2017-09-21 | 2022-10-31 | 삼성전기주식회사 | 커패시터 부품 |
WO2023214491A1 (ja) * | 2022-05-02 | 2023-11-09 | 株式会社村田製作所 | 電子部品及びその製造方法 |
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- 2007-08-24 US US12/377,076 patent/US7943518B2/en not_active Expired - Fee Related
- 2007-08-24 JP JP2008535297A patent/JP5094726B2/ja not_active Expired - Fee Related
- 2007-08-24 CN CN2007800307732A patent/CN101506965B/zh not_active Expired - Fee Related
- 2007-08-24 WO PCT/JP2007/066409 patent/WO2008035536A1/ja active Application Filing
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2011
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GB1287110A (en) * | 1968-12-20 | 1972-08-31 | Philips Electronic Associated | Semiconductor devices |
US20030116348A1 (en) * | 1999-11-12 | 2003-06-26 | Matsushita Electric Industrial Co., Ltd. | Capacitor-mounted metal foil and a method for producing the same, and a circuit board and a method for producing the same |
US20040067605A1 (en) * | 2002-10-02 | 2004-04-08 | Shinko Electric Industries, Co., Ltd. | Semiconductor device having additional functional element and method of manufacturing thereof |
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Also Published As
Publication number | Publication date |
---|---|
JP5094726B2 (ja) | 2012-12-12 |
US20100164061A1 (en) | 2010-07-01 |
US7943518B2 (en) | 2011-05-17 |
WO2008035536A1 (fr) | 2008-03-27 |
CN101506965A (zh) | 2009-08-12 |
US8324623B2 (en) | 2012-12-04 |
JPWO2008035536A1 (ja) | 2010-01-28 |
US20110180900A1 (en) | 2011-07-28 |
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