US7943518B2 - Semiconductor chip, semiconductor mounting module, mobile communication device, and process for producing semiconductor chip - Google Patents

Semiconductor chip, semiconductor mounting module, mobile communication device, and process for producing semiconductor chip Download PDF

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US7943518B2
US7943518B2 US12/377,076 US37707607A US7943518B2 US 7943518 B2 US7943518 B2 US 7943518B2 US 37707607 A US37707607 A US 37707607A US 7943518 B2 US7943518 B2 US 7943518B2
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semiconductor chip
electrode
electrodes
aluminum
capacitor
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US20100164061A1 (en
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Koichi Hirano
Tetsuyoshi Ogura
Seiichi Nakatani
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Panasonic Corp
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Panasonic Corp
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Definitions

  • the present invention relates to a semiconductor chip, more particularly to a semiconductor chip where capacitors are formed on electrodes.
  • the present invention further relates to processes for forming a semiconductor mounting module comprising the semiconductor chip thus constituted and the capacitor.
  • LSI semiconductor integrated circuit
  • a voltage drop occurs due to a parasitic resistance and a parasitic inductance present in wirings between a power supply and the LSI.
  • the voltage drop is more increased as the parasitic resistance and the parasitic inductance are larger and a load current variation time is shorter.
  • the operation frequency of an LSI is as large as a few-hundred MHz or the order of a GHz, and a clock rising time is thereby significantly shortened. Therefore, the voltage drop is increasingly larger, which often causes the malfunctioning of the LSI (for example, see the Patent Document 1).
  • capacitors In order to lessen the voltage drop, it is effective to provide capacitors in parallel between a power supply line and a ground line of the LSI.
  • the capacitors thus provided are generally called decoupling capacitors or bypass capacitors.
  • the decoupling capacitors are preferably provided as close to the LSI as possible because a wiring length is increased when the capacitors are distant from the LSI, and an L component (inductance component) is increased, which unfavorably causes a delay.
  • a structure often adopted to deal with the disadvantage is to provide decoupling capacitors 13 in close vicinity of a semiconductor chip (LSI) 12 mounted on a printed substrate 11 as illustrated in FIG. 1 .
  • the layout example illustrated in FIG. 1 increases a mounting area on the printed substrate, which is disadvantageous in terms of the reduction of the dimensions and the weight of an electronic device.
  • the mounting area for electronic parts mounted on the printed substrate is subject to more restrictions.
  • decoupling capacitors are preferably provided in the periphery of the LSI as close thereto as possible, it is actually difficult to secure an area on the wiring substrate on which they are mounted, or the mounting of the decoupling capacitors puts more restrictions on an area where other parts are mounted.
  • the Patent Document 1 disclosed a constitution wherein thin-film capacitors are formed on an uppermost insulation film of a semiconductor device (LSI). Decoupling capacitors provided for controlling the voltage drop of the LSI are required to have a relatively large capacity.
  • the thin-film capacitor recited in the Patent Document 1 structurally does not have enough capacity to control the voltage drop of the LSI.
  • the present invention was made to solve the foregoing problems, and a main object thereof is to provide a semiconductor chip comprising capacitors suitable for controlling the voltage drop of an LSI.
  • a semiconductor chip according to the present invention has a semiconductor substrate provided with an element electrode having at least its surface constituted of an aluminum electrode, wherein
  • an electrically conductive film is provided on the oxide film, and
  • the aluminum electrode, the oxide film and the conductive film constitute a capacitor.
  • the surface of the aluminum electrode is roughened so as to have at least a 50-fold surface expansion ratio.
  • the surface of the aluminum electrode is roughened so as to have at least a 50-fold to 120-fold surface expansion ratio.
  • the surface of the aluminum electrode is roughened so as to have at least a 100-fold surface expansion ratio.
  • conductive polymer molecules constitute the conductive film.
  • a part of the element electrode is covered with a passivation film.
  • a plurality of metallic layers constitute the element electrode, a lowermost layer of the plurality of metallic layers is formed on the semiconductor substrate, and the aluminum electrode is formed on the lowermost layer with a underlaying electrode interposed therebetween.
  • a semiconductor mounting module comprises the semiconductor chip and a mounting substrate on which the semiconductor chip is mounted.
  • a mobile communication device comprises the semiconductor mounting module according to the present invention.
  • a process for producing a capacitor according to the present invention comprises steps of:
  • a decoupling capacitor can be located at a position very close to the semiconductor chip.
  • the capacitor which has the oxide film (dielectric member) having a large surface area formed on the roughened surface, has a relatively large capacity. Therefore, the voltage drop of the semiconductor chip (LSI) can be effectively controlled, and the disadvantage of the mounting area can be cleared at the same time.
  • FIG. 1 is an upper view illustrating an example of a constitution where decoupling capacitors are provided in the periphery of a semiconductor chip.
  • FIG. 2A is a sectional view schematically illustrating a constitution of a semiconductor mounting module 200 according to a preferred embodiment of the present invention.
  • FIG. 2B is a sectional view schematically illustrating a constitution of a semiconductor chip 100 according to the preferred embodiment.
  • FIG. 3A is a sectional view schematically illustrating a constitution of a main section of a capacitor 50 according to the preferred embodiment.
  • FIG. 3B is another sectional view schematically illustrating the constitution of the main section of the capacitor 50 according to the preferred embodiment.
  • FIG. 4A is a process chart ( 1 ) for describing a process for producing the capacitor 50 .
  • FIG. 4B is a process chart ( 2 ) for describing the process for producing the capacitor 50 .
  • FIG. 4C is a process chart ( 3 ) for describing the process for producing the capacitor 50 .
  • FIG. 4D is a process chart ( 4 ) for describing the process for producing the capacitor 50 .
  • FIG. 5A is a process chart ( 5 ) for describing the process for producing the capacitor 50 .
  • FIG. 5B is a process chart ( 6 ) for describing the process for producing the capacitor 50 .
  • FIG. 6A is a process chart ( 7 ) for describing the process for producing the capacitor 50 .
  • FIG. 6B is a process chart ( 8 ) for describing the process for producing the capacitor 50 .
  • FIG. 6C is a process chart ( 9 ) for describing the process for producing the capacitor 50 .
  • FIG. 7 is a perspective view schematically illustrating a mobile communication device according to the preferred embodiment.
  • the inventors of the present invention investigated what kind of layout is preferable for decoupling capacitors (or bypass capacitors) on a printed substrate of an electronic device (for example, a mobile communication device) subject to strict restrictions in a mounting area thereof.
  • the decoupling capacitors are preferably provided as close to the semiconductor chip as possible because influences from an L component can be thereby avoided.
  • the inventors of the present invention came up with such an idea that the capacitors are directly formed on the element electrodes (aluminum electrodes) of the semiconductor chip.
  • the inventors of the present invention examined a process for forming the decoupling capacitor which can secure a relatively large capacity on the aluminum electrode, and finally completed the present invention.
  • FIGS. 2A , 2 B, 3 A and 3 B a semiconductor mounting module according to the present preferred embodiment is described.
  • FIG. 2A illustrates an entire structure of a semiconductor mounting module 200 .
  • FIG. 2B schematically illustrates a cross-sectional structure of a main section of a semiconductor chip 100 according to the preferred embodiment.
  • FIGS. 3A and 3B schematically illustrate a structure of a capacitor 50 formed on the element electrode of the semiconductor chip 100 according to the preferred embodiment.
  • the semiconductor mounting module 200 comprises a mounting substrate 210 and the semiconductor chip (semiconductor integrated circuit) 100 as illustrated in FIG. 2A .
  • the semiconductor chip 100 is mounted on a surface (upper surface in the drawings) of the mounting substrate 210 .
  • Substrate electrodes 220 are provided on a surface of the mounting substrate 210
  • aluminum electrodes (element electrodes) 20 are provided on a bottom surface (lower surface in the drawings) of the semiconductor chip 100 .
  • the substrate electrodes 220 and the aluminum electrodes (element electrodes) 20 correspond to each other, and the electrodes 210 and 20 face each other when the semiconductor chip 100 is mounted on the mounting substrate 210 .
  • solders 230 Between the substrate electrodes 210 and the aluminum electrodes (element electrodes) 20 facing each other are provided solders 230 .
  • the substrate electrodes 210 and the aluminum electrodes (element electrodes) 20 are respectively electrically connected to each other by the solders 230 .
  • the sections where the semiconductor chip 100 and the mounting substrate 210 are connected to each other are sealed with sealing resin 240 .
  • the semiconductor chip 100 comprises a substrate (semiconductor substrate) 10 as illustrated in FIG. 2B .
  • the substrate 10 is made up of silicon or the like, and a semiconductor integrated circuit (LSI, not shown) is incorporated therein.
  • the aluminum electrodes (element electrodes) 20 are electrically connected to the semiconductor integrated circuit. In at least one of the aluminum electrodes (element electrodes) 20 , a capacitor 50 is formed.
  • FIG. 3A is an enlarged view of the capacitor 50 .
  • FIG. 3B illustrates a main section of the capacitor 50 illustrated in FIG. 3A further enlarged.
  • surfaces of the aluminum electrodes (element electrodes) 20 are roughened.
  • to roughen the surface is to increase a surface expansion ratio, and more specifically, a surface is defined as roughened when its surface expansion ration is 50-fold or more. Further, the present invention regards 50-fold to 120-fold surface expansion ratios as suitable, and a 100-fold surface expansion ratio or so as optimal.
  • the roughened surface of the aluminum electrode (element electrode) 20 has a complicated shape like branches of a tree and is in a so-called sponge state.
  • the oxide film 22 is an aluminum oxide film constituting the aluminum electrode (element electrode) 20 . More specifically, the oxide film 22 is formed such that the surface of the aluminum electrode (element electrode) 20 is roughened and then oxidized.
  • a conductive film (solid electrolyte) 24 is formed on the oxide film 22 .
  • a solid electrolyte, conductive polymer molecules or the like (for example, polypyrrole, polythiofuran, polyaniline) constitutes the conductive film (solid electrolyte) 24 according to the present preferred embodiment.
  • the aluminum electrode (element electrode) 20 , oxide film 22 and conductive film (solid electrolyte) 24 constitute the capacitor 50 . More specifically, the aluminum electrode (element electrode) 20 constitutes a lower electrode, the conductive film (solid electrolyte) 24 constitutes an upper electrode, and the oxide film 22 therebetween constitutes a dielectric member.
  • carbon pastes 26 are deposited on the conductive film (solid electrolyte) 24 , and Ni/Au plated electrodes (barrier metal) 28 are formed thereon.
  • a part of the aluminum electrodes (element electrodes) 20 is covered with a passivation film 30 formed on the substrate (semiconductor substrate) 10 .
  • the passivation film 30 is, for example, a film made up of nitride (SiN film or the like) or a polyimide film and protects the surface of the substrate (semiconductor substrate) 10 .
  • the substrate (semiconductor substrate) 10 is not necessarily a silicon substrate, and may be a substrate made up of other semiconductor materials (for example, SiC substrate, GaN substrate) or a substrate in which a semiconductor layer is formed on at least a surface, such as a SOI substrate.
  • the surface of the aluminum electrode (element electrodes) 20 is roughened, and the aluminum oxide film 22 is formed on the roughened surface, so that the capacitor 50 is formed.
  • the decoupling capacitor cab be placed at a position very close to the semiconductor chip 100 such as LSI. Accordingly, the L component (inductance element) can be cut substantially to zero.
  • the dielectric member (oxide film 22 ) constituting the capacitor 50 according to the present preferred embodiment is formed on the surface of the roughened surface of the aluminum electrode (element electrode) 20 , and the capacity of the capacitor can be thereby easily increased.
  • the capacitor 50 capable of effectively controlling the voltage drop of the semiconductor chip 100 can be realized.
  • the capacitor 50 provided with the aluminum electrode 20 thus constituted has a capacity of 0.1 ⁇ F (or more), which is a satisfactory value for a decoupling capacitor.
  • the capacitor 50 according to the present preferred embodiment is formed on the aluminum electrode (element electrode) 20 of the semiconductor chip 100 , the conventional disadvantage in a mounting area on the printed substrate can be avoided in comparison to the case wherein the capacitors are separately provided in the periphery of the semiconductor chip. More specifically, since the capacitor 50 is formed on the aluminum electrode (element electrode) 20 in the semiconductor chip 100 according to the present preferred embodiment, the region for the coupling capacitors 13 provided in the periphery of the semiconductor chip 12 in the example illustrated in FIG. 1 becomes unnecessary in the case where the semiconductor chip 100 according to the present preferred embodiment is mounted on the mounting substrate (printed substrate) to form the semiconductor mounting module.
  • the mounting substrate (printed substrate) on which the semiconductor chip 100 is mounted may be any of a rigid substrate, a flexible substrate and a rigid flexible substrate.
  • the substrate (semiconductor substrate) 10 is a silicon substrate having the thickness of 100 ⁇ m, and the thickness of the aluminum electrode (element electrode) 20 is 40 ⁇ m, and the dimensions thereof are vertically 0.1 mm ⁇ horizontally 0.1 mm.
  • the shape of the aluminum electrode (element electrode) 20 is not necessarily rectangular, and may be any of other shapes (for example, circular shape).
  • the conductive film (solid electrolyte) 24 is made of polypyrrole, and the carbon paste 26 has the thickness of 3 ⁇ m.
  • An example of the Ni/Au plated electrode (barrier metal) 28 is an Ni/Au plated layer.
  • FIGS. 4A-4D A process for producing the capacitor 50 is described referring to FIGS. 4A-4D , 5 A, 5 B, and 6 A- 6 C.
  • the semiconductor chip in which the aluminum electrode (element electrode) 20 is formed as the element electrode is prepared.
  • the aluminum electrode (element electrode) 20 is formed on the substrate (semiconductor substrate) 10 .
  • a part (outer peripheral portion) of the aluminum electrode (element electrode) 20 is covered with the passivation film 20 formed on the substrate (semiconductor substrate) 10 ; however, the center of the aluminum electrode (element electrode) 20 is exposed.
  • the semiconductor chip illustrated in this section is a semiconductor device in which the aluminum electrode (element electrode) 20 is formed on the substrate (semiconductor substrate) 10 .
  • a semiconductor package in which a bare chip is packaged (for example, chip size package (CSP)) may be used as the semiconductor chip, and the aluminum electrode 20 may be similarly formed in the aluminum electrode (element electrode) 20 of the semiconductor package.
  • CSP chip size package
  • a underlaying electrode 40 is formed on the substrate (semiconductor substrate) 10 or the passivation film 30 so as to cover the aluminum electrode (element electrode) 20 .
  • the underlaying electrode 40 serves as a power feeding layer in an anodizing process implemented later.
  • the underlaying electrode (power feeding layer) 40 is made of, for example, Cr/Cu.
  • the underlaying electrode (power feeding layer) 40 has the thickness of approximately 0.05-2 ⁇ m.
  • a photo resist 42 having a predetermined pattern is formed on the underlaying electrode (power feeding layer) 40 , and an opening 43 is formed in the photoresist 42 at a position similar to that of the aluminum electrode (element electrode) 20 .
  • the opening 43 is formed by means of the photolithography conventionally known.
  • an aluminum electrode (element electrode) 20 lower than the aluminum electrode 20 A may be made of other metal (for example, copper).
  • an alternate current is applied with the underlaying electrode (power feeding layer) 40 serving as the power feeding layer so that the underlaying electrode 40 is subjected to the electrolytic etching in an electrolytic solution in which hydrochloric acid is included as a main constituent in order to roughen a surface thereof.
  • hydrochloric acid is included as a main constituent in order to roughen a surface thereof.
  • a voltage is applied to the underlaying electrode (power feeding layer) 40 in a neutral electrolytic solution so that the aluminum electrode (upper electrode) 20 A is anodized.
  • the surface of the aluminum electrode (upper electrode) 20 A is further roughened, and the surface expansion ratio is increased to be approximately 50-fold to 120-fold as illustrated in FIG. 3B .
  • the oxide film 20 is further formed thereon.
  • the applied voltage is, for example, approximately 30-100 V.
  • the thickness of the oxide film is, for example, approximately 20-120 nm.
  • the conductive film (solid electrolyte) 24 is formed on the substrate (semiconductor substrate) 10 or the passivation film 30 so as to cover the aluminum electrode (upper electrode) 20 A on which the oxide film 22 is formed, as illustrated in FIG. 5B .
  • the conductive film (solid electrolyte) 24 which covers the roughened surface of the aluminum electrode (upper electrode) 20 A, can fill uneven portions in the roughened surface.
  • the conductive layers ( 20 A, 24 ) are formed with the oxide film 22 as the dielectric layer interposed therebetween. As a result, the capacitor 50 is formed.
  • the thickness of the conductive film (solid electrolyte) 24 is, for example, approximately 1-3 ⁇ m.
  • the carbon paste 26 is deposited on the conductive film (solid electrolyte) 24 which covers the aluminum electrode (upper electrode) 20 A.
  • an Ag paste 27 is further deposited on the carbon paste 26 .
  • the thickness of the carbon paste 26 is, for example, approximately 0.1-5 ⁇ m, and the thickness of the Ag paste 27 is, for example, approximately 3-15 ⁇ m.
  • the Ni/Au plated electrode (barrier metal) 28 is formed on the surface of the Ag paste 27 .
  • the semiconductor chip 100 in which the capacitor 50 is formed on the aluminum electrode 20 (upper electrode) 20 A can be obtained.
  • any unnecessary portions of the photoresist 42 and the underlaying electrode (power feeding layer) 40 are removed as illustrated in FIG. 6C . These portions can be removed such that the photoresist 42 is peeled off by means of an alkali solution and the unnecessary portion of the underlaying electrode (power feeding layer) 40 is etched by means of a conventional etching solution suitable for the material of the underlaying electrode (power feeding layer) 40 .
  • a part of the photoresist 42 (for example, a lower portion of the layers constituting the capacitor 50 ) may be left, or a new material (for example, resin) may be supplied after the photoresist 42 is removed in order to protect the capacitor 50 .
  • the aluminum electrode (upper electrode) 20 A is provided, and the capacitor 50 is formed thereon.
  • the aluminum electrode (element electrode) 20 on the substrate (semiconductor substrate) 10 may be anodized so that the capacitor 50 is formed.
  • the electrode is made of tantalum or niobium in place of the Al electrode, an oxide film of the used material may be used to form the capacitor.
  • the AI electrode is of more technical significance in view of manufacturability and manufacturing costs.
  • the capacitor 50 may be formed on the electrode of the interposer (electrodes of the semiconductor package including the interposer, or the electrodes of the semiconductor mounting module including the interposer (for example, multi-chip module)).
  • the decoupling capacitors can be easily provided even on a printed substrate 310 housed in an electronic device (for example, mobile communication device) 300 subject to very strict restrictions on mounting areas such as a mobile telephone as illustrated in FIG. 7 .
  • the capacitor 50 according to the present preferred embodiment which is formed on the aluminum electrode (element electrode) 20 of the semiconductor chip, can be provided in substantially zero distance, which effectively eliminates the influences of the L component.
  • the constitution of the capacitor 50 according to the present preferred embodiment can easily secure any capacity necessary for controlling the voltage drop of the LSI.
  • Examples of the mobile communication device are a mobile telephone, and PDA and a laptop computer in which a mounting area is strictly restricted. Further, the semiconductor chip 100 according to the present preferred embodiment is widely applied to other electronic devices such as a digital camera, a digital video camera, and a flat panel display.
  • a semiconductor chip comprising a capacitor capable of effectively controlling the voltage drop of an LSI can be provided.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
US12/377,076 2006-09-21 2007-08-24 Semiconductor chip, semiconductor mounting module, mobile communication device, and process for producing semiconductor chip Expired - Fee Related US7943518B2 (en)

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KR102460748B1 (ko) * 2017-09-21 2022-10-31 삼성전기주식회사 커패시터 부품
WO2023214491A1 (ja) * 2022-05-02 2023-11-09 株式会社村田製作所 電子部品及びその製造方法

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US20110180900A1 (en) 2011-07-28
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JP5094726B2 (ja) 2012-12-12
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CN101506965A (zh) 2009-08-12
CN101506965B (zh) 2012-05-09

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