CN101504681A - Evaluation method for decoupling capacitor on ASIC sheet based on chain circuit - Google Patents

Abstract

The invention discloses a method for estimating the decoupling capacitors on a chip of an ASIC based on a chain circuit, and belongs to the field of estimation of the decoupling capacitors in inhibition of mains voltage fluctuation. The method comprises: firstly, adopting Star-RCXT to extract parasitic parameters of the ASIC after wiring, and using Perl to analyze the SPF file format and included information for the modeling of the chain circuit; secondly, using an Euler formula to realize the equivalence of the capacitors, and compressing the circuit by a Y-delta conversion method; thirdly, solving the voltage and the current of various nodes of a compressor circuit, and restoring the solving of the chain circuit; and fourthly, adopting integral idea to obtain the number of decoupling capacitors required to be added according to the principle that the voltage fluctuation of the nodes cannot exceed 10 percent of the mains voltage. The method estimates the number of the decoupling capacitors on a chip required to be added between power ground wires, makes the amplitude of mains fluctuation not exceed 10 percent of the mains voltage, and effectively solves the problem of voltage drop of a power network.

Description

Based on the ASIC sheet of the link circuit evaluation method for decoupling capacitor that gets on

Technical field

The present invention relates to suppress a kind of ASIC sheet in mains fluctuations technical field evaluation method for decoupling capacitor that gets on based on link circuit.

Background technology

Studies show that, the power-supply fluctuation amplitude of power ground network can not surpass 10% of supply voltage, otherwise can cause that the transmission delay of data-signal and level are unpredictable, produced simultaneously simultaneous switching noise brings electromagnetic interference (EMI) to other signals, reduces the Electro Magnetic Compatibility of chip.

Decoupling capacitor can effectively address this problem on the sheet adding between power supply ground, when circuit overturns, can at first extract electric charge from contiguous decoupling capacitor rather than from power bus, after the circuit upset is finished, decoupling capacitor can slowly charge in electric power network again, therefore can suppress mains fluctuations, reduce simultaneous switching noise.So in concrete enforcement, need estimate the quantity of decoupling capacitor.

In July, 2003, the disclosed patent No. was that the patent " based on the method for the ic power network transients analysis and solution of equivalent electrical circuit " of 03104770.X has proposed a kind of dynamic electric voltage derivation algorithm based on link circuit, with the RLC link circuit is ASIC circuit network model, by circuit compression and rejuvenation solving circuit dynamic electric voltage.

In present VLSI circuit, adopt the method for standard cell placement mostly, therefore the shared power supply ground of a plurality of devices exist a large amount of RC link circuits.When the upset of circuit when power bus extracts certain electric current, can cause certain pressure drop to the electric power network bus, and this pressure drop can have influence on the circuit of shared this power bus in the chip, makes its supply voltage shakiness.

Summary of the invention

The present invention proposes a kind of ASIC sheet based on link circuit evaluation method for decoupling capacitor that gets in order effectively to suppress mains fluctuations.

A kind of ASIC sheet based on link circuit evaluation method for decoupling capacitor that gets on comprises the steps:

(1) link circuit model

According to the ASIC circuit characteristic, whole network is abstract to be a link circuit, and its major parameter information comprises: the annexation between the element node, the resistance value R between the node _i, node capacitor C _iAnd element equivalent current source e _i

(2) the SPF file extracts

Tool using Star-RCXT extracts the parasitic parameter file of wiring back circuit, and promptly the SPF file orders to be: StarXtract-clean../script/starrcxt.cmd;

(3) parameter of using the Perl language to extract in the SPF file is carried out the link circuit modeling

A. to the extraction of node relationships and resistance: according in the SPF file to the description of resistance information, adopt Perl to extract: to choose a resistance arbitrarily, its two end node is numbered, with arbitrary node is that starting point is searched the SPF file, judge whether to exist the continuous new node of node therewith: if exist, repeat above-mentioned search procedure then to this new node numbering, and with it as starting point; If do not exist, then another node of initial resistance is searched according to same process, obtain the structural information of whole link circuit;

Resistance and nodal information deletion with extracting in this process repeat whole search procedure, can extract other electrical chains;

B. to the extraction of node capacitor: according in the SPF file to the description of capacitance information, extract all row with Perl with " C " beginning, be that key word mates with the nodename, search the corresponding electric capacity of this node;

C. current source equivalence: the usable floor area current method, calculate current source according to the standard block area:

$I_{\mathrm{total}}=\frac{P_{\mathrm{total}}}{\mathrm{Vdd}},$ $I_{\mathrm{cell}}=I_{\mathrm{total}}\×\frac{A_{\mathrm{cell}}}{A_{\mathrm{total}}}$

Wherein: P _Total-chip total power consumption, A _Total-gate cell area summation, A _Cell-certain gate cell area, I _Total-chip average current, I _Cell-gate cell consumed current, i.e. current source size;

Quote total power consumption and all the gate cell area sums that module consumes by report_power and report_area order when comprehensive using Design Compiler to net table, a certain gate cell area can be found in the java standard library file, promptly sets up the link circuit model by above method;

(4) electric power network node dynamic electric voltage is found the solution

A. capacitor equivalent: at k+1 constantly with Euler's formula with capacitance equation $I_{c,k+1}=C\×\frac{{\mathrm{dV}}_{c,k+1}}{\mathrm{dt}}$ Conversion obtains:

$I_{c,k+1}=\frac{2C}{h}{V}_{c,k+1}-(\frac{2C}{h}{V}_{c,k}+I_{c,k})$

This capacitive form and the original current source of link circuit are merged, and obtaining branch road is resistance

With current source

With form;

B. the Y-Δ conversion of equivalent electrical circuit: each nodes X of link circuit and two coupled branch road resistance R _aAnd R _bAnd branch road resistance R _cWith branch current I _cRegard a Y type circuit as, utilization Y-Δ equivalent transformation obtains:

$R_{\mathrm{ab}}=\frac{R_a{R}_b+R_a{R}_c+R_b{R}_c}{R_c},$ $R_{\mathrm{ac}}=\frac{R_a{R}_b+R_a{R}_c+R_b{R}_c}{R_b},$ $R_{\mathrm{b\; c}}=\frac{R_a{R}_b+R_a{R}_c+R_b{R}_c}{R_a}$

In like manner obtain: $I_{\mathrm{ac}}=\frac{R_c{I}_c}{R_{\mathrm{ac}}}-\frac{R_a{I}_a}{R_{\mathrm{ac}}},$ $I_{\mathrm{bc}}=\frac{R_c{I}_c}{R_{\mathrm{bc}}}-\frac{R_b{I}_b}{R_{\mathrm{bc}}}$

Circuit after the conversion and primary circuit like terms are merged, and iteration carries out circuit compression, can get first node of compressor circuit and the resistance of n node branch road With

Current source

With

And two internodal resistance of compressor circuit

C. compressor circuit is found the solution: make V _{1, k+1}≈ Vdd, obtain the node voltage of compressor circuit according to Kirchhoff's law:

$V_{n,k+1}={\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="A200910030395E00092.png,A200910030395E00111.png"\; state="\{\{state\}\}">R</figure-callout>}}_{1,n}^{\mathrm{equiv}}(\frac{{\mathrm{<figure-callout\; id="1"\; label="V"\; filenames="A200910030395E00092.png,A200910030395E00111.png"\; state="\{\{state\}\}">V</figure-callout>}}_{1,k+1}}{{\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="A200910030395E00092.png,A200910030395E00111.png"\; state="\{\{state\}\}">R</figure-callout>}}_1^{\mathrm{equiv}}}+I_{1,k+1}^{\mathrm{equiv}})+{\mathrm{<figure-callout\; id="1"\; label="V"\; filenames="A200910030395E00092.png,A200910030395E00111.png"\; state="\{\{state\}\}">V</figure-callout>}}_{1,k+1},$ ${\mathrm{<figure-callout\; id="1"\; label="E"\; filenames="A200910030395E00092.png,A200910030395E00111.png"\; state="\{\{state\}\}">E</figure-callout>}}_{1,k+1}=\frac{V_{n,k+1}-{\mathrm{<figure-callout\; id="1"\; label="V"\; filenames="A200910030395E00092.png,A200910030395E00111.png"\; state="\{\{state\}\}">V</figure-callout>}}_{1,k+1}}{{\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="A200910030395E00092.png,A200910030395E00111.png"\; state="\{\{state\}\}">R</figure-callout>}}_{1,n}^{\mathrm{equiv}}}-I_{1,k+1}^{\mathrm{equiv}}-\frac{{\mathrm{<figure-callout\; id="1"\; label="V"\; filenames="A200910030395E00092.png,A200910030395E00111.png"\; state="\{\{state\}\}">V</figure-callout>}}_{1,k+1}}{{\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="A200910030395E00092.png,A200910030395E00111.png"\; state="\{\{state\}\}">R</figure-callout>}}_1^{\mathrm{equiv}}}$

D. the link circuit node recovers: because E _{1, k+1}In compression process, do not change, utilize the circuit solving result after compressing to carry out iteration, thereby obtain the voltage and the electric current of all intermediate nodes:

V _2，k+1＝V _1，k+1+R ₁×E _1，k+1，

${\mathrm{<figure-callout\; id="2"\; label="E"\; filenames="A200910030395E00092.png,A200910030395E00121.png"\; state="\{\{state\}\}">E</figure-callout>}}_{2,k+1}={\mathrm{<figure-callout\; id="1"\; label="E"\; filenames="A200910030395E00092.png,A200910030395E00111.png"\; state="\{\{state\}\}">E</figure-callout>}}_{1,k+1}+\frac{{\mathrm{<figure-callout\; id="2"\; label="V"\; filenames="A200910030395E00092.png,A200910030395E00121.png"\; state="\{\{state\}\}">V</figure-callout>}}_{2,k+1}}{{\mathrm{<figure-callout\; id="2"\; label="r"\; filenames="A200910030395E00092.png,A200910030395E00121.png"\; state="\{\{state\}\}">r</figure-callout>}}_2}+{\mathrm{<figure-callout\; id="2"\; label="ec"\; filenames="A200910030395E00092.png,A200910030395E00121.png"\; state="\{\{state\}\}">ec</figure-callout>}}_{2,k+1},$

Can solve all nodes at k+1 node voltage V constantly _{J, k+1}With node branch current E _{J, k+1}, 2≤j≤n-1 wherein;

(5) decoupling capacitor on the sheet of estimation insertion

Make V _Th=90%Vdd according to the node voltage situation of change, supposes at t ₁-t ₂Time period i node instantaneous voltage v (i) is lower than V _Th, obtain the quantity of electric charge of required compensation:

$Q=\underset{t_1}{\overset{t_2}{\&Integral;}}[V_{\mathrm{th}}-v\left(i\right)]\mathrm{dt}$

According to Q=CVdd, be converted into electric capacity and be: $C=\frac{\underset{t_1}{\overset{t_2}{\&Integral;}}[V_{\mathrm{th}}-v\left(i\right)]\mathrm{dt}}{\mathrm{Vdd}};$

Wherein: C-capacitor's capacity, h-simulation step-length, V _{C, k+1}And I _{C, k+1}Be respectively k+1 electric capacity both end voltage and the electric current that flows through electric capacity, V constantly _{C, k}And I _{C, k}Be respectively k electric capacity both end voltage and the electric current that flows through electric capacity, V constantly _{I, k}And I _{I, k}Be respectively the k voltage and current of node i constantly, i is a node serial number, is natural number, e _{I, k+1}The equivalent current source of-gate cell, R _Ab, R _AcAnd R _BcBe equivalent Δ type circuit a, three nodes of b, c resistance between in twos, R _a, R _bAnd R _cBe the branch road resistance of equivalent Y type circuit node, I _a, I _bAnd I _cFor flowing through the branch current of equivalent Y type circuit node, I _Ab, I _BcAnd I _AcFor flowing through equivalent Δ type circuit a, two nodes of b, c branch current between in twos, V _{1, k+1}And V _{N, k+1}Be respectively the node voltage of the 1st node of compressor circuit and n node, E _{1, k+1}And E _{N, k+1}Be respectively the branch current that flows through the 1st node of compressor circuit and n node, n is the compressor circuit node serial number, is natural number, R ₁-the 1 node-resistance, ec _{I, k+1}-capacitor equivalent is replaced the branch current source of back link circuit, V _Th-node need insert the voltage threshold of decoupling capacitor, Vdd-supply voltage, the quantity of electric charge of the required compensation of Q-node.

The inventive method has designed a kind of compression and restoration methods based on link circuit, with the rlc circuit model simplification is RC circuit model solution node dynamic electric voltage, the decoupling capacitor quantity that estimation should add in circuit, mains fluctuations have effectively been suppressed, and make the mains fluctuations amplitude of power ground network be no more than 10% of supply voltage, the pressure drop that when reducing the circuit upset electric power network bus is caused, thereby the electromagnetic interference (EMI) of minimizing chip internal.

Description of drawings

Fig. 1 is a method flow diagram of the present invention.

Fig. 2 is the link circuit equivalent structure figure in the ASIC circuit among the present invention, standard block equivalent current source-representation among the figure.

Fig. 3 is a chain type circuit modeling process flow diagram among the present invention.

Fig. 4 is the circuit diagram that node is described in the SPF file among the present invention.

Fig. 5 uses the Perl language to SPF file processing process flow diagram among the present invention.

Fig. 6 is a capacitor equivalent principle schematic in the link circuit among the present invention.

Fig. 7 is the link circuit structural representation after the distortion among the present invention.

Fig. 8 is that the link circuit after will being out of shape among the present invention carries out the compression process synoptic diagram.

Fig. 9 is the link circuit structural drawing after the compression among the present invention.

Figure 10 is according to certain node change in voltage situation synoptic diagram in an iteration cycle among the present invention.

Embodiment

Be the inventive method basic procedure as shown in Figure 1, describe implementation step below in detail.

A kind of ASIC sheet based on link circuit evaluation method for decoupling capacitor that gets on comprises the steps:

(1) RC link circuit model in the ASIC circuit as shown in Figure 2

According to the ASIC circuit characteristic, whole network is abstract to be a link circuit, and its major parameter information comprises: the annexation between the element node, the resistance value R between the node _i, node capacitor C _iAnd element equivalent current source e _i, the charge and discharge process of constant current source analog chip internal standard unit wherein;

(2) the SPF file extracts

Tool using Star-RCXT extracts the parasitic parameter file of wiring back circuit, it is the SPF file, order is: StarXtract-clean../script/starrcxt.cmd, wherein specified the Milkyway form of input circuit and extracted requirement in the starrcxt.cmd script.Fig. 4 is the abstract circuit representation that comes out of the SPF file layout that extracts according to Star-RCXT and content;

(3) parameter of using the Perl language to extract in the SPF file is carried out the link circuit modeling, modeling flow process as shown in Figure 3: a. is to the extraction of node relationships and resistance: being described as resistance information in the SPF file: R168 fiforeg/Reg2/U7:VDDfiforeg/Reg30/out_reg_3_:VDD3.80094;

Wherein fiforeg/Reg2/U7:VDD and fiforeg/Reg30/out_reg_3_:VDD are the power supply node titles, 3.80094 be the resistance between the node, unit is Ω, can obtain resistance between annexation between the link circuit node and node according to its description.

As shown in Figure 5, adopt Perl to extract: to choose a resistance arbitrarily, its two end node is numbered, with arbitrary node is that starting point is searched the SPF file, judge whether to exist the continuous new node of node therewith: if exist, repeat above-mentioned search procedure then to this new node numbering, and with it as starting point; If do not exist, then another node of initial resistance is searched according to same process, obtain the structural information of whole link circuit;

Resistance and nodal information deletion with extracting in this process repeat whole search procedure, can extract other electrical chains;

B. to the extraction of node capacitor: being described as capacitance information in the SPF file:

Cg27KESblock/PE15/multiplierl/U10:VDD 0 4.05819e-16 extracts all row with " C " beginning with Perl, is that key word mates with the nodename, searches the corresponding electric capacity of this node;

C. current source equivalence: the usable floor area current method, calculate current source according to the standard block area:

$I_{\mathrm{total}}=\frac{P_{\mathrm{total}}}{\mathrm{Vdd}},$ $I_{\mathrm{cell}}=I_{\mathrm{total}}\&times;\frac{A_{\mathrm{cell}}}{A_{\mathrm{total}}}$

Wherein: P _Total-chip total power consumption, A _Total-gate cell area summation, A _Cell-certain gate cell area, I _Total-chip average current, I _Cell-gate cell consumed current, i.e. current source size;

Quote total power consumption and all the gate cell area sums that module consumes by report power and report_area order when comprehensive using Design Compiler to net table, a certain gate cell area can be found in the java standard library file, promptly sets up the link circuit model by above method;

(4) electric power network node dynamic electric voltage is found the solution

After modelling is good, need be out of shape,, need carry out equivalent transformation so that clear its function because electric capacity is a time varying element to circuit;

A. as shown in Figure 6, capacitor equivalent conversion: at k+1 constantly with Euler's formula with capacitance equation $I_{c,k+1}=C\&times;\frac{{\mathrm{dV}}_{c,k+1}}{\mathrm{dt}}$ Conversion obtains:

$I_{c,k+1}=\frac{2C}{h}{V}_{c,k+1}-(\frac{2C}{h}{V}_{c,k}+I_{c,k})$

This capacitive form and the original current source of link circuit are merged, and obtaining branch road is resistance

With current source

With form;

Equivalent link circuit as shown in Figure 7 is to be out of shape the arrangement of replacement back by the electric capacity in the link circuit to obtain the current source and the resistance form that have become when wherein branch road has comprised, branch current source after capacitor equivalent is replaced ${\mathrm{ec}}_{i,k+1}=e_{i,k+1}-(\frac{2C}{h}{V}_{i,k}+I_{i,k}),$ Branch impedance $r_i=\frac{h}{2C};$

Be the process that adopts the conversion of Y-Δ to compress in the circuit after the distortion as shown in Figure 8, describe in detail below:

B. the Y-Δ conversion of equivalent electrical circuit: each nodes X of link circuit and two coupled branch road resistance R _aAnd R _bAnd branch road resistance R _cWith branch current I _cRegard a Y type circuit as, utilization Y-Δ equivalent transformation, the parameter after the conversion is:

$R_{\mathrm{ab}}=\frac{R_a{R}_b+R_a{R}_c+R_b{R}_c}{R_c},$ $R_{\mathrm{ac}}=\frac{R_a{R}_b+R_a{R}_c+R_b{R}_c}{R_b},$ $R_{\mathrm{b\; c}}=\frac{R_a{R}_b+R_a{R}_c+R_b{R}_c}{R_a}$

Thereby have: $E_a=\frac{V_b-V_a}{R_{\mathrm{ab}}}-\frac{V_a}{R_{\mathrm{ac}}}-\frac{R_a{I}_c}{R_{\mathrm{ac}}},$ $E_b=\frac{V_a-V_b}{R_{\mathrm{ab}}}-\frac{V_b}{R_{\mathrm{bc}}}-\frac{R_c{I}_c}{R_{\mathrm{bc}}}$

In like manner obtain: $I_{\mathrm{ac}}=\frac{R_c{I}_c}{R_{\mathrm{ac}}}-\frac{R_a{I}_a}{R_{\mathrm{ac}}},$ $I_{\mathrm{bc}}=\frac{R_c{I}_c}{R_{\mathrm{bc}}}-\frac{R_b{I}_b}{R_{\mathrm{bc}}}$

Circuit after the conversion and primary circuit like terms are merged, and iteration carries out circuit compression, can get first node of compressor circuit and the resistance of n node branch road

With

Current source

With

And two internodal resistance of compressor circuit

Just obtain the link circuit after the compression as shown in Figure 9;

C. compressor circuit is found the solution: make V _{1, k+1}≈ Vdd, obtain the node voltage of compressor circuit according to Kirchhoff's law:

$V_{n,k+1}={\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="A200910030395E00092.png,A200910030395E00111.png"\; state="\{\{state\}\}">R</figure-callout>}}_{1,n}^{\mathrm{equiv}}(\frac{{\mathrm{<figure-callout\; id="1"\; label="V"\; filenames="A200910030395E00092.png,A200910030395E00111.png"\; state="\{\{state\}\}">V</figure-callout>}}_{1,k+1}}{{\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="A200910030395E00092.png,A200910030395E00111.png"\; state="\{\{state\}\}">R</figure-callout>}}_1^{\mathrm{equiv}}}+I_{1,k+1}^{\mathrm{equiv}})+{\mathrm{<figure-callout\; id="1"\; label="V"\; filenames="A200910030395E00092.png,A200910030395E00111.png"\; state="\{\{state\}\}">V</figure-callout>}}_{1,k+1},$ ${\mathrm{<figure-callout\; id="1"\; label="E"\; filenames="A200910030395E00092.png,A200910030395E00111.png"\; state="\{\{state\}\}">E</figure-callout>}}_{1,k+1}=\frac{V_{n,k+1}-{\mathrm{<figure-callout\; id="1"\; label="V"\; filenames="A200910030395E00092.png,A200910030395E00111.png"\; state="\{\{state\}\}">V</figure-callout>}}_{1,k+1}}{{\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="A200910030395E00092.png,A200910030395E00111.png"\; state="\{\{state\}\}">R</figure-callout>}}_{1,n}^{\mathrm{equiv}}}-{\mathrm{<figure-callout\; id="1"\; label="I"\; filenames="A200910030395E00092.png,A200910030395E00111.png"\; state="\{\{state\}\}">I</figure-callout>}}_{1,k+1}^{\mathrm{equiv}}-\frac{{\mathrm{<figure-callout\; id="1"\; label="V"\; filenames="A200910030395E00092.png,A200910030395E00111.png"\; state="\{\{state\}\}">V</figure-callout>}}_{1,k+1}}{{\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="A200910030395E00092.png,A200910030395E00111.png"\; state="\{\{state\}\}">R</figure-callout>}}_1^{\mathrm{equiv}}}$

D. the link circuit node recovers: comparison diagram 7 and Fig. 9 circuit structure, because E _{1, k+1}In compression process, do not change, utilize the circuit solving result after compressing to carry out iteration, thereby obtain the voltage and the electric current of all intermediate nodes:

V _2，k+1＝V _1，k+1+R ₁×E _1，k+1， ${\mathrm{<figure-callout\; id="2"\; label="E"\; filenames="A200910030395E00092.png,A200910030395E00121.png"\; state="\{\{state\}\}">E</figure-callout>}}_{2,k+1}={\mathrm{<figure-callout\; id="1"\; label="E"\; filenames="A200910030395E00092.png,A200910030395E00111.png"\; state="\{\{state\}\}">E</figure-callout>}}_{1,k+1}+\frac{{\mathrm{<figure-callout\; id="2"\; label="V"\; filenames="A200910030395E00092.png,A200910030395E00121.png"\; state="\{\{state\}\}">V</figure-callout>}}_{2,k+1}}{{\mathrm{<figure-callout\; id="2"\; label="r"\; filenames="A200910030395E00092.png,A200910030395E00121.png"\; state="\{\{state\}\}">r</figure-callout>}}_2}+{\mathrm{<figure-callout\; id="2"\; label="ec"\; filenames="A200910030395E00092.png,A200910030395E00121.png"\; state="\{\{state\}\}">ec</figure-callout>}}_{2,k+1},$

Can solve all nodes at k+1 node voltage V constantly _{J, k+1}With node branch current E _{J, k+1}, 2≤j≤n-1 wherein;

(5) decoupling capacitor on the sheet of estimation insertion

Be the node voltage situation of change of certain node in an iteration cycle as shown in figure 10, the principle that can not surpass supply voltage 10% according to the voltage fluctuation amplitude,, be lower than this threshold value and show and to come electric charge is regulated by decoupling capacitor as the voltage threshold that inserts decoupling capacitor with this;

Make V _Th=90%Vdd according to the node voltage situation of change, supposes at t ₁-t ₂Time period i node instantaneous voltage v (i) is lower than V _Th, adopt integration thought to obtain the quantity of electric charge of required compensation:

$Q=\underset{t_1}{\overset{t_2}{\&Integral;}}[V_{\mathrm{th}}-v\left(i\right)]\mathrm{dt}$

According to Q=C.Vdd, be converted into electric capacity and promptly obtain the electric capacity that this node need insert and be: $C=\frac{\underset{t_1}{\overset{t_2}{\&Integral;}}[V_{\mathrm{th}}-v\left(i\right)]\mathrm{dt}}{\mathrm{Vdd}};$

Wherein: C-capacitor's capacity, h-simulation step-length, V _{C, k+1}And I _{C, k+1}Be respectively k+1 electric capacity both end voltage and the electric current that flows through electric capacity, V constantly _{C, k}And I _{C, k}Be respectively k electric capacity both end voltage and the electric current that flows through electric capacity, V constantly _{I, k}And I _{I, k}Be respectively the k voltage and current of node i constantly, i is a node serial number, is natural number, r _ie _{I, k+1}The equivalent current source of-gate cell, R _Ab, R _AcAnd R _BcBe equivalent Δ type circuit a, three nodes of b, c resistance between in twos, R _a, R _bAnd R _cBe the branch road resistance of equivalent Y type circuit node, V _aAnd V _bBe the resistance at equivalent node a and b two ends, E _aAnd E _bFor flowing out the electric current of equivalent node a and b, I _a, I _bAnd I _cFor flowing through the branch current of equivalent Y type circuit node, I _Ab, I _BcAnd I _AcFor flowing through equivalent Δ type circuit a, three nodes of b, c branch current between in twos, V _{1, k+1}And V _{N, k+1}Be respectively the node voltage of the 1st node of compressor circuit and n node, E _{1, k+1}And E _{N, k+1}Be respectively the branch current that flows through the 1st node of compressor circuit and n node, n is the compressor circuit node serial number, is natural number, R ₁-the 1 node-resistance, ec _{I, k+1}-capacitor equivalent is replaced the branch current source of back link circuit, V _Th-node need insert the voltage threshold of decoupling capacitor, Vdd-supply voltage, the quantity of electric charge of the required compensation of Q-node.

Claims (1)

1, a kind of ASIC sheet based on link circuit evaluation method for decoupling capacitor that gets on is characterized in that comprising the steps: (1) link circuit model

According to the ASIC circuit characteristic, whole network is abstract to be a link circuit, and its major parameter information comprises: the annexation between the element node, the resistance value R between the node _i, node capacitor C _iAnd element equivalent current source e _i

(2) the SPF file extracts

Tool using Star-RCXT extracts the parasitic parameter file of wiring back circuit, and promptly the SPF file orders to be: StarXtract-clean../script/starrcxt.cmd;

(3) parameter of using the Perl language to extract in the SPF file is carried out the link circuit modeling

A. to the extraction of node relationships and resistance: according in the SPF file to the description of resistance information, adopt Perl to extract: to choose a resistance arbitrarily, its two end node is numbered, with arbitrary node is that starting point is searched the SPF file, judge whether to exist the continuous new node of node therewith: if exist, repeat above-mentioned search procedure then to this new node numbering, and with it as starting point; If do not exist, then another node of initial resistance is searched according to same process, obtain the structural information of whole link circuit;

Resistance and nodal information deletion with extracting in this process repeat whole search procedure, can extract other electrical chains;

B. to the extraction of node capacitor: according in the SPF file to the description of capacitance information, extract all row with Pcrl with " C " beginning, be that key word mates with the nodename, search the corresponding electric capacity of this node;

C. current source equivalence: the usable floor area current method, calculate current source according to the standard block area:

$I_{\mathrm{total}}=\frac{P_{\mathrm{total}}}{\mathrm{Vdd}},$ $I_{\mathrm{cell}}=I_{\mathrm{total}}\&times;\frac{A_{\mathrm{cell}}}{A_{\mathrm{total}}}$

Wherein: P _Total-chip total power consumption, A _Total-gate cell area summation, A _Cell-certain gate cell area, I _Total-chip average current, I _Cell-gate cell consumed current, i.e. current source size;

Quote total power consumption and all the gate cell area sums that module consumes by report_power and report_area order when comprehensive using Design Compiler to net table, a certain gate cell area can be found in the java standard library file, promptly sets up the link circuit model by above method;

(4) electric power network node dynamic electric voltage is found the solution

A. capacitor equivalent: at k+1 constantly with Euler's formula with capacitance equation $I_{c,k+1}=C\&times;\frac{{\mathrm{dV}}_{c,k+1}}{\mathrm{dt}}$ Conversion obtains:

$I_{c,k+1}=\frac{2C}{h}{V}_{c,k+1}-(\frac{2C}{h}{V}_{c,k}+I_{c,k})$

This capacitive form and the original current source of link circuit are merged, and obtaining branch road is resistance

With current source

With form;

B. the Y-Δ conversion of equivalent electrical circuit: each nodes X of link circuit and two coupled branch road resistance R _aAnd R _bAnd branch road resistance R _cWith branch current I _cRegard a Y type circuit as, utilization Y-Δ equivalent transformation obtains:

$R_{\mathrm{ab}}=\frac{R_a{R}_b+R_a{R}_c+R_b{R}_c}{R_c},$ $R_{\mathrm{ac}}=\frac{R_a{R}_b+R_a{R}_c+R_b{R}_c}{R_b},$ $R_{\mathrm{b\; c}}=\frac{R_a{R}_b+R_a{R}_c+R_b{R}_c}{R_a}$

In like manner obtain: $I_{\mathrm{ac}}=\frac{R_c{I}_c}{R_{\mathrm{ac}}}-\frac{R_a{I}_a}{R_{\mathrm{ac}}},$ $I_{\mathrm{bc}}=\frac{R_c{I}_c}{R_{\mathrm{bc}}}-\frac{R_b{I}_b}{R_{\mathrm{bc}}}$

Circuit after the conversion and primary circuit like terms are merged, and iteration carries out circuit compression, can get first node of compressor circuit and the resistance of n node branch road

With

Current source

With

And two internodal resistance of compressor circuit

C. compressor circuit is found the solution: make V _{1, k+1}≈ Vdd, obtain the node voltage of compressor circuit according to Kirchhoff's law:

$V_{n,k+1}=R_{1,n}^{\mathrm{equiv}}(\frac{V_{1,k+1}}{R_1^{\mathrm{equiv}}}+I_{1,k+1}^{\mathrm{equiv}})+V_{1,k+1},$ $E_{1,k+1}=\frac{V_{n,k+1}-V_{1,k+1}}{R_{1,n}^{\mathrm{equiv}}}-I_{1,k+1}^{\mathrm{equiv}}-\frac{V_{1,k+1}}{R_1^{\mathrm{equiv}}}$

D. the link circuit node recovers: because E _{1, k+1}In compression process, do not change, utilize the circuit solving result after compressing to carry out iteration, thereby obtain the voltage and the electric current of all intermediate nodes:

V _2，k+1＝V _1，k+1+R ₁×E _1，k+1， $E_{2,k+1}=E_{1,k+1}+\frac{V_{2,k+1}}{r_2}+{\mathrm{ec}}_{2,k+1},\&CenterDot;\&CenterDot;\&CenterDot;\&CenterDot;\&CenterDot;\&CenterDot;$

Can solve all nodes at k+1 node voltage V constantly _{J, k+1}With node branch current E _{J, k+1}, 2≤j≤n-1 wherein;

(5) decoupling capacitor on the sheet of estimation insertion

Make V _Th=90%Vdd according to the node voltage situation of change, supposes at t ₁-t ₂Time period i node instantaneous voltage v (i) is lower than V _Th, obtain the quantity of electric charge of required compensation:

$Q=\underset{t_1}{\overset{t_2}{\&Integral;}}[V_{\mathrm{th}}-v\left(i\right)]\mathrm{dt}$

According to Q=CVdd, be converted into electric capacity and be: $C=\frac{\underset{t_1}{\overset{t_2}{\&Integral;}}[V_{\mathrm{th}}-v\left(i\right)]\mathrm{dt}}{\mathrm{Vdd}};$

Wherein: C-capacitor's capacity, h-simulation step-length, V _{C, k+1}And I _{C, k+1}Be respectively k+1 electric capacity both end voltage and the electric current that flows through electric capacity, V constantly _{C, k}And I _{C, k}Be respectively k electric capacity both end voltage and the electric current that flows through electric capacity, V constantly _{I, k}And I _{I, k}Be respectively the k voltage and current of node i constantly, i is a node serial number, is natural number, e _{I, k+1}The equivalent current source of-gate cell, R _Ab, R _AcAnd R _BcBe equivalent Δ type circuit a, three nodes of b, c resistance between in twos, R _a, R _bAnd R _cBe the branch road resistance of equivalent Y type circuit node, I _a, I _bAnd I _cFor flowing through the branch current of equivalent Y type circuit node, I _Ab, I _BcAnd I _AcFor flowing through equivalent Δ type circuit a, three nodes of b, c branch current between in twos, V _{1, k+1}And V _{N, k+1}Be respectively the node voltage of the 1st node of compressor circuit and n node, E _{1, k+1}And E _{N, k+1}Be respectively the branch current that flows through the 1st node of compressor circuit and n node, n is the compressor circuit node serial number, is natural number, R ₁-the 1 node-resistance, ec _{I, k+1}-capacitor equivalent is replaced the branch current source of back link circuit, V _Th-node need insert the voltage threshold of decoupling capacitor, Vdd-supply voltage, the quantity of electric charge of the required compensation of Q-node.

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