CN101494144A - Structure of nanometer line cold-cathode electron source array with grid and method for producing the same as well as application of flat panel display - Google Patents
Structure of nanometer line cold-cathode electron source array with grid and method for producing the same as well as application of flat panel display Download PDFInfo
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Abstract
The invention discloses a structure of a nano-wire cold cathode electron source array with a grid electrode, and a production method and an application thereof in flat panel display. The electron source array structure comprises a substrate, a cathode electrode strip and a grid electrode strip which are mutually crossly arranged and produced on the substrate, an insulating layer between a cathode and the grid electrode, and a nano-wire cold cathode array produced on the cathode electrode strip. The electron source array structure is produced by adopting a method combining a film micro-processing technology and a self-assembly growth technology. In the method, a nano-wire cold cathode is made by adopting a direct oxidation method without catalyst. In addition, a covering layer is produced on the cathode for protecting a source material required for the growth of nano-wires and limiting the growth of the nano-wires in a region close to the grid electrode. The electron source array structure adopts the nano-wires as the cold cathode, has simple production method and technology as well as high controllability, and can be applied to panel display devices of field emission.
Description
Technical field
The present invention relates to structure of field emitting electronic source array and preparation method thereof, more specifically, relate to a kind of metal oxide nano-wire that adopts as structure of the electron source array of cold-cathode material and preparation method thereof.
Background technology
Cold-cathode electron source array is widely used at aspects such as Field Emission Display, x-ray source and microwave devices.Up to the present, the cold-cathode electron source array of research mainly adopts little pointed cone, diamond thin and quasi-one-dimensional nanometer material cold cathodes such as diamond like carbon film or carbon nano-tube.
Adopt the cold-cathode electron source of little pointed cone to reach higher level at aspect of performance, (S.Itoh et al, Journal of the SID 15/12,1057-1064 (2007)) appears in existing procucts at present.But its manufacture craft requires high-resolution photoetching, processing and fabricating condition harshness, and the cost costliness is difficult to realize large-area manufacturing.Though diamond thin and diamond like carbon film have lower emission threshold field, but the inhomogeneities of this class cold cathode emission makes this class material not reach practical requirement yet.
In recent years, it is found that carbon nano-tube, nano wire and other novel quasi-one-dimensional nanometer material have excellent field emission characteristic.Because accurate one-dimensional materials such as carbon nano-tube can adopt the nanometer cold cathode of accurate one-dimensional materials such as carbon nano-tube might realize the high performance cold-cathode electron source array of low-cost production with the method preparation of self-organizing growth.Realize the making of cold-cathode electron source array, key is the vacuum micro-nano electron source array of the grid of wanting to have made integrated and nanometer cold cathode, promptly to be made in the gated device structure quasi-one-dimensional nanometer cold cathode is integrated, and make that device can be than under the low driving voltage, realize addressable, and the ground work of reliable long-life.The existing at present some kinds of reports of realizing the carbon nanotube electron source array making method of band grid.In these methods, carbon nano-tube adopts silk screen printing or chemical vapour deposition technique preparation respectively.Korea S Samsung company reported that several employings can print the carbon nano-tube cold-cathode electron source array of the band grid that carbon nano-tube makes, and adopt this electron source to produce field emission display model machine (W.B.Choi, et al, Applied Physics Letters, 75 (20), 3129 (1999); N.S.Lee et al, Diamond and Related Materials, 10,265 (2001)).Although this method realizes the making of the electron source array of large-size easily, adopt silk screen printing to be difficult to realize the making of high-resolution device.Simultaneously, printed form carbon nano-tube cold cathode needs to introduce complicated aftertreatment technology in aspects such as emission uniformity and stability existing problems.The Oak Ridge National Laboratory of the Cambridge University of Britain, the U.S. and motorola inc etc. have reported that then making carbon nano-tube with the method for thermal chemical vapor deposition is band gate electron source array structure (the G.Pirio et al of cold cathode, Nanotechnology 13,1 (2002); M.A.Guilorn et al, Applied Physics.Letters 81,3660 (2002); JeanDijon et al, Journal of the SID 12/4,373-378 (2004); B.F.Coll et al, Journal of the SID 14/5,477 (2006)).Make in the carbon nano-tube method of chemical vapour deposition (CVD) above-mentioned, need catalyst and the higher growth temperature (550～600 ℃) of needs, the carbon nano tube growth process also needs to use expensive carbon-source gas.
Newfound in recent years nanometer line cold-cathode, but the characteristics of low-temperature epitaxy and superior electronic emission performance had.At present, the nanometer line cold-cathode electron source that also has only indivedual reports to realize grid integrated is made (J.C.She et al, AppliedPhysics Letters, 88 (1), 013112 (2006)).The key that realizes the nanometer line cold-cathode electron source of band grid is to locate the device architecture that is fit to nanometer line cold-cathode and with the manufacture method that integrates of nanometer line cold-cathode and gated device structure.If realize above-mentioned electron source array, need satisfy all procedures especially and be lower than the requirement that realizes under 650 ℃ of conditions, so that use glass substrate in the large scale scope.The invention provides that a kind of preparation technology is simple, the device architecture of the nanometer line cold-cathode electron source array that can on glass substrate, realize and preparation method thereof.This kind electron source array can be applicable to have broad application prospects in the Field Emission Display equal vacuum microelectronic component.
Summary of the invention
The invention provides a kind of nanometer line cold-cathode with grid electron source array structure and preparation method thereof and in the application of flat panel display.
Electron source array structure of the present invention comprises substrate 1, is produced on the cathode electrode bar 2 and the gate electrode bar 4 of the mutual cross arrangement on the substrate 1, the insulating barrier 3 between negative electrode and the grid, and be produced on nanometer line cold-cathode array 7 on the cathode electrode bar.In said structure, grid can be positioned at negative electrode below (following grid), top (going up grid) or parallel with it (flat grate); Also can adopt down grid simultaneously, go up grid or grid structure.
The manufacture method of the electron source array of the nanometer line cold-cathode of band grid of the present invention comprises the method for top-down film micro fabrication and the combination of self-assembled growth technology.When grid was above negative electrode, nanometer line cold-cathode electron source array was made according to the following steps:
(1) clean substrate 1;
(2) on substrate, make cathode electrode bar 2;
(3) on cathode electrode bar 2, make insulating barrier 3;
(4) on insulating barrier, make gate electrode bar 4;
(5) etching insulating barrier exposes cathode electrode bar 2 at the crossover location of gate electrode bar 4 and cathode electrode bar 2;
(6) make transition layer film 5 and growth source film 6 arrays successively on cathode electrode bar 2, transition layer film 5 is used to improve the adhesiveness of growth source film 6, and growth source film 6 arrays are used for the growth of nanometer line cold-cathode;
(7) adopt direct oxidation method to make nanometer line cold-cathode 7 from the growth source film growth.
When grid below negative electrode or when parallel, only need do corresponding adjustment to the order of above-mentioned steps (2)-(5).
Photoetching is adopted in the making of each layer film in the electron source array, and vacuum coating is peeled off and technology such as etching.Wherein, photoetching can be adopted ultraviolet or electron beam lithography, and vacuum coating technology adopts general film plating process, as electron beam evaporation, sputter, chemical vapour deposition (CVD) etc.; Lithographic technique adopts general film etching method, as methods such as wet etching, reactive ion etchings.
The nanometer cold cathode adopts the direct heat oxidizing process that need not catalyst.The structure that is manufactured with transition layer film and growth source membrane array directly is heated to a certain design temperature (200 ℃～650 ℃), and (30 minutes～12 hours) can produce nanometer line cold-cathode being incubated a period of time under the oxygen containing atmosphere under this temperature.
The transition layer film material of preparation nanometer line cold-cathode can be one or more in chromium, aluminium, titanium, tungsten, molybdenum or the niobium.The growth source thin-film material is copper, iron, zinc, tungsten, molybdenum, chromium, titanium or nickel.By direct oxidation, can generate cupric oxide, iron oxide, zinc oxide, tungsten oxide, molybdenum oxide, chromium oxide, titanium oxide or nickel oxide nano line.
Because grid is the strongest for the cathodic control effect near grid; in order to limit nanowire growth in fringe region near grid; on the growth source thin layer, can make cover layer 9; it is not oxidized that this cover layer plays protection growth source film simultaneously, thereby make the growth at the nano wire in unlapped zone that more raw materials be arranged.
In structure of above-mentioned nanometer line cold-cathode electron source array and preparation method thereof, cathode electrode bar and gate electrode bar are made up of the multiple layer metal film, this multiple layer metal film is used to improve the conductivity of electrode, and the metallic film of the superiors can be used for removing the residual sacrifice layer of etching.The material of film is chromium, aluminium, titanium, tungsten, molybdenum or niobium etc.
For the job stability and the life-span of improving electron source, must improve the reliability that insulate between grid and the negative electrode.The present invention introduces outstanding or recessed insulation step 8 between negative electrode and grid, be used to improve the insulation characterisitic between grid and the negative electrode.Simultaneously, insulating barrier can be made up of the multi-layer insulation film.The multilayer insulation layer film can be made up of silicon dioxide, silicon nitride or aluminium oxide etc., and its preparation method is a vacuum coating method, comprises methods such as electron beam evaporation method and plasma enhanced chemical vapor deposition.
The structure of nanometer line cold-cathode electron source of the present invention and manufacture method have the advantage that technology is simple, controllability is high.When nanometer line cold-cathode electron source array of the present invention was worked, whole electron source was in the vacuum environment.When between certain delegation's grid and a certain row negative electrode, applying voltage, the nanometer line cold-cathode of relevant position will be under the effect of grid voltage emitting electrons.Electron source array structure of the present invention can adopt glass as baseplate material, can realize the making of large scale electron source array.This kind electron source has significant application value on display of field-emitting flat panel equal vacuum microelectronic component.
Description of drawings
Fig. 1 is the electron source array structure schematic diagram of the cold cathode nano wire of band grid.
(a) the gate electrode bar is produced on the cathode electrode bar; (b) the gate electrode bar is produced under the cathode electrode bar; (c) gate electrode is parallel to the cathode electrode bar simultaneously and is positioned under the cathode electrode bar.(among the figure, 1: substrate; 2: the cathode electrode bar; 3: insulating barrier; 4: the gate electrode bar; 5: transition layer film; 6: the growth source film; 7: nanometer line cold-cathode.Below respectively scheme identical.)
Fig. 2 is the electron source array structure schematic diagram of the cold cathode nano wire of the insulation step 8 of adding projection between gate electrode bar and nanometer line cold-cathode.(a)-(c) distinguish three kinds of structures in the corresponding diagram 1.(among the figure, 8: the insulation step.Below respectively scheme identical.)
Fig. 3 is a kind of structural representation of introducing cover layer 9 on growth source film 6 surfaces.(a) introduce cover layer at the growth source film surface, before the grow nanowire.(b) after the growth source film surface is introduced cover layer, after the direct oxidation grow nanowire.(among the figure, 9: cover layer.Below respectively scheme identical.)
Fig. 4 is that the used tectal shape of difform nanometer line cold-cathode is given an example.(a) square; (b) circle.
Fig. 5 is that another kind is introduced tectal structural representation at the growth source film surface.(a) introduce cover layer at the growth source film surface, before the grow nanowire.(b) after the growth source film surface is introduced cover layer, after the direct oxidation grow nanowire.
Fig. 6 is a kind of electron source array structure schematic diagram of introducing tectal cold cathode nano wire shown in Figure 3 on growth source film 6 surfaces.(a)-(c) distinguish three kinds of structures in the corresponding diagram 1.
Fig. 7 is that the employing multiple layer metal film shown in Fig. 1 (a) is that electrode film, multi-layer insulation film are the electron source array making flow chart of insulating barrier.
Fig. 8 is the making flow chart that has the nano wire electron source array of insulating barrier step between cloudy grid.
Fig. 9 is a making flow chart of introducing the nano wire electron source array of cathode coating.
Figure 10 is a making flow chart of introducing the nano wire electron source array of insulating barrier step between cathode coating and cloudy grid simultaneously.
Figure 11 utilizes the structural upright schematic diagram of the nanometer line cold-cathode arrayed applications of the structure fabrication shown in Fig. 1 (a) in Field Emission Display.(among the figure, 10: phosphor powder layer; The 11:ITO film; 12: anode substrate)
Figure 12 is that the employing cupric oxide nano line of actual fabrication is Electronic Speculum (SEM) the photograph figure of the electron source array of cold cathode.
Figure 13 is that to adopt the cupric oxide nano line be Showing Picture and anode current-gate voltage curve of the Field Emission Display antetype device made of the electron source array of cold cathode.(a) device displayed map under the different grid voltages.(b) anode current-grid voltage characteristic curve.
Figure 14 adopts 3.5 inches cupric oxide nano lines of the full encapsulation cold-cathode field emission display profile of making of the present invention and the photo of character display and figure thereof.
Embodiment
In order more clearly to provide the process of above-mentioned electron source array structure and preparation method thereof, the present invention is described in further detail below in conjunction with accompanying drawing.
Fig. 1 has provided the structural representation of the nanometer line cold-cathode electron source array of band grid.As shown in Figure 1, the basic structure of this electron source array comprises substrate 1, is produced on the cathode electrode bar 2 and the insulating barrier 3 between gate electrode bar 4, negative electrode and the grid of the mutual cross arrangement on the substrate 1 and is produced on nanometer line cold-cathode array 7 on the cathode electrode bar 2.
In said structure, grid can be positioned at negative electrode below (following grid), top (going up grid) or parallel with it (flat grate); Also can adopt down grid simultaneously, go up grid or grid structure.Gate electrode bar 4 is produced on the cathode electrode bar 2 among Fig. 1 (a); Gate electrode bar 4 is produced under the cathode electrode bar 2 among Fig. 1 (b); Gate electrode 4 is parallel to cathode electrode bar 2 simultaneously and is positioned under the cathode electrode bar 2 among Fig. 1 (c).
Fig. 2 is the electron source array structure schematic diagram of the nanometer line cold-cathode of the insulation step 8 of adding projection between gate electrode bar 4 and nanometer line cold-cathode 7.(a)-(c) distinguish three kinds of structures in the corresponding diagram 1.In these three kinds of structures, introduced the insulating barrier step 8 of projection at cathode electrode bar 2 and gate electrode bar 4, be used to improve the insulation characterisitic between grid and the negative electrode, reduce the electric leakage between grid and the negative electrode, improve the reliability of device work and the power consumption of reduction device.The material of this insulating barrier step can adopt aluminium oxide, silicon dioxide and silicon nitride or other insulating material.Its thickness is identical with gate insulator or less than the gate insulator layer thickness.This insulating barrier step also can be made into recessed shape, can play the effect that improves the insulation characterisitic between grid and the negative electrode equally.
Fig. 3 is a kind of structural representation of introducing cover layer 9 on growth source film 6 surfaces.Fig. 3 (a) has shown that the material of cover layer 9 can be used metal, semiconductor or insulator at growth source film 6 surface introducing cover layers 9.It is used to limit the growth district of nanometer line cold-cathode 7, makes that nanometer line cold-cathode 7 can only be in the part growth near gate electrode bar 4.In such cases, cover layer 9 films are positioned at the central authorities of negative electrode growth source film 6.According to the shape of grid and negative electrode and the relative position between negative electrode and the grid thereof, coverlay film 9 can have different shapes.Fig. 4 (a) and (b) provided being shaped as of negative electrode two kinds of shapes of cover layer when square and circular respectively for example.During concrete enforcement, the shape of negative electrode and cover layer shape and relative position thereof will be not limited to Fig. 4 for two examples.Fig. 3 (b) has shown through after the direct oxidation grow nanowire, the schematic diagram after growth source film 6 superficial growths under the cover layer 9 go out nano wire.As can be seen from the figure, after introducing cover layer 9, can more effectively realize edge-emission, and compare with the nanometer line cold-cathode of intectate limiting growth, can avoid since the shielding action between the nanometer line cold-cathode make grid to the nano wire control action of centre part less than the caused non-uniformity of emission of edge-emission.
Fig. 5 is the another kind of structural representation of introducing cover layer 9 on growth source film 6 surfaces.(a) be grow nanowire schematic diagram before.(b) be direct oxidation grow nanowire schematic diagram afterwards.In this structure, negative electrode is only exposing on one side, and the another side cap rock that is covered fully covers.
Above-mentioned cover layer can adopt in the nanometer line cold-cathode electron source of different structure.Fig. 6 (a)-(c) has provided three kinds of structures respectively, all introduces cover layer 9 shown in Figure 3 on growth source film 6 surfaces.
Can also introduce insulation step and cathode coating simultaneously at the nanometer line cold-cathode electron source array of said structure, thereby improve the insulation characterisitic between the grid negative electrode simultaneously and limit nano wire in marginal growth near grid.
The preparation of each electrode and insulating barrier figure mainly adopts micro fabrications such as photoetching, etching, vacuum coating to realize in the above-mentioned nano wire electron source array structure.The nanometer cold cathode then adopts the direct heat oxidizing process that need not catalyst to make.Fig. 7, Fig. 8, Fig. 9 and Figure 10 provide the manufacturing process of several structures of introducing among the present invention.
Fig. 7 is that the employing multiple layer metal film shown in Fig. 1 (a) is that electrode film, multi-layer insulation film are the nano wire electron source array making flow chart of insulating barrier.At first on substrate 1, make cathode electrode bar 2 (shown in Fig. 7 (a)) with figure.Follow depositing insulating layer film 3 (shown in Fig. 7 (b)) on cathode electrode.Insulating layer of thin-film 3 is made up of multi-layer insulation films such as silicon dioxide, silicon nitride or aluminium oxide.Insulation film can adopt general method for manufacturing thin film, prepares as methods such as chemical vapour deposition (CVD), magnetron sputtering, electron beam evaporations.Then on insulating layer of thin-film 3, make the gate electrode bar 4 (as Fig. 7 (c) shown in) vertical with cathode electrode bar 2 directions.Afterwards insulating layer of thin-film 3 is carried out etching, form the insulating barrier hole and expose cathode electrode bar 7 (shown in Fig. 7 (d)).The etching insulating layer of thin-film can adopt general film etching method, as methods such as wet etching, reactive ion etchings.The surface can be adopted the superiors metallic film corrosion of the method for wet etching with the multiple layer metal film, thereby realize with round-about way residue being cleaned if there is etch residue after the etching.On the specific region, deposit transition layer film 5 and growth source film 6 (shown in Fig. 7 (e)) then.Transition layer film and growth source film can adopt general method for manufacturing thin film, comprise method preparations such as sputter, electron beam evaporation.At last the substrate of making is heated to 200～650 ℃ under oxygen containing atmosphere, and is incubated 30 minutes～12 hours, cooling at last just can make and adopt the electron source array (as Fig. 7 (f) shown in) of nano-wire array 7 as cold-cathode material.
Fig. 8 has provided the schematic flow sheet that a kind of making has the nano wire electron source array of insulating barrier step.Adopting the multiple layer metal film in its structure is electrode film, and multi-layer insulation film is an insulating barrier.At first on substrate 1, make cathode electrode bar 2 (shown in Fig. 8 (a)) with figure.Follow depositing insulating layer film 3 (shown in Fig. 8 (b)) on cathode electrode.Insulating layer of thin-film 3 is made up of multi-layer insulation films such as silicon dioxide, silicon nitride or aluminium oxide.Insulation film can adopt general method for manufacturing thin film, prepares as methods such as chemical vapour deposition (CVD), sputter, electron beam evaporations.Then on insulating layer of thin-film 3, make the gate electrode bar 4 (as Fig. 8 (c) shown in) vertical with cathode electrode bar 2 directions.Afterwards insulating layer of thin-film 3 is carried out etching, form the insulating barrier hole and expose cathode electrode bar 2 (shown in Fig. 8 (d)).The etching insulating layer of thin-film can adopt general film etching method, as methods such as wet etching, reactive ion etchings.The surface can be adopted the superiors metallic film corrosion of the method for wet etching with the multiple layer metal film, thereby realize with round-about way residue being cleaned if there is etch residue after the etching.Follow on the cathode electrode bar 2 that exposes in the insulating barrier hole, localization plates insulation step 8 (shown in Fig. 8 (e)).Insulation step 8 can adopt low temperature thin film technology of preparing (as electron beam evaporation, technology such as magnetron sputterings) and lift-off technology process combined method to make.On the specific region, deposit transition layer film 5 and growth source film 6 (shown in Fig. 8 (f)) then.Transition layer film and growth source film can adopt general method for manufacturing thin film, comprise method preparations such as sputter, electron beam evaporation.At last the substrate of making is heated to 200～650 ℃ under oxygen containing atmosphere, and is incubated 30 minutes～12 hours, cooling at last just can make and adopt the electron source array (as Fig. 8 (g) shown in) of nano-wire array 7 as cold-cathode material.
Fig. 9 is that a kind of making has a cathode coating electron source array and makes flow chart.Adopting the multiple layer metal film in its structure is electrode film, and multi-layer insulation film is an insulating barrier.At first on substrate 1, make cathode electrode bar 2 (shown in Fig. 9 (a)) with figure.Follow depositing insulating layer film 3 (shown in Fig. 9 (b)) on cathode electrode.Insulating layer of thin-film 3 is made up of multi-layer insulation films such as silicon dioxide, silicon nitride or aluminium oxide.Insulation film can adopt general method for manufacturing thin film, prepares as methods such as chemical vapour deposition (CVD), magnetron sputtering, electron beam evaporations.Then on insulating layer of thin-film 3, make the gate electrode bar 4 (as Fig. 9 (c) shown in) vertical with cathode electrode bar 2 directions.Afterwards insulating layer of thin-film 3 is carried out etching, form the insulating barrier hole and expose cathode electrode bar 2 (shown in Fig. 9 (d)).The etching insulating layer of thin-film can adopt general film etching method, as methods such as wet etching, reactive ion etchings.The surface can be adopted the superiors metallic film corrosion of the method for wet etching with the multiple layer metal film, thereby realize with round-about way residue being cleaned if there is etch residue after the etching.Then on the specific region, deposit transition layer film 5 and growth source film 6 (shown in Fig. 9 (e)).Transition layer film 5 and growth source film 6 can adopt general method for manufacturing thin film, comprise method preparations such as sputter, electron beam evaporation.Then on the growth source film 6, localization plates cover layer 9 (shown in Fig. 9 (f)).Cover layer 9 can adopt general film preparing technology (as electron beam evaporation, technology such as magnetron sputterings) and lift-off technology process combined method to make.At last the substrate of making is heated to 200～650 ℃ under oxygen containing atmosphere, and is incubated 30 minutes～12 hours, cooling at last just can make and adopt the electron source array (as Fig. 9 (g) shown in) of nano-wire array 7 as cold-cathode material.
Figure 10 has provided the schematic flow sheet that a kind of making has the nano wire electron source array of cathode coating and insulating barrier step simultaneously.Adopting the multiple layer metal film in its structure is electrode film, and multi-layer insulation film is an insulating barrier, and cover layer adopts the insulating material identical with the insulating barrier step.At first on substrate 1, make cathode electrode bar 2 (shown in Figure 10 (a)) with figure.Follow depositing insulating layer film 3 (shown in Figure 10 (b)) on cathode electrode.Insulating layer of thin-film 3 is made up of multi-layer insulation films such as silicon dioxide, silicon nitride or aluminium oxide.Insulation film can adopt general method for manufacturing thin film, prepares as methods such as chemical vapour deposition (CVD), magnetron sputtering, electron beam evaporations.Then on insulating layer of thin-film 3, make the gate electrode bar 4 (as Figure 10 (c) shown in) vertical with cathode electrode bar 2 directions.Afterwards insulating layer of thin-film 3 is carried out etching, form the insulating barrier hole and expose cathode electrode bar 2 (shown in Figure 10 (d)).The etching insulating layer of thin-film can adopt general film etching method, as methods such as wet etching, reactive ion etchings.The surface can be adopted the superiors metallic film corrosion of the method for wet etching with the multiple layer metal film, thereby realize with round-about way residue being cleaned if there is etch residue after the etching.Then on the specific region, deposit transition layer film 5 and growth source film 6 (shown in Figure 10 (e)).Transition layer film 5 and growth source film 6 can adopt general method for manufacturing thin film, comprise method preparations such as sputter, electron beam evaporation.Then cathode electrode bar 2 places of exposing in growth source film 6 and insulating barrier hole respectively localization plate cover layer 9 and insulation step 8 (shown in Figure 10 (f)).Cover layer 9 and insulation step 8 can adopt general film preparing technology (as electron beam evaporation, technology such as magnetron sputterings) and lift-off technology process combined method to make.At last the substrate of making is heated to 200～650 ℃ under oxygen containing atmosphere, and is incubated 30 minutes～12 hours, cooling at last just can make and adopt the electron source array (as Figure 10 (g) shown in) of nano-wire array 7 as cold-cathode material.
The making of other device architecture can be carried out according to the basic step of above four examples among the present invention.It needs to be noted, the actual fabrication process be not limited only to above-mentioned for example, can also adopt other similar micro-processing method.
Figure 11 has provided the perspective view that nanometer line cold-cathode electron source array that the present invention makes is applied to Field Emission Display.The basic structure of this display device is made up of electron source array substrate and glass anode substrate.The insulating layer of thin-film 3 of preparation on cathode electrode bar 2 arranged, the gate electrode bar 4 on the insulating layer of thin-film 3, and the nano-wire array on cathode electrode bar 27 on the electron source array substrate.The phosphor powder layer 10 that the strip of preparation on ito thin film 11 arranged on the anode substrate 12.Use the solid insulating material insulation between electron source array electrode substrate and the anode substrate.Can adopt binding agent, for example glass powder with low melting point is fixed two substrates and seal.Be the spacing between the control two substrates, can make the supporter of insulation by the method for silk screen printing in the relevant position on substrate, or insulator is installed as supporter.
Embodiment
Present embodiment has provided and has adopted the manufacturing process of cupric oxide nano line as the electron source array of cold-cathode material.Concrete manufacturing process steps is referring to accompanying drawing 7.At first glass substrate usefulness acetone, ethanol and deionized water are distinguished ultrasonic cleaning 20 minutes, dry up with nitrogen, again oven dry.On glass substrate, adopt magnetically controlled DC sputtering vacuum coating technology and stripping technology to prepare the cathode electrode bar.The cathode electrode bar is made up of chromium film and aluminium film, and its thickness is respectively 120nm and 100nm.The method that using plasma strengthens vapour deposition prepares silicon nitride and the compound insulating layer of thin-film of silicon dioxide, and its gross thickness is 1.5 μ m.Adopt magnetically controlled DC sputtering vacuum coating technology and stripping technology to prepare the gate electrode bar.The gate electrode bar is made up of chromium film and aluminium film, and its thickness is respectively 400nm and 100nm.Adopt reactive ion etching technology etching insulating layer of thin-film, thereby form the insulating barrier hole.Adopt magnetically controlled DC sputtering vacuum coating technology and stripping technology to prepare transition layer film and growth source film, the material of transition layer film and growth source film is respectively chromium film and copper film, and its thickness is 100nm and 1.0 μ m respectively.At last glass substrate is put into to tube furnace and carried out oxidation.Earlier be increased to 400 ℃, be incubated 3 hours down at 400 ℃ then from room temperature, last natural cooling, above-mentioned whole oxidizing process is carried out under air.
Electron source array to preparation carries out scanning electron microscopy (SEM) observation.Accompanying drawing 12 is Electronic Speculum pictures of the observed electron source array of scanning electron microscopy (SEM), can find that the cupric oxide nano line is integrated in the grid structure, formed cupric oxide nano line electron source array, wherein the diameter of cupric oxide nano line is about 80～100nm, highly is 0.3～3.0 μ m.
The electron source array substrate and the anode phosphor screen substrate in batch that complete are dressed up the Field Emission Display antetype device, keep insulation with ceramic insulating material between the two substrates.After the device assembling finished, entire device inside is under the vacuum state to be tested.At first on anode electrode, apply voltage, between certain delegation's grid and a certain row negative electrode or whole cathode columns, apply voltage then, electronics will emit from cupric oxide nano line cold cathode under the effect of anode voltage and grid voltage, after quickening in a vacuum, bombard anode light, thereby realize the demonstration of a certain pixel or certain delegation's pixel.Showing Picture of the Field Emission Display that accompanying drawing 13 (a) is assembled into for the cupric oxide nano line electron source array of made of the present invention.The corresponding work condition is: the anode working electric field is fixed on 5.2MV/m, and the grid operating voltage is respectively 40V, 80V, 100V, 120V.Figure 13 (b) is the relation curve of anode collected current and grid voltage.From curve as can be known, when anode electric field was fixed on 5.2MV/m, when grid voltage was increased to 120 V from 0V, the electric current that anode is collected was increased to 480nA from 170nA.Figure 14 (a) is 3.5 inches cupric oxide nano line cold-cathode field emission display profile photos that adopt the full encapsulation of making of the present invention.Figure 14 (b) is the photo of this device character display and graphical effect.Above experimental result has proved that the nano wire electron source array of made is hopeful to be applied to the field emission display of high-resolution, low-voltage.
Claims (14)
1. structure with the nanometer line cold-cathode electron source array of grid, this structure comprises:
(1) substrate;
(2) be produced on the cathode electrode bar and the gate electrode bar of the mutual cross arrangement on this substrate;
(3) insulating barrier between negative electrode and the grid;
(4) be produced on nanometer line cold-cathode on the cathode electrode bar.
2. according to the manufacture method of the described nanometer line cold-cathode electron source array of claim 1, its making step is as follows:
(1) clean substrate;
(2) on substrate, make the cathode electrode bar;
(3) on the cathode electrode bar, make insulating barrier;
(4) on insulating barrier, make the gate electrode bar;
(5) etching insulating barrier exposes the cathode electrode bar at the crossover location of grid and cathode electrode bar;
(6) make transition layer film and growth source membrane array respectively on the cathode electrode bar, transition layer film is used to improve the adhesiveness of growth source film, and the growth source membrane array is used for the growth of nanometer line cold-cathode;
(7) adopt direct oxidation method to make nanometer line cold-cathode from the growth source film growth.
3. according to the manufacture method of the described nanometer line cold-cathode electron source array of claim 2, it is characterized in that: the step of described direct oxidation method is:
(1) structure that will be manufactured with transition layer film and growth source membrane array is heated to 200 ℃～650 ℃;
(2) under oxygen containing atmosphere, be incubated 30 minutes～12 hours;
(3) cooling.
4. according to the structure of the described a kind of nanometer line cold-cathode electron source array with grid of claim 1-3, it is characterized in that: described substrate is glass, pottery or silicon chip etc.
5. according to the structure of the described a kind of nanometer line cold-cathode electron source array with grid of claim 1-3, it is characterized in that: in the described structure, projection or recessed insulation step be can between gate electrode bar and nanometer line cold-cathode, make, the insulation characterisitic between grid and the negative electrode and the stability and the life-span of device work are used to improve.
6. according to the structure of the described a kind of nanometer line cold-cathode electron source array with grid of claim 1-3, it is characterized in that: in the described structure, can on the thin layer of source, introduce cover layer, be used to limit the growth district of nanometer line cold-cathode, and guarantee the supply of the source material that nanowire growth is required.Described tectal material is metal, semiconductor or insulation film.
7. according to structure of the described nanometer line cold-cathode electron source array of claim 1-3 and preparation method thereof, it is characterized in that: cathode electrode bar and gate electrode bar are made up of multiple layer metal films such as chromium, aluminium, titanium, tungsten, molybdenum or niobiums, this multiple layer metal film is used to improve the conductivity of electrode, and the metallic film of the superiors can be used for removing the residual sacrifice layer of etching.
8. according to structure of the described nanometer line cold-cathode electron source array of claim 1-3 and preparation method thereof, it is characterized in that: insulating barrier is made up of the multi-layer insulation film, and this multilayer insulation layer film is used to improve the insulating properties of insulating barrier.
9. according to claim 1, the structure of 8 described nanometer line cold-cathode electron source arrays, it is characterized in that: described multilayer insulation layer film is made up of silicon dioxide, silicon nitride or aluminium oxide etc., its preparation method is a vacuum coating method, comprises electron beam evaporation method and plasma enhanced chemical vapor deposition method.
10. according to the manufacture method of the described nanometer line cold-cathode electron source array of claim 1-3, wherein do not use any catalyst in the manufacturing process of nanometer line cold-cathode.
11., it is characterized in that in the manufacture method of source array according to the described nanometer line cold-cathode electricity of claim 1-3: described transition layer film material is one or more in chromium, titanium, aluminium, molybdenum or the niobium.
12. the manufacture method according to the described nanometer line cold-cathode electron source array of claim 1-3 is characterized in that: described growth source thin-film material is copper, iron, zinc, tungsten, molybdenum, chromium, titanium or nickel.
13. the manufacture method according to the described nanometer line cold-cathode electron source array of claim 1-3 is characterized in that: described nano-material is cupric oxide, iron oxide, zinc oxide, tungsten oxide, molybdenum oxide, chromium oxide, titanium oxide or nickel oxide.
14. the application of nanometer line cold-cathode electron source array on display of field-emitting flat panel according to the described method making of claim 1-14.
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