CN101490807B - 在半导体装置形成期间使用的方法 - Google Patents

在半导体装置形成期间使用的方法 Download PDF

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CN101490807B
CN101490807B CN200780026005.XA CN200780026005A CN101490807B CN 101490807 B CN101490807 B CN 101490807B CN 200780026005 A CN200780026005 A CN 200780026005A CN 101490807 B CN101490807 B CN 101490807B
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周葆所
米尔扎菲尔·K·阿巴切夫
阿尔达万·尼鲁曼德
保罗·A·摩根
孟双
约瑟夫·格里利
布里安·J·科帕
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North Star Franchise Group Co ltd
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Micron Technology Inc
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Abstract

一种用于对层进行图案化的方法增加使用一系列自对准间隔物在初始图案化层上方形成的特征的密度。提供待蚀刻层，然后在所述待蚀刻层上方形成例如使用光学光刻形成的初始牺牲图案化层。视实施例而定，可修整所述图案化层，然后形成并蚀刻一系列间隔物层。间隔物层的数目及其目标尺寸取决于特征密度的所期望增加。还描述一种处理过程中的半导体装置及电子***。

Description

在半导体装置形成期间使用的方法
技术领域
本发明涉及半导体制造领域，且更特定来说涉及一种用于通过使用各种保形层及选择性蚀刻借助光刻掩模在起始特征密度下形成特征并形成是所述第一密度的n倍的最终密度的方法，其中n为大于1的整数。 
背景技术
在半导体装置形成期间，通常在半导体晶片上方形成许多特征，例如，字线、数字线、触点及其它特征。半导体装置工程师的一个目标是在既定区域中形成尽可能多的这些特征以增大产率、减少制造成本并使装置小型化。在半导体晶片上形成这些结构通常需要使用光刻。光学光刻是前沿晶片处理中使用最多的方法，其包括从照明源(照明器)投射既定波长(通常为248纳米(nm)或193纳米)的相干光，透过具有表示待形成的特征的铬图案的石英光掩模或光罩，并使所述图案成像到涂布有光致抗蚀剂的晶片上。所述光以化学方式改变光致抗蚀剂并使得暴露的光致抗蚀剂(在使用正性抗蚀剂的情况下)或未暴露的光致抗蚀剂(在使用负性抗蚀剂的情况下)能够使用显影剂被漂洗掉。 
随着特征大小减少，持续地测试光学光刻的限度。可通过工艺推进、增强的光刻方法(称为分辨率增强技术)及改善的设备及材料来做出对特征密度的改善。 
如图1-6中所示的一种此工艺推进使用掩模，所述掩模具有既定间距(即，从一个重复特征的开始到下一特征的开始的既定距离)的重复特征连同各种层的形成以及选择性蚀刻以使得从光刻掩模形成的特征的密度加倍。图1描绘半导体晶片衬底组合件10，其包括：半导体晶片、待蚀刻层12(例如氮化硅层)、支撑层14(例如使用化学气相沉积(CVD)或旋涂技术由碳形成)及经图案化遮蔽层16(例如使用光学光刻工艺形成的光致抗蚀剂层及使用光学光刻及蚀刻工艺形成的硬掩模层)。经图案化遮蔽层16可在光刻工艺允许的特征大小限度下形成，且包括相距既定距离18而形成的三个个别特征(三个周期/间距)。 
在形成图1的结构之后，通过将掩模16用作图案来执行对支撑层14的蚀刻。此蚀刻通常是一种选择性地针对待蚀刻层12蚀刻支撑层14的各向异性干蚀刻(即，其移除支撑层14而几乎不或不蚀刻待蚀刻层12)。在蚀刻支撑层14之后，移除经图案化遮蔽层16并形成保形硬掩模层20(例如二氧化硅)以形成图2的结构。 
 随后，执行对图2结构的间隔物蚀刻以形成具有来自所述硬掩模层沿支撑层14侧壁的间隔物20′的图3的结构。随后，蚀刻支撑层14以形成图4的结构。 
接下来，将从硬掩模层形成的间隔物20′用作图案以蚀刻待蚀刻层12，从而形成图5的结构。最后，选择性地针对待蚀刻层12蚀刻间隔物20′以形成图6的结构。 
图1-6的工艺具有以下优点：使用光学光刻来形成具有相距既定距离18的三个特征的遮蔽层16，而图6中所描绘的完成后结构具有相距原始距离18的六个特征12(六个周期/间距)。因此，在不需要额外光刻掩模的情况下使所述距离内特征的数目近似加倍。 
增大特征密度的各种技术描述于泰勒A劳瑞(Tyler A.Lowrey)等人所著的美国专利第5,328,810号及塞瑞狄罗伯茨(Ceredig Roberts)等人所著的美国专利第5,254,218号中，此两个专利均受让于美光科技有限公司(Micron Technology，Inc)且如同整体阐述并入本文中。 
一种用于使用具有第一间距的光学光刻掩模形成半导体装置并形成具有等于1/n的第二间距的特征的方法可是需要的，其中n为大于1的整数且不将特征大小的减小或间隔限定为使用光刻可达到的一半。 
发明内容
附图说明
图1-6为描绘用于加倍掩模特征(例如使用光刻法形成的掩模特征)数目的常规工艺的截面图； 
图7-15为描绘使既定区域中特征的数目增大四倍的本发明方法的实施例的处理过程中的半导体装置的截面图； 
图16-22为描绘使既定区域中特征的数目增大六倍的本发明方法的实施例的截面图； 
图23-31是描绘使既定区域中特征的数目增大三倍的本发明方法的变化形式的另一实施例的截面图； 
图32-38是描绘使既定区域中特征的数目增大五倍的本发明另一实施例的截面图； 
图39是可使用用本发明实施例形成的装置制造的各种组件的等角描绘；且 
图40是本发明用以形成具有存储装置晶体管阵列的存储器装置的一部分的例示性使用的方块图。 
应强调，本文中的图式可能未按精确比例绘制，而仅为示意性表示。所述图式并不意在描绘具体参数、材料、特定用途或本发明的结构细节，其可通过所属技术领域的技术人员检验本文中的信息来确定。 
具体实施方式
术语“晶片”应理解为基于半导体的材料，其中包含硅、绝缘体上硅(SOI)或蓝宝石上硅(SOS)技术、经掺杂及未经掺杂的半导体、由基底半导体基础支撑的硅外延层及其它半导体结构。此外，当在以下说明中提及“晶片”时，可能已利用先前的工艺步骤在所述基底半导体结构或基础中或其上方形成区或结。另外，当在以下说明中提及“衬底组合件”时，所述衬底组合件可包含晶片，视特定的处理阶段而定，所述晶片具有包含电介质及导体以及形成于其上方的特征(例如，晶体管)的层。另外，所述半导体不需要基于硅，但可基于硅-锗、绝缘体上硅、蓝宝石上硅、锗或砷化镓及其它。此外，在本文中的论述及权利要求书中，针对两个层所使用的术语“在......上(on)”，“一个在另一个上”，意指层之间的至少某些接触，而“在......上方(over)”意指各层紧密接近，但可能具有一个或一个以上额外中间层，使得接触成为可能但不是必需的。本文所使用的“在......上(on)”或“在......上方(over)”均不暗示任何方向性。术语“约(about)”指示所列出的值可稍微改变，只要所述改变不会导致所讨论的工艺或结构不顺应本发明。“间隔物”指示作为保形层而形成于不均匀形貌上方的层(通常为电介质)，然后对所述层进行各向异性蚀刻以移除所述层的水平部分并留下所述层较高的竖直部分。 
本发明的各种实施例使用可使间距减小的交替间隔物沉积(ASD)来实现可变临界尺寸(CD)减小比率。所述间距减小工艺可实现小于先前形成的光刻掩模所界定的CD的CD。本文中描述的各种工艺实施例包括使用第一类型间隔物材料，所述第一类型间隔物材料被用作牺牲层并以对用于图案化下伏层的第二间隔物材料的高选择性将其移除。视修整比率而定，可实现间隔物沉积数目、每一沉积的厚度、是先前光刻法所界定的原始值的1/n的CD，其中n为大于1的奇数或偶数整体。换句话说，所述工艺将图案密度增加了n倍。特定来说，通过将对应间隔物蚀刻所遵循的ASD工艺重复m次，可实现是起始CD的1/2m或1/(2m-1)的CD，此可视执行两种方法中的哪一种而定。用于形成半导体装置的本发明方法的第一实施例描绘于图7-14中。此工艺实施例形成减小到其原始值的1/2m的CD。值m可通过合计在ASD工艺期间形成的间隔物层的数目来确定。 
图7描绘牺牲光刻图案70，其包括(例如)具有截面侧壁的上覆于待蚀刻层72的分段区段的光致抗蚀剂。待蚀刻层72可以是半导体晶片、包括上覆于半导体晶片或晶片区段的一个或一个以上层的半导体晶片衬底组合件或待经受图案化蚀刻的一个或一个以上其它层。在此实施例中，光刻特征70在每一特征70的宽度及特征70之间的间距14均大约相等的光刻限度下形成。层70可包括不同于光致抗蚀剂的经图案化材料。 
在形成图7的结构之后，使用各向同性蚀刻对光致抗蚀剂执行修整以形成图8的结构。当将光致抗蚀剂用作层70时，可通过将掩模70暴露到基于氧的等离子体(例 如O2/Cl2等离子体或O2/HBr等离子体)来执行所述修整。在此实施例中，对光致抗蚀剂70的修整的目的在于使每一特征70的宽度缩小0.25(25％)。也就是说，在修整之后，每一特征的宽度均从预修整特征的宽度缩小了约25％。在为规定修整工艺的此实施例及其它实施例执行修整的替代方案中，如果光刻工艺足够宽松以允许无需修整即直接进行图案化，则可替代地根据图8的尺寸直接印刷光致抗蚀剂特征70。完成后掩模的目标密度是原始图案的四倍，其中所述原始图案是图7处的未经修整光致抗蚀剂层70。由于目标是形成是原始图案四倍的图案密度(即，具有原始间距1/4的间距)，因此由1/2m指示的所需间隔物层的数目为2。 
接下来，在图8结构的表面上方沉积第一间隔物层90(例如二氧化硅)以形成图9的结构。第一间隔物层90的目标厚度是图7的原始图案70的宽度的0.25倍。参照图9，距离92与每一经修整光致抗蚀剂特征70的宽度相同。使用常规技术对图9的第一间隔物层90执行间隔物蚀刻以形成具有第一间隔物90′的图10结构。 
在对第一间隔物层90进行间隔物蚀刻以形成间隔物90′之后，使用(例如)由晶片清洗所遵循的灰化工艺来移除光致抗蚀剂层70以形成图11结构。由于此工艺移除极少或不移除第一间隔物90′，所以110处及92处的间隔不发生明显变化。 
接下来，在图11结构上方形成第二间隔物层120以形成图12结构。选择第二间隔物层120的材料以使得第一间隔物90′可选择性地针对层120被移除(即，可移除间隔物层90′而几乎不或不蚀刻层120)。在此实施例中，第二间隔物层120包括氮化硅。此层120的目标厚度也等于原始未经修整光致抗蚀剂特征的厚度的0.25倍。由于图11的间距110与92大约相等，所以图12的间距122与124也大约相等。 
在形成图12结构之后，对第二间隔物层120执行诸如间隔物(各向异性)蚀刻的蚀刻以形成图13中具有第二间隔物120′的结构。然后选择性地针对第二间隔物120′移除第一间隔物90′以形成图14结构。可使用所属技术领域中已知的诸如经缓冲氢氟酸(HF)等湿工艺或干蚀刻工艺来选择性地移除二氧化硅。在此实施例中，通过剩下第二间隔物120′而形成的图案具有是图7的原始层70的四倍的密度(即，间距是图7的特征的间距的0.25倍)。用于选择性地针对第二间隔物120′移除第一间隔物90′的特定蚀刻视每一层所使用的材料而定，且可以是所属技术领域中已知的任何合适的蚀刻。最后，通过将间隔物120′用作图案来蚀刻待蚀刻层72以从待蚀刻层72形成特征。可使用以对间隔物120′合理的选择性来移除层72并形成类似于图15结构的完成后结构的任何蚀刻剂。 
对于此实施例，可以数学术语来描述与所形成的图案相关的各种元件的大小。参照图7，将每一牺牲光致抗蚀剂特征70形成为任意宽度1，其中每一特征70之间的距离14也为1；因此，间距为2。将每一光致抗蚀剂特征70修整掉X以形成图8的结构。因此，每一特征70具有宽度1-X，且每一特征之间的距离14为1+X。在此实施例中，当每一特征70具有宽度1时，X等于0.25(即，特征70的宽度的25％)。接下来，形成第一间隔物层90使其具有厚度“a”，因而距离92等于1+X-2am，其 中m是所述工艺中相距如此远而形成的间隔物层的数目(即，1)。在此实施例中，且在将CD减小到起始CD的1/2m的其它实施例中，“a”(第一间隔物层90的厚度)的目标确定为与相等X(从每一特征70修整掉的宽度)。蚀刻第一间隔物层90以形成图10结构不会改变元件70或90之间的关系。移除光致抗蚀剂特征70以形成图11可形成具有宽度1-X(.75)(所述宽度是光致抗蚀剂特征70的后修整宽度)的开口110及1+X-2am的距离92。(由于此时“a”等于X且m等于1，1-X＝1+X-2am，因此不将任何工艺引发的偏差计算在内，两个距离110与92相等。)在图12处，形成第二间隔物层120使其具有厚度“a”(同样，对于此实施例来说，“a”等于X)。因此，距离122等于1-X-2a(m-1)，其中m是相距如此远而形成的间隔物层的数目(即，2)。接下来，蚀刻第二间隔物层120以形成图13结构，且移除第一间隔物层90以形成图14的结构。 
当图7处的光致抗蚀剂70的原始(预修整)宽度等于1，则图14中每一特征之间的距离等于0.25。如以上段落中所描述，距离122等于1-X-2a(m-1)，其中对于此实施例来说，X＝a＝0.25且m＝2(间隔物层的数目)。因此，可确定距离122等于1-0.25-2(2-1)0.25＝0.25。此外，距离124等于1+X-2am，因此可确定距离124等于1+0.25-2(.25)(2)＝0.25。笼统地说，第一及第二间隔物层厚度“a”等于X(修整量)，且还等于1/2m(最终CD，其中“m”等于间隔物层的数目)。 
预期，可修改上文所描述工艺以获得表达式1/2m中的较高m值，从而将特征密度增大2倍。图7及16-22中描绘了一种其中m＝3的工艺，其将特征间距减少1/6(即，特征密度增大了六倍)。同样，为便于解释，光致抗蚀剂的最初目标宽度为任意厚度1，其中光致抗蚀剂之间的距离为1。因此，所述光致抗蚀剂特征具有间距2，其描绘于图7中。在形成图7结构之后，将每一光致抗蚀剂特征70修整掉其宽度的1/6(即，X＝1/6)。因此，光致抗蚀剂特征70之间的距离增大到7/6。 
接下来，在图16中所描绘的经修整光致抗蚀剂上方形成毯覆式第一间隔物层16，例如氮化硅。第一间隔物层160的目标厚度是厚度1/6。在图16中，光致抗蚀剂70具有5/6的宽度162，且距离164也等于5/6。第一间隔物层160是经蚀刻以形成图17中所描绘的第一间隔物160′的间隔物。每一间隔物160′的目标基底宽度均保持在1/6。作为第一间隔物层的间隔物层160表示m＝1。 
在形成图17结构之后，移除光致抗蚀剂70并在图18所描绘的第一间隔物160′上方形成毯覆式第二间隔物层180。作为第二间隔物层的间隔物层180表示m＝2。第二间隔物层180由一种可针对第一间隔物160′选择性地蚀刻的材料形成，例如二氧化硅。第二间隔物层180的目标厚度为1/6，因此距离182等于3/6(即，X/2)。图18结构经受层180的间隔物蚀刻以形成如图19中所描绘的第二间隔物180′，然后形成如图中所描绘的毯覆式第三间隔物层190。第三间隔物层190可由与第一间隔物层相同的材料形成，例如氮化硅，且其目标厚度为1/6。因此距离192为1/6。间隔物层190表示m＝3，且最终间隔物层以1/2m表示，其中m＝3。 
执行对层190的间隔物蚀刻以形成包括间隔物160′、180′及190′的图20的结构，然后蚀刻第二间隔物180′并选择性地针对第一间隔物160′且针对第三间隔物190′将其移除。在选择性地针对氮化硅间隔物160′及190′蚀刻二氧化硅第二间隔物180′之后，剩下图21的结构。间隔物160′、190′提供具有是图7的光致抗蚀剂层70的密度的六倍的密度的掩模。最后，通过将间隔物160′、190′作为掩模来蚀刻待蚀刻层72以形成图22的结构。 
根据本文说明可修改此工艺以获得任何m值。最大m值的实际限度视处理技术及图7处X的起始尺寸(光致抗蚀剂的宽度及光致抗蚀剂之间的距离)而定。 
对于m次的总间隔物沉积来说，从第(m-1)、第(m-3)、第(m-5)等次沉积获得的间隔物为牺牲间隔物且可选择性地被移除。对于其中m＝3的图16-22的实施例来说，m-1间隔物(即，第二间隔物180′)是牺牲间隔物且被移除。对于本发明揭示内容来说，术语“牺牲”是指在图案化中所使用的可在图案化待蚀刻层之前被移除的间隔物或其它层(例如层70)。 
在上文所述提供1/2m(其中m是所形成的间隔物层的数目)的CD减小的实施例中，间距的减少是2的倍数(即，1/2、1/4、1/6等)。下文描述的实施例提供1/(2m-1)(其中m≥2)的CD减小，因此所述减小可以是原始图案的1/3、1/5、1/7等。 
在此实施例中，图7的结构是根据所属技术领域中已知的技术而形成的，且包括待蚀刻层72以及包括上覆于待蚀刻层72的光致抗蚀剂70的光刻图案。所述待蚀刻层可以是半导体晶片、上覆于半导体层的一个或一个以上层或待经受图案化蚀刻的一个或一个以上其它层。在此实施例中，光刻特征70在光刻限定下形成，其中每一特征70的宽度及特征70之间的间距14均大约相等。层70可包括不同于光致抗蚀剂的经图案化材料。 
在形成图7结构之后，在图7结构的表面上方沉积第一间隔物层230(例如二氧化硅)以形成图23的结构。第一间隔物层230的目标厚度为光致抗蚀剂70的宽度的1/3倍。对图23的第一间隔物层230执行间隔物蚀刻，然后移除光致抗蚀剂层70，从而形成具有间隔物230′的图24结构。由于间隔物蚀刻及光致抗蚀剂蚀刻极少或不移除第一间隔物层230的竖直部分，因此232及240处的间距不发生明显变化。间距240等于图23中所描绘的光致抗蚀剂层70的宽度。 
接下来，在图24结构上方形成第二间隔物层250以形成图25结构。选择第二间隔物层250的材料以使得第一间隔物230′可选择性地相对于层250被移除。在此实施例中，第二间隔物层250包括氮化硅。此层250的目标厚度也等于图23中所描绘的光致抗蚀剂层70的厚度的1/3倍。相距如此远的工艺形成约为图23中所描绘的光致抗蚀剂层70的宽度的1/3的间距232。由于形成层250使其具有大于232的距离(等于1/3)的1/2的厚度(等于1/3)，因此层250桥接跨越232处的开口，但不桥接跨越240处的开口。 
在形成图25结构之后，对第二间隔物层250执行诸如间隔物蚀刻的蚀刻以形成 包括间隔物230′及250′的图26的结构。此蚀刻暴露待蚀刻层72，但仅在最初在其上形成光致抗蚀剂层70的位置260处暴露。此外，位置260各自仅为图23处光致抗蚀剂层70的宽度的1/3。 
在形成图26结构之后，选择性地针对第二间隔物250′蚀刻第一间隔物230′以形成图27的结构。在此实施例中，通过剩下第二间隔物层250而形成的图案具有是图23处的层70的三倍(即，间距是图23处的特征70的间距的1/3倍)的密度。用于选择性地针对第二间隔物250′移除第一间隔物230′的特定蚀刻可视每一层所使用的材料而定，且可以是所属技术领域中已知的任何合适蚀刻。最后，使用以针对间隔物250′的合理选择性移除层72(未描绘移除)的任何蚀刻剂来蚀刻待蚀刻层72。 
可对图25结构执行平坦化工艺(例如CMP工艺)以形成图28的结构，而不是对图25结构执行间隔物蚀刻以形成图26结构。然后移除间隔物230′以留下图29的图案，然后执行对间隔物层250的蚀回(间隔物蚀刻)以形成包括间隔物250′的图30结构。最后，蚀刻层72以形成图31的结构。此CMP工艺可形成间隔物250′，其包括比使用间隔物蚀刻更均匀的高度，这对于后续处理来说可是有利的。当对图29结构执行间隔物蚀刻以清除层250的连接相邻间隔物的水平部分时，图30所描绘的所有特征250′均为间隔物，且包括平坦共面顶部。 
在先前段落的替代实施例中，可首先执行图28的层250的回蚀，然后可移除间隔物230′。 
图23-27的工艺提供1/(2m-1)(其中m＝2)的CD减小(其中包括间隔物层230及250)，因此间距减小为1/3(特征密度的三倍)。可修改此工艺以获得任何实际m值，因此所述减小可以是原始图案的1/3、1/5、1/7等。下文描绘一种其中m＝3的工艺，因此间距将为原始掩模的1/5(即，特征密度的五倍)。同样，为便于解释，光致抗蚀剂的最初目标宽度为任意厚度1，其中光致抗蚀剂之间的距离为1。因此，所述光致抗蚀剂特征具有间距2，此描绘于图7中。如同图23-27的实施例，此实施例中没有修整光致抗蚀剂。 
对于此实施例，在图7结构上方形成毯覆式间隔物层，例如氮化硅。所述毯覆式间隔物层具有是每一光致抗蚀剂特征70的宽度的1/5的目标厚度。对第一间隔物层执行间隔物蚀刻以留下具有第一间隔物320、光致抗蚀剂70及待蚀刻层72的图32的结构。此时，m＝1，其中间隔物320从第一间隔物形成。 
移除光致抗蚀剂层70且在第一间隔物320上方形成第二间隔物层330，如图33中所描绘。层330包括可选择性地针对间隔物320的材料而被蚀刻的材料，例如二氧化硅。层330的目标厚度为1/5，因此332处的间距为3/5且334处的间距为1/5。执行间隔物蚀刻以形成具有第一间隔物320及第二间隔物330′的图34的结构，因此在所述工艺中的此处m＝2，其中间隔物330′从第二间隔物层320形成。 
接下来，形成第三间隔物层350。第三间隔物层350可包括与第一间隔物层相同的材料，在此实施例中为氮化硅，或包括将经受住对第二间隔物层的蚀刻的不同材料。 第三间隔物层的目标厚度为1/5。因为第三间隔物层350的目标厚度大于334处间距的一半，所以层350桥接跨越开口334的两端，而在间距332处保形地形成，其具有距离3/5。由于已有三个间隔物层用于所述工艺中的此处，因此m＝3。 
在完成图35结构后，对第三间隔物层350执行间隔物蚀刻以形成具有第三间隔物350′的图36的结构。 
随后，选择性地针对第一间隔物320及第三间隔物350′蚀刻第二间隔物330′以形成图37结构。然后将剩余间隔物320、350用作掩模来蚀刻待蚀刻层72以形成图38的结构。最后，可移除间隔物320、350′。 
在使用间隔物蚀刻的替代方案中，可对各种实施例的结构执行平坦化，例如CMP。此CMP工艺可形成具有均匀高度的间隔物中的每一者，此对于后续处理可是有利的。当使用较高m值时，使用平坦化工艺而非间隔物蚀刻来移除间隔物层的一部分可是有利的。使用平坦化工艺而形成的结构将具有类似于图31的轮廓，而不是具有使用间隔物蚀刻而形成的图38的轮廓。还预期，一个或一个以上间隔物蚀刻可与一个或一个以上平坦化工艺组合。 
如同图7-22所描绘的实施例，可以数学术语来描述与通过图23-38的实施例形成的图案相关的各种元件的大小。将CD减小到其原始值的1/(2m-1)，其中CD的原始值是图23及32处的光致抗蚀剂特征70的宽度，且m是所形成的间隔物层的数目，其中m≥2。可使用方程式1+X+2ma＝-a来确定既定的CD减小所需要的间隔物层的数目，其中m≥2，且“a”是间隔物层的厚度被原始光致抗蚀剂层的宽度所除而得。在此实施例中，X＝0表示没有修整。 
虽然原始掩模层70在图7-22的实施例中被修整且在图23-38的实施例中未被修整，但所述两个工艺具有相似之处。例如，仅由两种不同类型材料形成所有间隔物是可能的(但不是必需的)。m、m-2、m-4等间隔物层可均由相同材料形成，而m-1、m-3、m-5等层也可由相同材料形成(但不同于所述m、m-2、m-4等层且可选择性地针对所述层来蚀刻)。每一间隔物层均由不同于前述间隔物的材料形成。此外，在形成第二间隔物层之前移除这两个实施例中的原始遮蔽层一层70。同样，在任一实施例中均可移除m-1、m-3、m-5等间隔物层，而m、m-2、m-4等间隔物层则可用作图案。 
图7-22的实施例提供是偶数的特征密度乘数，而图23-38的实施例则提供是奇数的特征密度乘数。图7-22的实施例不具有对间隔物层的桥接，而图23-38的两个实施例则具有对间隔物层的桥接(图25的232处及图35的334处)的实例。 
在又一实施例中，形成图14的结构，且使用层120来代替图7的光致抗蚀剂层70。因此，如图8-11所进行的那样修整层120且形成间隔物层并蚀刻间隔物，然后移除层120。所述工艺对于图12及13的第二间隔物层继续进行。 
在另一实施例中，形成图27的结构，且使用层250来代替图7的光致抗蚀剂层70。因此，如在图24中对层70所进行的那样在层250上方形成间隔物层，然后移除 层250，且将此最终间隔物层用作掩模来蚀刻层10。可以本文所揭示的其它实施例来执行类似工艺。 
如图39中所描绘，根据本发明形成的半导体装置390可连同其它装置(例如，微处理器392)一起附装到印刷电路板394(例如，附装到计算机母板)，或作为用于个人计算机、小型计算机或大型计算机396中的存储器模块的一部分。所述微处理器及/或存储器装置可与本发明实施例一起(或以其它方式包括)形成。图39还可表示装置390在与电信、汽车工业、半导体测试及制造装备、消费者电子装置或实质上任何一件消费者或工业电子装备有关的其它电子装置(包括外壳396)中的使用，例如包括微处理器392的装置。 
本文中所描述的工艺及结构可用于制造若干不同结构，其中包括根据本发明工艺而形成的经图案化层。例如，图40是具有容器式电容器、晶体管栅极及可使用本发明实施例而形成的其它特征的存储器装置(例如动态随机存取存储器)的简化方块图。所属技术领域的技术人员已知这一装置的一般操作。图40描绘耦合到存储器装置390的处理器392，且进一步描绘存储器集成电路的以下基本部分：控制电路400；行地址缓冲器402；列地址缓冲器404；行解码器406；列解码器408；感测放大器410；存储器阵列412；及数据输入/输出414。 
虽然已参照说明性实施例对本发明进行了描述，但并不打算将此说明解释为限定性意义。参照此说明，所属技术领域的技术人员将明了对说明性实施例以及本发明额外实施例的各种修改。例如，描述为从光致抗蚀剂形成的结构可由其它材料形成，例如无定形碳(AC)、透明碳(TC)、多层抗蚀剂(MLR)或双层抗蚀剂(BLR)。可执行干显影蚀刻以将图案从光致抗蚀剂层转变为介电抗反射涂层(DARC)，或转变为底部抗反射涂层(BARC)，然后转变为无定形碳、透明碳、下伏多层抗蚀剂或者转变为多层抗蚀剂或双层抗蚀剂的衬层。此外，可对干显影蚀刻之前的光致抗蚀剂或对干显影蚀刻之后的下伏层执行修整(如果采用)。 
假定各种实施例中的间隔物厚度均等于目标CD。结果是，线与间距具有相等宽度。然而，所述两种类型的间隔物材料的间隔物的厚度可是不同的，因而可形成具有各种占空系数的最终图案，只要所述两个间隔物厚度的和等于最终间距。例如，在间距三倍减小工艺期间，较厚的第一间隔物可与较薄的第二间隔物一起使用。在选择性地移除第一间隔物之后，形成间距宽松的最终图案(即，线小于间距)，其厚度是原始厚度的三倍。这在某些实施例中可是较佳的，例如当与浅沟槽隔离工艺一起使用时。因此，预期所附权利要求书将涵盖归属于本发明真实范围内的任何此类修改或实施例。 

Claims (14)

1.一种在半导体装置制作期间使用的方法，其包括：
提供待蚀刻层；
在所述待蚀刻层上方形成牺牲图案化层，其中所述牺牲图案化层包括具有至少第一及第二截面侧壁的多个分段部分；
形成多个牺牲第一间隔物，其中在所述牺牲图案化层的每一分段部分的每一侧壁上形成一个间隔物；
移除所述牺牲图案化层；
在所述多个牺牲第一间隔物上方形成保形第二间隔物层；
移除所述保形第二间隔物层的一部分以在所述牺牲第一间隔物上形成多个第二间隔物，其中执行平坦化工艺以移除所述保形第二间隔物层的一部分；
在形成所述第二间隔物之后，移除所述牺牲第一间隔物；及
使用所述第二间隔物作为图案来蚀刻所述待蚀刻层，其中所述牺牲图案化层的每一部分均包括第一宽度，且所述方法进一步包括：
将每一牺牲图案化层的所述第一宽度修整为具有比所述第一宽度窄25%的第二宽度；
将所述多个第一间隔物中的每一者形成为具有为所述第一宽度的25%的宽度；及
蚀刻所述保形第二间隔物层以使得所述第二间隔物各自具有为所述第一宽度的25%的宽度。
2.如权利要求1所述的方法，其进一步包括蚀刻所述待蚀刻层以从所述待蚀刻层形成特征，其中从所述待蚀刻层形成的每一特征包括为所述第一宽度的25%的宽度。
3.如权利要求2所述的方法，其进一步包括：
将所述牺牲图案化层的所述多个分段部分形成为具有为所述第一宽度的两倍的预修整间距；及
蚀刻所述待蚀刻层以将所述特征形成为具有为所述牺牲图案化层的所述分段部分的所述预修整间距的25%的间距。
4.如权利要求1所述的方法，其进一步包括：
形成所述牺牲图案化层以使得所述多个分段部分具有第一密度；及
使用所述第二间隔物作为图案来蚀刻所述待蚀刻层以形成多个特征，其中所述多个特征具有为所述第一密度的四倍的第二密度。
5.如权利要求1所述的方法，其进一步包括：
形成所述牺牲图案化层以使得所述多个分段部分具有第一密度；及
使用所述第二间隔物作为图案来蚀刻所述待蚀刻层以形成多个特征，其中所述多个特征具有为所述第一密度的三倍的第二密度。
6.如权利要求1所述的方法，其进一步包括由光致抗蚀剂形成所述牺牲图案化层。
7.如权利要求1所述的方法，其进一步包括由选自由透明碳、多层抗蚀剂及双层抗蚀剂组成的群组的材料形成所述牺牲图案化层。
8.一种在半导体装置制作期间使用的方法，其包括：
提供待蚀刻层；
在所述待蚀刻层上方形成牺牲图案化层，其中所述牺牲图案化层包括具有至少第一及第二截面侧壁的多个分段部分；
形成多个牺牲第一间隔物，其中在所述牺牲图案化层的每一分段部分的每一侧壁上形成一个间隔物；
移除所述牺牲图案化层；
在所述多个牺牲第一间隔物上方形成保形第二间隔物层；
移除所述保形第二间隔物层的一部分以在所述牺牲第一间隔物上形成多个第二间隔物，其中执行平坦化工艺以移除所述保形第二间隔物层的一部分；
在形成所述第二间隔物之后，移除所述牺牲第一间隔物；及
使用所述第二间隔物作为图案来蚀刻所述待蚀刻层，
其中所述牺牲图案化层的每一部分均包括第一宽度，且所述方法进一步包括：
将所述多个第一间隔物中的每一者形成为具有为所述第一宽度的33%的宽度；以及
蚀刻所述保形第二间隔物层以使得所述第二间隔物各自具有为所述第一宽度的33%的宽度。
9.如权利要求8所述的方法，其进一步包括蚀刻所述待蚀刻层以从所述待蚀刻层形成特征，其中从所述待蚀刻层形成的每一特征包括为所述第一宽度的33%的宽度。
10.如权利要求9所述的方法，其进一步包括：
将所述牺牲图案化层的所述多个分段部分形成为具有为所述第一宽度的两倍的预定间距；及
蚀刻所述待蚀刻层以将所述特征形成为具有为所述牺牲图案化层的所述分段部分的所述预定间距的33%的间距。
11.如权利要求8所述的方法，其进一步包括：
形成所述牺牲图案化层以使得所述多个分段部分具有第一密度；及
使用所述第二间隔物作为图案来蚀刻所述待蚀刻层以形成多个特征，其中所述多个特征具有为所述第一密度的三倍的第二密度。
12.如权利要求8所述的方法，其进一步包括由光致抗蚀剂形成所述牺牲图案化层。
13.如权利要求8所述的方法，其进一步包括由选自由透明碳、多层抗蚀剂及双层抗蚀剂组成的群组的材料形成所述牺牲图案化层。
14.一种在电子***制作期间使用的方法，其包括：
使用包括以下步骤的方法来制作半导体装置：
提供待蚀刻层；
在所述待蚀刻层上方形成牺牲图案化层，其中所述牺牲图案化层包括具有至少第一及第二截面侧壁的多个分段部分；
形成多个牺牲第一间隔物，其中在所述牺牲图案化层的每一分段部分的每一侧壁上形成一个间隔物；
移除所述牺牲图案化层；
在所述多个牺牲第一间隔物上方形成保形第二间隔物层；
移除所述保形第二间隔物层的一部分以在所述牺牲第一间隔物上形成多个第二间隔物，其中执行平坦化工艺以移除所述保形第二间隔物层的一部分；
在形成所述第二间隔物之后，移除所述牺牲第一间隔物；及
使用所述第二间隔物作为图案来蚀刻所述待蚀刻层；
提供微处理器；及
在所述半导体装置与所述微处理器之间提供电路径以促进其之间的电连通，其中所述牺牲图案化层的每一部分均包括第一宽度，且所述方法进一步包括：
将每一牺牲图案化层的所述第一宽度修整为具有比所述第一宽度窄25%的第二宽度，将所述多个第一间隔物中的每一者形成为具有为所述第一宽度的25%的宽度，并且蚀刻所述保形第二间隔物层以使得所述第二间隔物各自具有为所述第一宽度的25%的宽度；或
将所述多个第一间隔物中的每一者形成为具有为所述第一宽度的33%的宽度，并且蚀刻所述保形第二间隔物层以使得所述第二间隔物各自具有为所述第一宽度的33%的宽度。
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US9305782B2 (en) 2016-04-05
CN104064457B (zh) 2017-05-31
US20200203171A1 (en) 2020-06-25
CN101490807A (zh) 2009-07-22
KR20090018725A (ko) 2009-02-20
US20160203993A1 (en) 2016-07-14
KR101573286B1 (ko) 2015-12-02
US9761457B2 (en) 2017-09-12
CN104064457A (zh) 2014-09-24
US8852851B2 (en) 2014-10-07
US11935756B2 (en) 2024-03-19
US10607844B2 (en) 2020-03-31
US11335563B2 (en) 2022-05-17
US20080008969A1 (en) 2008-01-10
JP5453650B2 (ja) 2014-03-26
US20220254644A1 (en) 2022-08-11
SG173362A1 (en) 2011-08-29
US10096483B2 (en) 2018-10-09
WO2008008338A3 (en) 2008-03-20

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