CN101477838B - Condition detection apparatus, system and electronic device for NAND flash memory body - Google Patents
Condition detection apparatus, system and electronic device for NAND flash memory body Download PDFInfo
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- CN101477838B CN101477838B CN200810241769.7A CN200810241769A CN101477838B CN 101477838 B CN101477838 B CN 101477838B CN 200810241769 A CN200810241769 A CN 200810241769A CN 101477838 B CN101477838 B CN 101477838B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
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Abstract
The invention, which is suitable for the technical field of electrons, provides a device and a system for detecting states of an NAND flash and an electronic aid, wherein, the device comprises a central processing unit (CPU); the CPU comprises a state detection pin, a BOOT pin 0 and a BOOT pin 1; the CPU is configured into a mode of the high-capacity NAND flash, the state detection pin of the CPU is configured into a ready state , the CPU further comprises a detection unit used for detecting the working conditions of a low-capacity NAND flash through a state query command; and/or the state detection pin of the CPU is connected with the high-capacity NAND flash, so as to detect the working conditions of the high-capacity NAND flash. In the invention, the CPU obtains the working states of the NAND flash through the state detection pin or the state query command, and has the advantages of low application limitation of the hardware platform, and convenient extension.
Description
Technical field
The invention belongs to electronic technology field, relate in particular to a kind of and non-fast flash memory bank condition checkout gear, system, electronic equipment and method.
Background technology
Existing CPU supports and non-fast flash memory bank (NAND Flash) start-up mode mostly, after machine powers on, can from NAND Flash, read startup run time version carries out to internal memory, the initialization such as completion system phaselocked loop, clock, internal memory, peripheral hardware, this just can carry out read-write operation to the storer of start-up code with regard to requiring in the time that CPU powers on.
NAND Flash has distinguished two types of low capacity (Small Block) and large capacity (Large Block) by measure, the NAND Flash that General Definition capacity is more than or equal to 1G bytes is large capacity NANDFlash, and the NAND Flash that capacity is less than 1G bytes is low capacity NAND Flash.NAND Flash for different capabilities has different demands to addressing length, for low capacity NAND Flash, when read-write, need to adopt four circulations (Circle) addressed command to carry out addressing, and for large capacity NAND Flash, when read-write, need to adopt five cyclic addressing orders to carry out addressing.
For the NAND Flash of different capabilities, first sound out 4 cyclic addressing orders of sending 32, if low capacity NAND is Flash, detect that Flash just can read and write in ready (Ready) state; If large capacity NAND Flash, because addressing does not complete, CPU delays the 5th the cyclic addressing order of sending 8, and NAND Flash detecting after correct addressed command, notice CPU its in Ready state, can read and write.
And, NAND Boot Starting mode is system realizes electrifying startup a kind of Starting mode by the boot on Nand Flash, the addressed command of NAND Boot is cured to CPU the inside, brought in and controlled sending of the 5th cyclic addressing order by CPU, whether CPU can decide the 5th sequential that cyclic addressing order is sent in Ready state by detecting NAND Flash.And along with the progress of Flash technique, Flash is also increasingly strict for the judgement of addressed command, for some low capacity NAND Flash, if it completes rear unexpected the 5th the cyclic addressing order of receiving of read-write preparation, can automatically interrupt read-write, cause CPU cannot read the data in NAND Flash, system starts unsuccessfully.So, the NAND Boot function of CPU just depends on the detection constraint of Flash manufacturer self, and the Flash that causes Flash type selecting to be confined to certain batch could use.Current, the NAND Flash of new technology has become the market mainstream, and the NAND Flash of original batch slowly withdraws from the market, and for example the Samsung of main flow and modern NAND Flash can occur that this type of is incompatible on the market.In addition, because the control operation flow process of CPU and NAND Flash is to be all cured to chip internal, once both occur incompatible, be the defect that cannot go beyond for the developer who uses this type of hardware plan, replace the material alteration that any one hardware all may cause scheme.And this defect is all often just to come out in the platform development later stage, can cause whole Platform to face the situation of redesign.
In sum, the NAND Flash that the existing system start method based on NAND Flash can not compatible two kinds of different capabilities, the limitation that hardware platform is used is large, inconvenience expansion.
Summary of the invention
The object of the embodiment of the present invention is to provide a kind of system start method based on NAND Flash, is intended to solve the problem that limitation is large, inconvenience is expanded that the existing system start method based on NAND Flash uses hardware platform.
The embodiment of the present invention is achieved in that a kind of and non-fast flash memory bank condition checkout gear, comprises CPU, and described CPU comprises state-detection pin, BOOT 0 pin and BOOT 1 pin, and described CPU is configured to large capacity and non-fast-flash memory bulk-mode,
The state-detection pin of described CPU is set to ready state, and described CPU also comprises detecting unit, for detect the duty of low capacity and non-fast flash memory bank by status inquiry command; And/or
The state-detection pin of described CPU is connected with non-fast flash memory bank with outside large capacity, detects the duty of described large capacity and non-fast flash memory bank.
Another object of the embodiment of the present invention is to provide a kind of system based on starting with non-fast flash memory bank that comprises above-mentioned and non-fast flash memory bank condition checkout gear, and described system also comprises and non-fast flash memory bank;
In the time that described and non-fast flash memory bank is large capacity and non-fast flash memory bank, the state-detection pin of described CPU connects state-detection pin described and non-fast flash memory bank through the second resistance R 2;
In the time that described and non-fast flash memory bank is low capacity and non-fast flash memory bank, the state-detection pin of described CPU is set to ready state, described CPU also comprises detecting unit, for detect duty described and non-fast flash memory bank by status inquiry command;
Described CPU detects with non-fast flash memory bank when ready by state-detection pin, sends address to described and non-fast flash memory bank, reads the data of storing in described and non-fast flash memory bank with startup system.
Described and non-fast flash memory bank, starts required data for storage system, reads the data of storage according to the address receiving, and returns to described CPU the data that read.
Another object of the embodiment of the present invention is to provide a kind of electronic equipment that comprises the above-mentioned system based on starting with non-fast flash memory bank.
Another object of the embodiment of the present invention is to provide a kind of low capacity and non-fast flash memory bank condition detection method, and described method comprises the steps:
Send the querying command of inquiry low capacity and non-fast flash memory bank duty;
The state value that reception is returned;
Judge the duty of low capacity and non-fast flash memory bank according to the state value receiving;
In the duty that judges described low capacity and non-fast flash memory bank while being busy, the time that time delay is default.
In embodiments of the present invention, CPU detects pin by detected state or obtains and the duty of non-fast flash memory bank by status inquiry command, a kind of and non-fast flash memory bank condition checkout gear are realized, for the NAND Flash of different capabilities, hardware design is changed little, and hold embedded NAND Boot start-up code just can carry out corresponding read-write operation to NAND Flash after technique upgrading without amendment CPU, limitation that hardware platform is used is less, be convenient to expand.
Brief description of the drawings
Fig. 1 is the structural representation of the NAND Flash condition checkout gear that provides of the embodiment of the present invention;
Fig. 2 is the pin level schematic diagram that the embodiment of the present invention provides;
Fig. 3 is the structural representation of the system based on starting with non-fast flash memory bank that provides of the embodiment of the present invention;
Fig. 4 be the embodiment of the present invention that provide with realization flow figure non-fast flash memory bank condition detection method.
Embodiment
In order to make object of the present invention, technical scheme and advantage clearer, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein, only in order to explain the present invention, is not intended to limit the present invention.
In embodiments of the present invention, CPU detects pin by detected state or obtains and the duty of non-fast flash memory bank by status inquiry command.
Fig. 1 shows the structure of the NAND Flash condition checkout gear that the embodiment of the present invention provides, and only shows for convenience of explanation the part relevant to the embodiment of the present invention.
This device can be for the system starting based on NAND Flash, also can be for electronic equipment, for example mobile terminal, personal digital assistant (Personal Digital Assistant, PDA), portable navigator (Portable Navigation Devices, PND) etc., can be to run on the unit that software unit, hardware cell or software and hardware in these electronic equipments combine, also can be used as independently suspension member is integrated in these electronic equipments or runs in the application system of these electronic equipments, wherein:
CPU 101 is configured to large capacity NAND Flash pattern.In embodiments of the present invention, BOOT 1 pin of CPU 101 is through capacitor C ground connection, and BOOT 0 pin connects operating voltage through the first resistance R 1.
For large capacity NAND Flash, the state-detection pin of CPU 101 is connected with non-fast flash memory bank with outside large capacity, detects the duty of outside large capacity NAND Flash.In embodiments of the present invention, the state-detection pin of CPU101, i.e. R/B# pin, connects the second resistance R 2.In use, the R/B# pin of the outside large capacity Nand Flash of another termination of the second resistance R 2, CPU 101 obtains the duty of large capacity NAND Flash by detecting the voltage of R/B# pin, in the time detecting that large capacity NAND Flash is ready state, large capacity NAND Flash is carried out to corresponding reading and writing operation.Wherein, operating voltage is 3.3V, and capacitor C is 0.01-0.1 microfarad, and the first resistance R 1 can be 10K ohm, and the second resistance R 2 is 0-10 ohm.Certainly, the value of capacitor C, the first resistance R 1 and the second resistance R 2 can also modify according to actual conditions, select.
For low capacity NAND Flash, the state-detection pin of CPU 101 is set to ready state, the R/B# pin of CPU 101 is unsettled or connect pull-up resistor to power supply, and CPU 101 also comprises:
Detecting unit 1011, detects the duty of outside low capacity NAND Flash by status inquiry command.
Wherein, detecting unit 1011 comprises:
Order sending module 10111, sends NAND Flash status inquiry command.In embodiments of the present invention, status inquiry command is sent to command port by CPU 101, and this command port is the CMD port that is embedded into the NAND Flash controller in CPU.
Condition judgment module 10112, the duty of the NAND Flash that judgement inquires.
State processing module 10113, in the time that condition judgment module 10112 judges that the duty of NAND Flash is busy (busy), the time that time delay is default, and control command sending module 10111 continues to detect; In the time that condition judgment module 10112 judges that the duty of NAND Flash is ready, detection of end.
In embodiments of the present invention, status inquiry command (being 0x70) is sent to command port by order sending module 10111, NAND Flash responds this order after receiving status inquiry command, inquire about the state of himself, and return and send the state value inquiring to CPU 101 by data line.Then, condition judgment module 10112 is preserved the state value receiving by FPDP, and judges whether the 6th of this state value is 0, if 0 judges that NAND Flash is Busy state, state processing module 10113 time delay 50 μ s, return to step 1 and continue inquiry; If 1 judges that NAND Flash is Ready state, state processing module 10113 detection of end, CPU 101 can carry out corresponding reading and writing operation to NAND Flash.Certainly,, in the time detecting that NAND Flash is Busy state, the delay time of state processing module 10113 can be determined according to the reality precision consuming time of NAND Flash reading and writing data, is generally microsecond unit, for example, can be 30-100 microsecond.Thereby make that the present embodiment provides with non-fast flash memory bank condition checkout gear can without change hardware design, without the embedded NAND Boot start-up code of amendment CPU 101 ends just can to technique upgrading afterwards NAND Flash carry out corresponding read-write operation.
In addition, when CPU 101 detects the duty of NAND Flash by status inquiry command, the time interval of himself state of NANDFlash inquiry need to reach microsecond rank, need to revise the code for status monitoring part in NAND Flash driver, to remove to inquire about himself state by the unit of Microsecond grade.Like this, CPU 101 could obtain correct sequential, NAND Flash is carried out to normal reading and writing operation.Wherein, the driver of NAND Flash can be by developer's amendment or replacement arbitrarily, so implement more convenient.
Fig. 2 shows the Flash for low capacity NAND, pin level schematic diagram, as from the foregoing, for low capacity NAND Flash, cut off and open being connected between CPU 101R/B# pin and low capacity NAND Flash R/B# pin, keep the pull-up state of CPU 101 R/B# pins, CPU 101 can think that low capacity NANDFlash is always in Ready state, the WE# pin of CPU 101 can follow front 4 cyclic addressing orders closely and send the 5th cyclic addressing order so, front 4 cyclic addressing orders that CPU 101 sends are as the sequential in the solid line ellipse that in Fig. 2, WE# pin is corresponding, the 5th cyclic addressing order is as the sequential in the dotted ellipse that in Fig. 2, WE# pin is corresponding.Need consuming timely because low capacity NAND Flash receives front 4 cyclic addressing order aftertreatment data that CPU 101 sends, in the time that CPU 101 sends the 5th cyclic addressing order, low capacity NAND Flash reality is in Busy state so.Like this, low capacity NAND Flash just can not respond the 5th the cyclic addressing order receiving, therefore can not interrupt read-write operation, hold normal data to prepare after time delay until low capacity NAND Flash, correctly send data by IO pin, avoided it in the time receiving the 5th cyclic addressing order, automatically to interrupt read-write and caused system to start unsuccessfully.
Fig. 3 shows the structure of the system starting based on NAND Flash, only shows for convenience of explanation the part relevant to the embodiment of the present invention.
Wherein, the system starting based on NAND Flash comprises above-mentioned NAND Flash condition checkout gear and NAND Flash 102.
In the time that NAND Flash 102 is large capacity NAND Flash, the R/B# pin of CPU 101 connects the R/B# pin that meets NAND Flash 102 through the second resistance R 2, and CPU 101 obtains the duty of NANS Flash by detecting the voltage of R/B# pin.
In the time that NAND Flash 102 is low capacity NAND Flash, between the R/B# pin of CPU 101 and the R/B# pin of NAND Flash 102, disconnect, the R/B# pin of CPU 101 is set to ready state, can be by unsettled the R/B# pin of CPU 101 or connect pull-up resistor to power supply.And CPU 101 also comprises:
Detecting unit 1011, detects the duty of NAND Flash 102 by status inquiry command.
Wherein, detecting unit 1011 comprises:
Order sending module 10111, sends NAND Flash status inquiry command.In embodiments of the present invention, status inquiry command is sent to command port by CPU 101, and its implementation is described above, repeats no more.
Condition judgment module 10112, the duty of the NAND Flash that judgement inquires, its implementation is described above, repeats no more.
State processing module 10113, in the time that condition judgment module 10112 judges that the duty of NAND Flash 102 is busy (busy), the time that time delay is default, and control command sending module 10111 continues to detect; In the time that condition judgment module 10112 judges that the duty of NAND Flash 102 is ready, detection of end, its implementation is described above, repeats no more.
In addition, for low capacity NAND Flash 102, also need to revise the code for status monitoring part in its driver, so that the unit that the frequency of himself state of low capacity NAND Flash 102 inquiry is Microsecond grade.
CPU 101 detects that by R/B# pin NAND Flash 102, when ready, sends address to NANDFlash 102, reads the data of storage in NAND Flash 102 with startup system.
In NAND Flash 102, storage system starts required data, reads the data of storage according to the address receiving, and returns to CPU101 the data that read.
Fig. 4 show the embodiment of the present invention that provide with realization flow non-fast flash memory bank condition detection method, details are as follows:
In step S401, send the querying command of inquiry and non-fast flash memory bank duty;
In step S402, receive the state value returning;
In step S403, the duty according to the state value judgement receiving with non-fast flash memory bank;
In step S404, in the time that to judge with the duty of non-fast flash memory bank be busy, the time that time delay is default.
In embodiments of the present invention, by command port, status inquiry command (being 0x70) is sent to corresponding NAND Flash, and receive the state value that corresponding NAND Flash returns.Then, judge whether the 6th of this state value is 0, if 0 judges that corresponding NAND Flash is Busy state, after time delay 50 μ s, return to step S401 and continue inquiry; If 1 judges that corresponding NAND Flash is Ready state, detection of end.Delay time can be determined according to the reality precision consuming time of corresponding NAND Flash reading and writing data, is generally microsecond unit, for example, can be 30-100 microsecond.
In embodiments of the present invention, CPU detects pin by detected state or obtains and the duty of non-fast flash memory bank by status inquiry command, realize a kind of NAND Flash condition checkout gear, for the NAND Flash of different capabilities, hardware design is changed little, and hold embedded NANDBoot start-up code just can carry out corresponding read-write operation to NAND Flash after technique upgrading without amendment CPU, limitation that hardware platform is used is less, be convenient to expand.
One of ordinary skill in the art will appreciate that, the all or part of step realizing in above-described embodiment method is can carry out the hardware that instruction is relevant by program to complete, described program can be being stored in a computer read/write memory medium, described storage medium, as ROM/RAM, disk, CD etc.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, all any amendments of doing within the spirit and principles in the present invention, be equal to and replace and improvement etc., within all should being included in protection scope of the present invention.
Claims (8)
1. with a non-fast flash memory bank condition checkout gear, comprise CPU, described CPU comprises state-detection pin, BOOT0 pin and BOOT1 pin, the BOOT1 pin of described CPU is through capacity earth, described CPU is configured to large capacity and non-fast-flash memory bulk-mode, it is characterized in that
By unsettled the state-detection pin of described CPU or connect pull-up resistor to described BOOT0 pin, described CPU also comprises detecting unit, for detect the duty of outside low capacity and non-fast flash memory bank by status inquiry command; And/or
The state-detection pin of described CPU is connected with non-fast flash memory bank with outside large capacity, detects the duty of described large capacity and non-fast flash memory bank;
Described detecting unit comprises:
Order sending module, for sending and non-fast flash memory bank status inquiry command;
Condition judgment module, for judging that inquire and duty non-fast flash memory bank; And
State processing module, while being busy for judge with the duty of non-fast flash memory bank in described condition judgment module, the time that time delay is default, and control described order sending module and continue to detect.
2. device as claimed in claim 1, is characterized in that, described CPU is configured to large capacity and non-fast-flash memory bulk-mode is that the BOOT0 pin of described CPU is connect to operating voltage through the first resistance, by the BOOT1 pin of described CPU through capacity earth.
3. device as claimed in claim 1, is characterized in that, the state-detection pin of described CPU is connected with non-fast flash memory bank with outside large capacity through the second resistance.
4. device as claimed in claim 3, is characterized in that, the described default time is 30-100 microsecond.
5. comprise described in claim 1 to 4 any one and the system based on starting with non-fast flash memory bank of non-fast flash memory bank condition checkout gear, it is characterized in that, described system also comprises and non-fast flash memory bank;
In the time that described and non-fast flash memory bank is large capacity and non-fast flash memory bank, the state-detection pin of described CPU connects state-detection pin described and non-fast flash memory bank through the second resistance R 2;
In the time that described and non-fast flash memory bank is low capacity and non-fast flash memory bank, the state-detection pin of described CPU is set to ready state, described CPU also comprises detecting unit, for detect duty described and non-fast flash memory bank by status inquiry command;
Described CPU detects with non-fast flash memory bank when the ready state by state-detection pin, sends address to described and non-fast flash memory bank, reads the data of storing in described and non-fast flash memory bank with startup system;
Described and non-fast flash memory bank, starts required data for storage system, reads the data of storage according to the address receiving, and returns to described CPU the data that read.
6. system as claimed in claim 5, is characterized in that, the frequency of himself state of described low capacity and non-fast flash memory bank inquiry is Microsecond grade.
7. one kind comprises described in claim 5 electronic equipment of the system based on starting with non-fast flash memory bank.
8. one kind comprises described in claim 6 electronic equipment of the system based on starting with non-fast flash memory bank.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200810241769.7A CN101477838B (en) | 2008-12-31 | 2008-12-31 | Condition detection apparatus, system and electronic device for NAND flash memory body |
| PCT/CN2009/075939 WO2010075746A1 (en) | 2008-12-31 | 2009-12-24 | Nand flash state detecting device, system, electrical device and method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200810241769.7A CN101477838B (en) | 2008-12-31 | 2008-12-31 | Condition detection apparatus, system and electronic device for NAND flash memory body |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101477838A CN101477838A (en) | 2009-07-08 |
| CN101477838B true CN101477838B (en) | 2014-07-30 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN200810241769.7A Expired - Fee Related CN101477838B (en) | 2008-12-31 | 2008-12-31 | Condition detection apparatus, system and electronic device for NAND flash memory body |
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| Country | Link |
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| CN (1) | CN101477838B (en) |
| WO (1) | WO2010075746A1 (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101477838B (en) * | 2008-12-31 | 2014-07-30 | 深圳市同洲电子股份有限公司 | Condition detection apparatus, system and electronic device for NAND flash memory body |
| CN102279823B (en) * | 2011-06-13 | 2013-09-18 | 杭州华三通信技术有限公司 | Device and method for detecting status of Nand Flash |
| TWI494944B (en) | 2013-10-25 | 2015-08-01 | Phison Electronics Corp | Method of detecting memory modules, memory control circuit unit and storage appartus |
| CN104615554B (en) * | 2013-11-04 | 2018-11-23 | 群联电子股份有限公司 | Memory module detection method, memorizer control circuit unit and storage device |
| KR20190018326A (en) * | 2017-08-14 | 2019-02-22 | 에스케이하이닉스 주식회사 | Memory system and operation method for the same |
| CN110993012B (en) * | 2019-11-12 | 2023-07-25 | 山东华芯半导体有限公司 | Device and method for counting nand flash busy time |
| CN111857599A (en) * | 2020-07-29 | 2020-10-30 | 浪潮(北京)电子信息产业有限公司 | Data reading and writing method, device and equipment and readable storage medium |
| CN112130789B (en) * | 2020-08-06 | 2024-05-10 | 许继集团有限公司 | Method for converting insufficient space of RAM (random Access memory) in chip into flash storage in chip |
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| US5778440A (en) * | 1994-10-26 | 1998-07-07 | Macronix International Co., Ltd. | Floating gate memory device and method for terminating a program load cycle upon detecting a predetermined address/data pattern |
| CN1362708A (en) * | 2001-01-02 | 2002-08-07 | 吴秀林 | Read-write method for flash memory chip |
| CN1873619A (en) * | 2005-05-30 | 2006-12-06 | 株式会社东芝 | Memory device |
| CN101064192A (en) * | 2007-06-15 | 2007-10-31 | 华为技术有限公司 | System and method for accessing not-and flash memory |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101477838B (en) * | 2008-12-31 | 2014-07-30 | 深圳市同洲电子股份有限公司 | Condition detection apparatus, system and electronic device for NAND flash memory body |
-
2008
- 2008-12-31 CN CN200810241769.7A patent/CN101477838B/en not_active Expired - Fee Related
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2009
- 2009-12-24 WO PCT/CN2009/075939 patent/WO2010075746A1/en active Application Filing
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5778440A (en) * | 1994-10-26 | 1998-07-07 | Macronix International Co., Ltd. | Floating gate memory device and method for terminating a program load cycle upon detecting a predetermined address/data pattern |
| CN1362708A (en) * | 2001-01-02 | 2002-08-07 | 吴秀林 | Read-write method for flash memory chip |
| CN1873619A (en) * | 2005-05-30 | 2006-12-06 | 株式会社东芝 | Memory device |
| CN101064192A (en) * | 2007-06-15 | 2007-10-31 | 华为技术有限公司 | System and method for accessing not-and flash memory |
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| WO2010075746A1 (en) | 2010-07-08 |
| CN101477838A (en) | 2009-07-08 |
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