CN104615554B - Memory module detection method, memorizer control circuit unit and storage device - Google Patents
Memory module detection method, memorizer control circuit unit and storage device Download PDFInfo
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- CN104615554B CN104615554B CN201310537831.8A CN201310537831A CN104615554B CN 104615554 B CN104615554 B CN 104615554B CN 201310537831 A CN201310537831 A CN 201310537831A CN 104615554 B CN104615554 B CN 104615554B
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Abstract
A method of detection reproducible nonvolatile memorizer module comprising：The output voltage of the write protection pin of memory interface is set as the first logic level, reading state is assigned and instructs and receive first state message.This method further includes：Whether the correspondence position data for judging first state message are the state for meeting corresponding first logic level；And if so, identification reproducible nonvolatile memorizer module has been connected to memory interface.
Description
Technical field
The invention relates to a kind of method for detecting reproducible nonvolatile memorizer module and use the method
Memorizer control circuit unit and memorizer memory devices.
Background technique
Since type nonvolatile (rewritable non-volatile memory) has data non-
Volatibility, power saving, it is small in size, without the characteristics such as mechanical structure, read or write speed be fast, therefore, duplicative non-volatile memories in recent years
Device industry becomes a ring quite popular in electronic industry.For example, the solid state hard disk using flash memory as storage media is answered extensively
It is used as the hard disk of main frame, to promote the access efficiency of computer.When user carries out suspend mode (sleep
When mode), host system can as shutdown interrupt storage storage device and buffer storage power supply.In addition, when making
When user is intended to be returned to normal operation from suspend mode, memorizer memory devices needs are reinitialized.For example, in general,
The memorizer control circuit unit of memorizer memory devices can be answered seriatim by each in enable memorizer memory devices
It writes formula non-volatile memory module and is operated according to response in the signal on the Ready/Busy pin of memory interface to detect
Whether it is smoothly connected to memorizer control circuit in each type nonvolatile in memorizer memory devices
The memory interface of unit.However, not being connected to memorizer control circuit unit smoothly in type nonvolatile
Memory interface example in, memorizer control circuit unit need to Ready/Busy pin in one section of preset time (that is,
Overtime) it just can confirm that type nonvolatile is not connected to storage smoothly when not responding ready state (for example, ' 0 ')
The memory interface of device control circuit unit, and issue error message.
Summary of the invention
The present invention provides a kind of method of detection reproducible nonvolatile memorizer module, memorizer control circuit unit
And memorizer memory devices, can rapidly determine type nonvolatile in memorizer memory devices is whether
Have been connected to memorizer control circuit unit.
Accordingly, an exemplary embodiment of the invention proposes a kind of method for detecting reproducible nonvolatile memorizer module,
For detecting reproducible nonvolatile memorizer module by memory interface by memorizer control circuit unit.This detection can
The method of manifolding formula non-volatile memory module includes：(a) by the write protection pin of the control bus of memory interface
Output voltage is set as the first logic level, assigns reading state instruction, and the number for passing through memory interface by control bus
First state message is received according to bus, wherein control bus and data/address bus are bus independent of each other.This detection duplicative
The method of non-volatile memory module further includes：(c) whether the correspondence position data for judging first state message are to meet correspondence
The state of first logic level；And if (d) the correspondence position data of first state message are to meet corresponding first logic level
State when, identify that above-mentioned reproducible nonvolatile memorizer module has been connected to memory interface.
In one example of the present invention embodiment, the method for above-mentioned detection reproducible nonvolatile memorizer module is also wrapped
It includes：(b) output voltage of the write protection pin of control bus is set as the second logic level, reading is assigned by control bus
Status command is taken, and the second status message is received by data/address bus；And (c) judge the correspondence position data of the second status message
It whether is the state for meeting corresponding second logic level, wherein only when the correspondence position data of first state message are to meet corresponding the
The state of one logic level and the correspondence position data of the second status message are that when meeting the state of corresponding second logic level, can answer
The formula non-volatile memory module of writing can just be identified and have been connected to memory interface.
In one example of the present invention embodiment, the method for above-mentioned detection reproducible nonvolatile memorizer module is also wrapped
It includes before executing above-mentioned steps (a), reset indication is assigned by control bus.
In one example of the present invention embodiment, the method for above-mentioned detection reproducible nonvolatile memorizer module is also wrapped
It includes before assigning above-mentioned reset indication by control bus, is believed by the chip enable pin transmission chip enable of control bus
Number.
In one example of the present invention embodiment, above-mentioned steps (a), above-mentioned steps (b) and above-mentioned steps (c) are above-mentioned
Memorizer control circuit unit is performed when powering on every time.
In one example of the present invention embodiment, the control bus of above-mentioned memory interface is not configured with Ready/Busy and connects
Foot.
An exemplary embodiment of the invention proposes a kind of memorizer control circuit unit comprising memory interface and memory
Manage circuit.Memory interface includes control bus and data/address bus, and wherein control bus includes write protection pin and controls
Bus processed and data/address bus are bus independent of each other.Memory management circuitry is electrically connected to memory interface, will write
Enter to protect the output voltage of pin to be set as the first logic level, reading state instruction is assigned by control bus, and pass through number
First state message is received according to bus.Furthermore correspondence position data of the memory management circuitry also to judge first state message
It whether is to meet the state of corresponding first logic level, and judge whether the correspondence position data of the second status message are to meet pair
Answer the state of the second logic level.If the correspondence position data of first state message are to meet the state of corresponding first logic level
When, memory management circuitry identification reproducible nonvolatile memorizer module has been connected to memory interface.
In one example of the present invention embodiment, memory management circuitry is also to by the write protection pin of control bus
Output voltage be set as the second logic level, by control bus assign reading state instruction, and by data/address bus reception
Second status message.Memory management circuitry is also to judge whether the correspondence position data of the second status message are to meet corresponding the
The state of two logic levels, wherein only when the correspondence position data of first state message are to meet the state of corresponding first logic level
And second the correspondence position data of status message be to meet the state of corresponding second logic level, memory management circuitry can just identify
Reproducible nonvolatile memorizer module has been connected to memory interface.
In one example of the present invention embodiment, above-mentioned memory management circuitry is also to assign resetting by control bus
Instruction.
In one example of the present invention embodiment, above-mentioned memory management circuitry is also to assign weight by control bus
Before setting instruction, pass through the chip enable pin transmission chip enable signal of control bus.
In one example of the present invention embodiment, the control bus of above-mentioned memory interface further includes that instruction latch enable connects
Foot, address latch enable pin and chip enable pin.
In one example of the present invention embodiment, the control bus of above-mentioned memory interface is not configured with Ready/Busy and connects
Foot.
An exemplary embodiment of the invention proposes a kind of memorizer memory devices comprising connecting interface unit, duplicative
Non-volatile memory module and memorizer control circuit unit.Connecting interface unit is electrically connected to host system.It can
Manifolding formula non-volatile memory module has multiple physical erase units.Memorizer control circuit unit is electrically connected to connection
Interface unit and reproducible nonvolatile memorizer module, and including memory interface.Memorizer control circuit unit is used
The output voltage of write protection pin is set as the first logic level, reading state instruction is assigned by control bus, and
First state message is received by data/address bus, wherein control bus and data/address bus are bus independent of each other.Furthermore it stores
Device control circuit unit is also to judge whether the correspondence position data of first state message are to meet corresponding first logic level
State.If the correspondence position data of first state message are memory control electricity when meeting the state of corresponding first logic level
Road unit identification reproducible nonvolatile memorizer module has been connected to memory interface.
In one example of the present invention embodiment, above-mentioned memorizer control circuit unit is also to by the write-in of control bus
The output voltage of protection pin is set as the second logic level, assigns reading state instruction by control bus, and pass through data
Bus receives the second status message.In addition, correspondence digit of the memorizer control circuit unit also to judge the second status message
According to whether being the state for meeting corresponding second logic level, wherein only when the correspondence position data of first state message are to meet correspondence
The state of first logic level and the correspondence position data of the second status message are to meet the state of corresponding second logic level, storage
Device control circuit unit can just identify that reproducible nonvolatile memorizer module has been connected to memory interface.
In one example of the present invention embodiment, above-mentioned memorizer control circuit unit by control bus also to be assigned
Reset indication.
In one example of the present invention embodiment, above-mentioned memorizer control circuit unit is also under through control bus
Up to before reset indication, pass through the chip enable pin transmission chip enable signal of control bus.
An exemplary embodiment of the invention proposes a kind of memorizer memory devices comprising connecting interface unit, duplicative
Non-volatile memory module and memorizer control circuit unit.Connecting interface unit is electrically connected to host system.It can
Manifolding formula non-volatile memory module has multiple physical erase units.Memorizer control circuit unit is electrically connected to connection
Interface unit and reproducible nonvolatile memorizer module, and connect including the memory with control bus and data/address bus
Mouthful.Control bus includes write protection pin, instructs latch enable pin, address latch enable pin and chip enable pin,
And write protection pin, instruction latch enable pin, address latch enable pin and chip enable pin respectively electrically connect
It is connected to reproducible nonvolatile memorizer module, wherein the control bus of memory interface is not configured with Ready/Busy pin.
Based on above-mentioned, the method for the detection reproducible nonvolatile memorizer module of above-mentioned exemplary embodiment, memory
Whether normally control circuit unit and memorizer memory devices can shorten detection reproducible nonvolatile memorizer module
It is connected the required time.
To make the foregoing features and advantages of the present invention clearer and more comprehensible, special embodiment below, and cooperate institute's accompanying drawings
It is described in detail below.
Detailed description of the invention
Fig. 1 is the host system according to depicted in an exemplary embodiment and memorizer memory devices.
Fig. 2 is computer, input/output device and memorizer memory devices depicted in exemplary embodiment according to the present invention
Schematic diagram.
Fig. 3 is the schematic diagram of host system and memorizer memory devices depicted in exemplary embodiment according to the present invention.
Fig. 4 is the schematic block diagram for being painted memorizer memory devices shown in FIG. 1.
Fig. 5 is the schematic block diagram of the memorizer control circuit unit according to depicted in an exemplary embodiment.
Fig. 6 is according to the present invention depicted in an exemplary embodiment for connect memorizer control circuit unit and can answer
Write the detailed block diagram of the memory interface of formula non-volatile memory module.
Fig. 7 is the stream of the method for detection reproducible nonvolatile memorizer module according to depicted in an exemplary embodiment
Cheng Tu.
[label declaration]
1000：Host system 1100：Computer
1102：Microprocessor 1104：Random access memory
1106：Input/output device 1108：System bus
1110：Data transmission interface 1202：Mouse
1204：Keyboard 1206：Display
1208：Printer 1212：Portable disk
1214：Storage card 1216：Solid state hard disk
1310：Digital camera 1312：SD card
1314：Mmc card 1316：Memory stick
1318：CF card 1320：Embedded storage device
100：Memorizer memory devices 102：Connecting interface unit
104：Memorizer control circuit unit 106：Reproducible nonvolatile memorizer module
202：Memory management circuitry 204：Host interface
206：Memory interface 208：Buffer storage
210：Electric power management circuit 212：Error checking and correcting circuit
410 (0)~410 (N)：Physical erase unit 602：Control bus
604：Data/address bus 604
612：Chip enable (chip enable, CE) pin
614：Instruct latch enable (command latch enable, CLE) pin
616：Address latch enable (address latch enable, ALE)
618：Write protection (write protect, WP) pin
620：Ready/Busy (Ready/Busy) pin
S701,S703,S705,S707,S709,S711,S713,S715,S717：Detect duplicative non-volatile memories
The step of method of device module
Specific embodiment
In general, memorizer memory devices (also known as, memory storage system) include duplicative non-volatile memories
Device module and controller (also known as, control circuit).Being commonly stored device storage device is used together with host system, so that host
System can write data into memorizer memory devices or read from memorizer memory devices data.
Fig. 1 is the host system according to depicted in an exemplary embodiment and memorizer memory devices.
Fig. 1 is please referred to, host system 1000 generally comprises computer 1100 and input/output (input/output, I/O)
Device 1106.Computer 1100 includes microprocessor 1102, random access memory (random access memory, RAM)
1104, system bus 1108 and data transmission interface 1110.Input/output device 1106 includes mouse 1202, the keyboard such as Fig. 2
1204, display 1206 and printer 1208.It will be appreciated that the unrestricted input/output device of device shown in Fig. 2
1106, input/output device 1106 can further include other devices.
In embodiments of the present invention, memorizer memory devices 100 are by data transmission interface 1110 and host system
1000 other elements are electrically connected.By microprocessor 1102, random access memory 1104 and input/output device 1106
Running can write data into memorizer memory devices 100 or read data from memorizer memory devices 100.For example, depositing
Reservoir storage device 100 can be portable disk 1212 as shown in Figure 2, storage card 1214 or solid state hard disk (Solid State
Drive, SSD) 1216 equal type nonvolatile storage devices.
In general, host system 1000 is that can substantially cooperate with memorizer memory devices 100 to store appointing for data
Meaning system.Although host system 1000 is explained with computer system, however, in the present invention in this exemplary embodiment
Host system 1000 can be digital camera, video camera, communication device, audio player or video and broadcast in another exemplary embodiment
Put the systems such as device.For example, when host system is digital camera (video camera) 1310, type nonvolatile storage
Device is then its used SD card 1312, mmc card 1314, memory stick (memory stick) 1316, CF card 1318 or insertion
Formula storage device 1320 (as shown in Figure 3).Embedded storage device 1320 include embedded multi-media card (Embedded MMC,
eMMC).It is noted that embedded multi-media card is directly electrically connected on the substrate of host system.
Fig. 4 is the schematic block diagram for being painted memorizer memory devices shown in FIG. 1.
Referring to figure 4., memorizer memory devices 100 include connecting interface unit 102, memorizer control circuit unit 104
With reproducible nonvolatile memorizer module 106.
In this exemplary embodiment, connecting interface unit 102 is compatible with the advanced attachment (SerialAdvanced of sequence
Technology Attachment, SATA) standard.However, it is necessary to be appreciated that, the invention is not limited thereto, connecting interface unit
102 can also meet advanced attachment (Parellel Advanced Technology Attachment, PATA) mark side by side
Quasi-, Institute of Electrical and Electric Engineers (Institute of Electrical and Electronic Engineers,
IEEE) 1394 standards, high-speed peripheral component connecting interface (Peripheral Component Interconnect Express,
PCI Express) standard, universal serial bus (Universal Serial Bus, USB) standard, a ultrahigh speed generation (Ultra
High Speed-I, UHS-I) interface standard, two generation of ultrahigh speed (Ultra High Speed-II, UHS-II) interface standard, peace
Digital (Secure Digital, SD) interface standard, memory stick (Memory Stick, MS) interface standard, multimedia memory
Block (Multi Media Card, MMC) interface standard, compact flash (Compact Flash, CF) interface standard, integrated form to drive
Dynamic electrical interface (Integrated Device Electronics, IDE) standard or other suitable standard.In this example reality
It applies in example, connecting interface unit can be encapsulated in a chip with memorizer control circuit unit, or is laid in one and is included storage
Outside the chip of device control circuit unit.
Memorizer control circuit unit 104 is to execute multiple logic gates or control with hardware pattern or firmware pattern implementation
System instruction, and data are carried out in reproducible nonvolatile memorizer module 106 according to the instruction of host system 1000
The running such as be written, read and erase.
Reproducible nonvolatile memorizer module 106 is electrically connected to memorizer control circuit unit 104, and uses
To store the data that host system 1000 is written.Reproducible nonvolatile memorizer module 106 has physical erase unit
410 (0)~410 (N).For example, physical erase unit 410 (0)~410 (N) can belong to the same memory crystal grain (die) or
Belong to different memory crystal grains.Each physical erase unit is respectively provided with multiple physical programming units, wherein belonging to same
The physical programming unit of physical erase unit can be written independently and simultaneously be erased.However, it is necessary to be appreciated that, this hair
Bright without being limited thereto, each physical erase unit is can be by 64 physical programming units, 256 physical programming units or other any
A physical programming unit is formed.
In more detail, physical erase unit is the minimum unit erased.Also that is, each physical erase unit contains minimum
The storage unit of number being erased together.Physical programming unit is the minimum unit of programming.That is, physical programming unit is write-in
The minimum unit of data.Each physical programming unit generally includes data bit area and redundant digit area.Data bit area includes multiple objects
Manage data of the access address to store user, and redundant digit area to stocking system data (for example, control information and wrong
Accidentally more code).In this exemplary embodiment, 4 physics access ground can be included in the data bit area of each physical programming unit
Location, and the size of a physics access address is 512 bytes (byte).However, in other exemplary embodiments, in data bit area
It also may include the more or fewer physics access addresses of number, the present invention is not intended to limit the size of physics access address and a
Number.For example, in an exemplary embodiment, physical erase unit is physical blocks, and physical programming unit be physical page or
Physical sector, but invention is not limited thereto.
In this exemplary embodiment, reproducible nonvolatile memorizer module 106 is multi-level cell memory (Multi
Level Cell, MLC) NAND-type flash memory module (that is, flash memory module that 2 bit datas can be stored in a storage unit).So
And the invention is not limited thereto, reproducible nonvolatile memorizer module 106 also can be single-order storage unit (Single
Level Cell, SLC) it is NAND-type flash memory module (that is, flash memory module that 1 bit data can be stored in a storage unit), more
Rank storage unit (Trinary Level Cell, TLC) NAND-type flash memory module is (that is, can store 3 positions in a storage unit
The flash memory module of data), other flash memory modules or other memory modules with the same characteristics.
Fig. 5 is the schematic block diagram of the memorizer control circuit unit according to depicted in an exemplary embodiment.
Referring to figure 5., memorizer control circuit unit 104 includes memory management circuitry 202, host interface 204 and deposits
Memory interface 206.
Overall operation of the memory management circuitry 202 to control memorizer control circuit unit 104.Specifically, it deposits
Reservoir, which manages circuit 202, has multiple control instructions, and when memorizer memory devices 100 operate, these control instruction meetings
It is performed the running such as to carry out the write-in of data, read and erase.
In this exemplary embodiment, the control instruction of memory management circuitry 202 is to carry out implementation with firmware pattern.For example,
Memory management circuitry 202 has microprocessor unit (not being painted) and read-only memory (not being painted), and these controls refer to
Order is programmed in so far read-only memory.When memorizer memory devices 100 operate, these control instructions can be by microprocessor
Unit is executed the running such as to carry out the write-in of data, read and erase.
In another exemplary embodiment of the present invention, the control instruction of memory management circuitry 202 also can be with procedure code pattern
The specific region of reproducible nonvolatile memorizer module 106 is stored in (for example, being exclusively used in storage system in memory module
The system area of data) in.In addition, memory management circuitry 202 has microprocessor unit (not being painted), read-only memory (not
It is painted) and random access memory (not being painted).In particular, this read-only memory has driving code, and when memory controls
When circuit unit 104 is enabled, microprocessor unit can first carry out this driving code section, and will to be stored in duplicative non-volatile
Control instruction in memory module 106 is loaded onto the random access memory of memory management circuitry 202.Later, micro- place
Reason device unit such as can operate these control instructions to carry out the write-in of data, read and erase at the running.
In addition, the control instruction of memory management circuitry 202 can also a hardware in another exemplary embodiment of the present invention
Pattern carrys out implementation.For example, memory management circuitry 202 includes microcontroller, Storage Unit Management circuit, memory write-in electricity
Road, memory reading circuitry, memory are erased circuit and data processing circuit.Storage Unit Management circuit, memory write-in electricity
Circuit is erased on road, memory reading circuitry, memory and data processing circuit is electrically connected to microcontroller.Wherein, it stores
Physical erase unit of the Single Component Management circuit to manage reproducible nonvolatile memorizer module 106；Memory write-in electricity
Road writes data into non-volatile to duplicative to assign write instruction to reproducible nonvolatile memorizer module 106
In property memory module 106；Memory reading circuitry refers to assign reading to reproducible nonvolatile memorizer module 106
It enables to read data from reproducible nonvolatile memorizer module 106；Memory erases circuit to non-to duplicative
Volatile 106 assigns instruction of erasing so that data to be erased from reproducible nonvolatile memorizer module 106；
And data processing circuit is intended to be written data to reproducible nonvolatile memorizer module 106 and from can make carbon copies to handle
The data read in formula non-volatile memory module 106.
Host interface 204 is electrically connected to memory management circuitry 202 and to receive and identification host system
1000 instructions and data transmitted.That is, instruction and data that host system 1000 is transmitted can pass through host interface
204 are sent to memory management circuitry 202.In this exemplary embodiment, host interface 204 is compatible with SATA standard.So
And, it should be understood that the invention is not limited thereto, host interface 204 can also be compatible with PATA standard, IEEE1394 standard,
PCI Express standard, USB standard, UHS-I interface standard, UHS-II interface standard, SD standard, MS standard, MMC standard, CF
Standard, IDE standard or other suitable data transmission standard.
Memory interface 206 is electrically connected to memory management circuitry 202 and non-volatile to access duplicative
Property memory module 106.That is, the data for being intended to be written to reproducible nonvolatile memorizer module 106 can be via depositing
Memory interface 206 is converted to the 106 receptible format of institute of reproducible nonvolatile memorizer module.
In an exemplary embodiment of the invention, memorizer control circuit unit 104 further includes buffer storage 208, power supply
Manage circuit 210 and error checking and correcting circuit 212.
Buffer storage 208 is electrically connected to memory management circuitry 202 and is configured to temporarily store from host system
1000 data and instruction or the data from reproducible nonvolatile memorizer module 106.
Electric power management circuit 210 is electrically connected to memory management circuitry 202 and to control memory storage dress
Set 100 power supply.
Error checking and correcting circuit 212 are electrically connected to memory management circuitry 202 and to execute wrong inspection
It looks into and correction program is to ensure the correctness of data.Specifically, when memory management circuitry 202 connects from host system 1000
When receiving write instruction, error checking can generate corresponding mistake with correcting circuit 212 for the data of this corresponding write instruction and examine
It looks into and correcting code (Error Checking and Correcting Code, ECC Code), and memory management circuitry 202
The data of this corresponding write instruction can be written with corresponding error checking and correcting code to type nonvolatile
In module 106.Later, when data are read from reproducible nonvolatile memorizer module 106 when memory management circuitry 202
The corresponding error checking of this data and correcting code can be read simultaneously, and error checking and correcting circuit 212 can be according to this mistakes
It checks and correcting code executes error checking and correction program to read data.
Fig. 6 is according to the present invention depicted in an exemplary embodiment for connect memorizer control circuit unit and can answer
Write the detailed block diagram of the memory interface of formula non-volatile memory module.
Fig. 6 is please referred to, memory interface 206 includes control bus 602 and data/address bus 604.Also, control bus 602
It is connect including chip enable (chip enable, CE) pin 612, instruction latch enable (command latch enable, CLE)
Foot 614, address latch enable (address latch enable, ALE) 616,
Write protection (write protect, WP) pin 618 and Ready/Busy (Ready/Busy) pin 620.
Memorizer control circuit unit 104 (or memory management circuitry 202) assigns control instruction via control bus 602
Type nonvolatile is obtained to reproducible nonvolatile memorizer module 106 and by control bus 602
The state of module 106.In addition, memorizer control circuit unit 104 (or memory management circuitry 202) is via data/address bus 604
Transfer data to reproducible nonvolatile memorizer module 106 or from reproducible nonvolatile memorizer module 106
Receive data.Base this, by control bus 602 and data/address bus 604, (or the memory management of memorizer control circuit unit 104
Circuit 202) (reset) running, write-in (write) fortune can be reset to reproducible nonvolatile memorizer module 106
Make, read (read) running, (erase) running etc. of erasing.
In this exemplary embodiment, when memorizer memory devices 100 power on, memorizer control circuit unit 104 (or deposit
Reservoir manages circuit 202) it can be by 612 transmission chip enable signal of chip enable pin to type nonvolatile
Module 106 and by instruction latch enable pin 614 send reset indication to reproducible nonvolatile memorizer module
106.In particular, after resetting reproducible nonvolatile memorizer module 106, memorizer control circuit unit 104 (or deposit
Reservoir manages circuit 202) output voltage of write protection pin 618 can be set as the first logic level.For example, in this example
In embodiment, the first logic level is a logic high potential.
Then, memorizer control circuit unit 104 (or memory management circuitry 202) can be by instructing latch enable pin
614 send reading state instruction (read status command) and receive this reading state of response by data/address bus 604
The first state message of instruction.Also, memorizer control circuit unit 104 (or memory management circuitry 202) judges first
Corresponded in status message write protection pin 618 position data (for example, in first state message the 8th bit data (that is,
' bit7 ') it whether is state when the output voltage of corresponding write protection pin 618 is set to the first logic level.For example,
In the example that the first logic level is logic high potential, the output voltage of corresponding write protection pin 618 is set to first
State when logic level is ' 0 '.If the position data for corresponding to write protection pin 618 in first state message are non-for corresponding write-in
When state when the output voltage of protection pin is set to the first logic level, memorizer control circuit unit 104 (or storage
Device manages circuit 202) it can determine that reproducible nonvolatile memorizer module 106 is not connected to memory interface 206.
If the position data for corresponding to write protection pin 618 in first state message are the output electricity of corresponding write protection pin
When pressing state when being set to the first logic level, memorizer control circuit unit 104 (or memory management circuitry 202) meeting
The output voltage of write protection pin 618 is set as the second logic level again.For example, second patrols in this exemplary embodiment
Collecting current potential is a logic low potential.
Then, memorizer control circuit unit 104 (or memory management circuitry 202) can be by instructing latch enable pin
614, which send reading state, instructs and receives the second status message for responding the instruction of this reading state by data/address bus 604.And
And memorizer control circuit unit 104 (or memory management circuitry 202) judges in the second status message and corresponds to write protection
The position data of pin 618 are (for example, whether the 8th bit data (that is, ' bit7 ') in the second status message is corresponding write protection
The output voltage of pin 618 is set to state when the second logic level.For example, being logic high potential in the second logic level
Example in, the state when output voltage of corresponding write protection pin 618 is set to the second logic level is ' 1 '.If the
The non-output voltage for corresponding write protection pin 618 of position data that write protection pin 618 is corresponded in two-state message is set
When state when being set to the second logic level, memorizer control circuit unit 104 (or memory management circuitry 202) can determine can
Manifolding formula non-volatile memory module 106 is not connected to memory interface 206.
If the position data for corresponding to write protection pin 618 in first state message are the defeated of corresponding write protection pin 618
The position data of write protection pin 618 are corresponded in state and the second status message when voltage is set to the first logic level out
When state when being set to the second logic level for the output voltage of corresponding write protection pin 618, memorizer control circuit
Unit 104 (or memory management circuitry 202) can determine that reproducible nonvolatile memorizer module 106 has been connected to memory
Interface 206.
In this exemplary embodiment, determine to answer in the state by the logic level for responding write protection pin 618
Formula non-volatile memory module 106 is write to be not connected to after memory interface 206, memorizer control circuit unit 104 (or deposit
Reservoir manages circuit 202) just capable of emitting error message connect from Ready/Busy without lasting wait to host system 100
The signal of foot 620.
It will be appreciated that although being to detect a type nonvolatile in this exemplary embodiment
Module 106 explains, however, the present invention is not limited thereto.For example, with multiple reproducible nonvolatile memorizer modules
In memorizer memory devices, memorizer control circuit unit (or memory management circuitry) can synchronously to be connected to these can
The multiple groups control bus and data/address bus of manifolding formula non-volatile memory module execute the running of above-mentioned detection and judgement.Especially
It is herein in the memorizer memory devices example with multiple reproducible nonvolatile memorizer modules, to pass through each control
The write protection pin of bus can confirm more quickly each reproducible nonvolatile memorizer module whether successfully by
It is connected to memorizer control circuit unit.
In addition, it is noted that although Ready/Busy pin 620 still can be transported normally in this exemplary embodiment
Make, and memorizer control circuit unit 104 (or memory management circuitry 202) can pass through the letter in Ready/Busy pin 620
Number know reproducible nonvolatile memorizer module 106 whether in idle or busy.However, real in another example of the present invention
It applies in example, control bus 602 can also be not configured with Ready/Busy pin 620.Specifically, on memorizer memory devices 100
When electric, memorizer control circuit unit 104 (or memory management circuitry 202) can patrolling by response write protection pin 618
It collects the state of current potential and determines whether reproducible nonvolatile memorizer module 106 is connected to memory interface 206.Then,
In 106 operation process of reproducible nonvolatile memorizer module, memorizer control circuit unit 104 (or memory management
Circuit 202) reading state instruction can be sent by instruction latch enable pin 614, response is received by data/address bus 604 and is read
The status message of status command and reproducible nonvolatile memorizer module is judged according to the position data in status message
106 be in idle or busy.Therefore, Ready/Busy pin 620 can also be not required to configuration and be connected to memorizer control circuit list
Between member 104 and reproducible nonvolatile memorizer module 106.
Fig. 7 is the stream of the method for detection reproducible nonvolatile memorizer module according to depicted in an exemplary embodiment
Cheng Tu.
Fig. 7 is please referred to, when memorizer memory devices 100 power on, in step s 701, memorizer control circuit unit
104 (or memory management circuitries 202) by 612 transmission chip enable signal of chip enable pin and can pass through control bus
602 (for example, instruction latch enable pins 614) send reset indication.
Later, in step S703, memorizer control circuit unit 104 (or memory management circuitry 202) can will be stored
The output voltage of the write protection pin 618 of the control bus 602 of device interface 206 is set as the first logic level.
Then, in step S705, memorizer control circuit unit 104 (or memory management circuitry 202) can pass through control
Bus 602 processed assigns reading state instruction, and the first state message for responding this reading state is received by data/address bus 604.
Also, in step S707, memorizer control circuit unit 104 (or memory management circuitry 202) judges first state and disappears
Whether the correspondence position data of breath are the state for meeting the first logic level.Specifically, as described above, response reading state instruction
Status message in the 8th bit data (that is, bit7) be corresponding write protection pin 618 state, and memory control
Circuit unit 104 (or memory management circuitry 202) understands the value of this data to determine whether and response setting to write protection
The state of first logic level of pin 618 is consistent.
If the non-correspondence position data of first state message are when meeting the state of the first logic level, in step S709
In, memorizer control circuit unit 104 (or memory management circuitry 202) can determine reproducible nonvolatile memorizer module
106 are not connected to memorizer control circuit unit 104 and output error message.
If the correspondence position data of first state message are when meeting the state of the first logic level, in step S711,
Memorizer control circuit unit 104 (or memory management circuitry 202) can writing the control bus 602 of memory interface 206
Enter to protect the output voltage of pin 618 to be set as the second logic level.
Then, in step S713, memorizer control circuit unit 104 (or memory management circuitry 202) can pass through control
Bus 602 processed assigns reading state instruction, and the second status message for responding this reading state is received by data/address bus 604.
Also, in step S715, memorizer control circuit unit 104 (or memory management circuitry 202) judges the second state and disappears
Whether the correspondence position data of breath are the state for meeting the second logic level.
If the non-correspondence position data of the second status message are then step S709 meeting when meeting the state of the second logic level
It is performed.Conversely, memorizer control circuit unit 104 (or memory management circuitry 202) can determine answer in step S717
It writes formula non-volatile memory module 106 and has been connected to memorizer control circuit unit 104.For example, being deposited after step S717
Memory control circuit unit 104 (or memory management circuitry 202) can be according to reproducible nonvolatile memorizer module 106
State executes initialization running.
It will be appreciated that although in this exemplary embodiment, memorizer control circuit unit 104 (or memory management
Circuit 202) it can determine that at the same time the correspondence position data of first state message are to meet the first logic level state and the second shape
Whether the correspondence position data of state message are just to identify type nonvolatile in the state of meeting the second logic level
Module 106 has been connected to memorizer control circuit unit 104.However, the invention is not limited thereto, implement in another example of the present invention
In example, memorizer control circuit unit 104 (or memory management circuitry 202) also can be in the correspondence position data of first state message
In the state of meeting the first logic level, decide that reproducible nonvolatile memorizer module 106 has been connected to memory
Control circuit unit 104.That is, above-mentioned steps S713 and S715 can be omitted.
In conclusion the method for the detection reproducible nonvolatile memorizer module of exemplary embodiment of the present invention, storage
Device control circuit unit and memorizer memory devices are by the output voltage of setting write protection pin and according to reading shape
State confirms whether reproducible nonvolatile memorizer module is normally connected, non-thus, it is possible to shorten detection duplicative
Time needed for volatile.
Claims (18)
1. a kind of method for detecting reproducible nonvolatile memorizer module, for being passed through by a memorizer control circuit unit
One memory interface detects a reproducible nonvolatile memorizer module, the detection reproducible nonvolatile memorizer module
Method include：
(a) by the memorizer control circuit unit by the output of a write protection pin of a control bus of the memory interface
Voltage is set as one first logic level, assigns a reading state by the control bus by the memorizer control circuit unit and refers to
It enables, one first state message is received by a data/address bus of the memory interface by the memorizer control circuit unit, by this
Whether the corresponding data of the one of the memorizer control circuit unit judges first state message are to meet corresponding first logic electricity
The state of position, wherein the control bus and the data/address bus are bus independent of each other；
If (b) the correspondence position data of the first state message are to meet the state of corresponding first logic level, by the storage
The output voltage of the write protection pin of the control bus is set as one second logic level by device control circuit unit, by
The memorizer control circuit unit assigns reading state instruction by the control bus, is led to by the memorizer control circuit unit
It crosses the data/address bus and receives one second status message, and being somebody's turn to do by memorizer control circuit unit judges second status message
Whether corresponding position data are the state for meeting corresponding second logic level；And
If (c) the correspondence position data of second status message are when meeting the state of corresponding second logic level, to be deposited by this
Memory control circuit unit identifies that the reproducible nonvolatile memorizer module has been connected to the memory interface.
2. the method for detection reproducible nonvolatile memorizer module according to claim 1, wherein first logic
Current potential is a logic high potential, and second logic level is a logic low potential.
3. the method for detection reproducible nonvolatile memorizer module according to claim 1, further includes：
Before executing above-mentioned steps (a), one reset indication is assigned by the control bus by the memorizer control circuit unit.
4. the method for detection reproducible nonvolatile memorizer module according to claim 3, further includes：
Before assigning the reset indication by the control bus, which is passed through by the memorizer control circuit unit
One chip enable pin sends a chip enable signal.
5. the method for detection reproducible nonvolatile memorizer module according to claim 1, wherein above-mentioned steps
(a), above-mentioned steps (b) with above-mentioned steps (c) are performed when the memorizer control circuit unit powers on every time.
6. the method for detection reproducible nonvolatile memorizer module according to claim 1, wherein the memory is connect
The control bus of mouth is not configured with a Ready/Busy pin.
7. a kind of memorizer control circuit, including：
One memory interface, including a control bus and a data/address bus, wherein the control bus includes a write protection pin
And the control bus and the data/address bus are bus independent of each other；And
One memory management circuitry is electrically connected to the memory interface, to set the output voltage of the write protection pin
It is set to one first logic level, reading state instruction is assigned by the control bus, receives one first by the data/address bus
Status message judges whether a corresponding data of the first state message are the state for meeting corresponding first logic level,
If wherein the correspondence position data of the first state message are to meet the state of corresponding first logic level, the memory
Management circuit also the output voltage of the write protection pin of the control bus is set as one second logic level, leads to
Cross the control bus assign the reading state instruction, by the data/address bus receive one second status message, and judge this second
Whether the correspondence position data of status message are the state for meeting corresponding second logic level,
If wherein the correspondence position data of second status message are storage when meeting the state of corresponding second logic level
Device management circuit identifies that a reproducible nonvolatile memorizer module has been connected to the memory interface.
8. memorizer control circuit according to claim 7, wherein first logic level is a logic high potential, and should
Second logic level is a logic low potential.
9. memorizer control circuit according to claim 7, wherein the memory management circuitry is also to pass through the control
Bus assigns a reset indication.
10. memorizer control circuit according to claim 9, wherein the memory management circuitry is also to pass through the control
Before bus processed assigns the reset indication, a chip enable signal is sent by a chip enable pin of the control bus.
11. memorizer control circuit according to claim 7, wherein the control bus of the memory interface further includes one
Instruct latch enable pin, an address latch enable pin and a chip enable pin.
12. memorizer control circuit according to claim 11, wherein the control bus of the memory interface is not configured
There is a Ready/Busy pin.
13. a kind of memorizer memory devices, including：
One connecting interface unit, is electrically connected to a host system；
One reproducible nonvolatile memorizer module has multiple physical erase units；And
One memorizer control circuit unit is electrically connected to the connecting interface unit and the type nonvolatile mould
Block, and including a memory interface,
Wherein the memorizer control circuit unit is to by a write protection pin of a control bus of the memory interface
Output voltage is set as one first logic level, assigns reading state instruction by the control bus, is connect by the memory
Mouthful a data/address bus receive a first state message, judge whether a corresponding data of the first state message are to meet pair
Should the first logic level state, wherein the control bus and the data/address bus are bus independent of each other,
If wherein the correspondence position data of the first state message are to meet the state of corresponding first logic level, the memory
Control circuit unit is also to judge whether the correspondence position data of one second status message are to meet corresponding one second logic electricity
The state of position,
If wherein the correspondence position data of second status message are storage when meeting the state of corresponding second logic level
Device control circuit unit identifies that the reproducible nonvolatile memorizer module has been connected to the memory interface.
14. memorizer memory devices according to claim 13, wherein first logic level is a logic high potential, and
Second logic level is a logic low potential.
15. memorizer memory devices according to claim 13, wherein the memorizer control circuit unit is also to pass through
The control bus assigns a reset indication.
16. memorizer memory devices according to claim 15, wherein the memorizer control circuit unit is also to logical
It crosses before the control bus assigns the reset indication, the chip enable pin for passing through the control bus sends chip enable letter
Number.
17. memorizer memory devices according to claim 13, wherein the control bus of the memory interface further includes
One instruction latch enable pin, an address latch enable pin and a chip enable pin.
18. memorizer memory devices according to claim 17, wherein the control bus of the memory interface is not configured
There is a Ready/Busy pin.
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| CN101295285A (en) * | 2007-04-25 | 2008-10-29 | 群联电子股份有限公司 | Integrated data processing system, flash memory system and flash memory controller |
| CN101477838A (en) * | 2008-12-31 | 2009-07-08 | 深圳市同洲电子股份有限公司 | Condition detection apparatus, system and electronic device for NAND flash memory body |
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| CN101295285A (en) * | 2007-04-25 | 2008-10-29 | 群联电子股份有限公司 | Integrated data processing system, flash memory system and flash memory controller |
| CN101740105A (en) * | 2008-11-24 | 2010-06-16 | 联发科技股份有限公司 | System and method for accessing memory card |
| CN101477838A (en) * | 2008-12-31 | 2009-07-08 | 深圳市同洲电子股份有限公司 | Condition detection apparatus, system and electronic device for NAND flash memory body |
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