CN101465375A - MOS device with schottky barrier controlling layer - Google Patents
MOS device with schottky barrier controlling layer Download PDFInfo
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- CN101465375A CN101465375A CNA2008101823208A CN200810182320A CN101465375A CN 101465375 A CN101465375 A CN 101465375A CN A2008101823208 A CNA2008101823208 A CN A2008101823208A CN 200810182320 A CN200810182320 A CN 200810182320A CN 101465375 A CN101465375 A CN 101465375A
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Abstract
The invention relates to a MOS device with Schottky barrier control layer. Provided is a semiconductor device formed on a semiconductor substrate, which comprises: a drain, an epitaxial layer overlaying the drain and an active region; the active region comprises: a body which is disposed in the epitaxial layer, and has a body top surface, a source which is embedded in the body and extends from the body top surface into the body, a gate trench extending into the epitaxial layer, a gate disposed in the gate trench, an active region contact trench extending to the drain through the source and the body, an active region contact electrode disposed within the active region contact trench and forming Schottky diode with the drain, and a Schottky barrier control layer disposed in the epitaxial layer adjacent to the active region contact trench.
Description
The cross reference of related application
The application is submission on September 11st, 2007, common unsettled U.S. Patent application No.11/900,616, name is called the part continuation application of POWER MOS DEVICE, also be on February 11st, 2005 submitted to, U.S. Patent application No.11/056,346 (the present patent No. is 7,285,822), name is called the continuation application of POWER MOS DEVICE, for all purposes, above-mentioned two documents are incorporated herein.
Technical field
The present invention relates to metal-oxide semiconductor (MOS) (MOS) device and manufacture method thereof.
Background technology
Power MOS (Metal Oxide Semiconductor) device uses in electronic circuit usually.Depend on application, may expect different device properties.An exemplary application is the DC-DC transducer, it comprise a power MOS (Metal Oxide Semiconductor) device as synchronous rectifier (being also referred to as low side FET) and another power MOS (Metal Oxide Semiconductor) device as control switch (being also referred to as high-end FET).Low side FET requires less conducting resistance usually, so that obtain power switch efficient preferably.High-end FET requires less grid capacitance usually, to obtain high-speed switch and superperformance.
Transistorized conducting resistance (R
Dson) value is directly proportional with channel length (L) usually, be inversely proportional to active cell quantity on the per unit area (W).When selecting R
DsonValue the time, should consider the balance between performance and the puncture voltage.In order to reduce R
DsonValue, can reduce channel length by using more shallow source electrode and body, and can be by reducing the element number that cell size increases per unit area.Yet because punch-through, channel length L is restricted usually.The element number of per unit area also is restricted owing to manufacturing technology and owing to the source area that need make the unit well contacts with this tagma.Along with the increase of channel length and cell density, grid capacitance also increases.In order to reduce the loss of switch, lower device capacitor is preferred.In some application (such as, synchronous rectification), the forward voltage drop of charge stored and body diode also can cause efficiency losses.These factors have just limited the performance of DMOS power device together.
What expected is: if the conducting resistance of DMOS power device and grid capacitance can be lower than the current level that reaches, the reliability of power switch and power consumption all can be improved.What also come in handy is: develop practical technology, this technology can produce improved DMOS power device reliably.
Summary of the invention
For this reason, the invention provides a kind of semiconductor device and manufacture method thereof, feasible reliability and the power consumption of improving power switch.
In one aspect, the invention provides a kind of semiconductor device that is formed on the Semiconductor substrate, comprising: drain electrode; Cover the epitaxial loayer of described drain electrode; And active area, comprising: body, described body places described epitaxial loayer, and has the body top surface; Source electrode, described source electrode is embedded in the described body, and extends to the described body from described body top surface; Gate trench, described gate trench extend in the described epitaxial loayer; Grid, described grid places described gate trench; Active region contact trench, described active region contact trench extends in the described drain electrode by described source electrode and described body; And the active area contact electrode, described active area contact electrode places in the described active region contact trench, and wherein said active area contact electrode and described drain electrode form Schottky diode; And schottky barrier controlling layer, described schottky barrier controlling layer places the described epitaxial loayer contiguous with described active region contact trench.
In another aspect, the invention provides a kind of method of making semiconductor device, comprising: in the epitaxial loayer that covers Semiconductor substrate, form gate trench; Deposition of gate material in described gate trench; Form body; Form source electrode; Form active region contact trench, described active region contact trench extends in the described drain electrode by described source electrode and described body; The deposition schottky barrier controlling layer; And in described active region contact trench, arrange contact electrode.
Description of drawings
The following specifically describes with accompanying drawing in various embodiment of the present invention is disclosed.
Figure 1A-1F shows the embodiment of some double-diffused metal oxide semiconductors (DMOS) device.
Fig. 2 shows the schematic diagram of step-down (buck) converter circuit example.
Fig. 3 shows the flow chart of the embodiment of the manufacturing process that is used to construct the DMOS device.
Fig. 4 A-4U is the device viewgraph of cross-section that has specifically illustrated the exemplary manufacturing process that is used to make the MOS device.
Fig. 5 A-6B shows the additional optional embodiment of manufacturing step.
Fig. 7-10 shows the optional improvement of manufacturing process, and wherein these improvement are used in certain embodiments with further enhance device performance.
Embodiment
The present invention can realize with multiple mode, comprise the combination that is embodied as technology, device, system, thing, computer-readable medium (such as, computer-readable recording medium) or computer network (wherein, program command is sent by optical link or communication link).In this manual, these realize, perhaps the present invention's any other form that can adopt can be called technology.Be described as " assembly that is configured to execute the task " (such as processor or memory) and both comprised that general purpose module (it is to execute the task in preset time by provisional configuration) also comprised personal module (it is manufactured to execute the task).Usually, within the scope of the present invention, the order of disclosed processing step can change.
The specific descriptions of one or more embodiment of the present invention provide with the accompanying drawing that shows the principle of the invention following.Though described the present invention in conjunction with such embodiment, the present invention is not limited to any embodiment.Scope of the present invention is only limited by claim, and multiple alternative, improvement and equivalent have been contained in the present invention.Providing multiple concrete details in the following description is for complete understanding of the present invention is provided.The purpose that these details are in example provides, and the present invention can realize according to claim, and need not some of these details or all.For purpose clearly, the technique known material is not described in detail in relating to technical field of the present invention, is unnecessarily obscured to avoid the present invention.
Metal-oxide semiconductor (MOS) (MOS) device and manufacturing thereof are described.For exemplary purposes, go through the N channel device in this manual, it has the body that source electrode that n type material makes and drain electrode and P-type material are made.Technology disclosed herein and structure also are applicable to P-channel device.
Figure 1A-1F shows the embodiment of some double-diffused metal oxide semiconductors (DMOS) device.Figure 1A is the viewgraph of cross-section of the embodiment of DMOS device.In this example, device 100 comprises drain electrode, and it is formed on N
+The back side of N-type semiconductor N substrate 103.The drain region extend to covered substrate 103, N
-In the extension of N-type semiconductor N (epi) layer 104.In epitaxial loayer 104, etch gate trench (such as 111,113 and 115).Gate oxide level 121 is formed in the gate trench.Grid 131,133 and 135 is arranged in gate trench 111,113 and 115, and insulate with epitaxial loayer by oxide skin(coating).Grid is by making such as the electric conducting material of polysilicon (poly), and oxide skin(coating) is to be made by the insulating material such as thermal oxide.Particularly, gate trench 111 is arranged in termination area, and this termination area is furnished with the grid lead (gate runner) 131 that is used for being connected to the grid contacting metal.For this purpose, compare with 115 with active gate trench 113, grid lead groove 111 can be wideer and darker.Further, the spacing between the active groove that grid lead groove 111 is adjacent with it (being groove 113 in the case) can be bigger than the spacing between active gate trench 113 and 115.
Source area 150a-150d embeds respectively among the 140a-140d of this tagma.Source area extends downwardly into the body itself from the top surface of body.Although this tagma is injected into along the sidepiece of all gate trenchs, source area only is injected at contiguous active gate trench place, and is not injected at grid lead groove place.In the embodiment shown, the grid such as 133 has the grid top surface, and this grid top surface extends on embedding has the top surface of body of source electrode basically.Such configuration has guaranteed the overlapping of grid and source electrode, thereby allows source area more shallow than the source area of the device with recess gate, and such configuration has increased the efficient and the performance of device.The amount that the grid polycrystalline silicon top surface extends on source electrode-bulk junction can change at different embodiment.In certain embodiments, the grid of device does not extend on the top surface in source area/this tagma, but caves in from the top surface in source area/this tagma.
During operation, the effect of diode has been played in drain region and this tagma together, is called body diode.Dielectric materials layer 160 be arranged in grid above so that grid is contacted insulation with source electrode-body.Dielectric material is having formed insulation layer on the top of grid and on the top of this tagma and source area, such as 160a-160c.Suitable dielectric material comprises thermal oxide, low temperature oxide (LTO), boron-phosphorosilicate glass (BPSG) etc.
A large amount of contact trench 112a-112b is formed between near source area and this tagma the active gate trench.These grooves are called as active region contact trench, because the active area of these groove adjacent devices (being formed by source area and this tagma).For example, contact trench 112a extends through source electrode and body, has formed source area 150a-150b and this tagma 140a-140b of adjacent trenches.On the contrary, the groove 117 that is formed on grid lead 131 tops is not positioned near the active area, and therefore, groove 117 is not an active region contact trench.Groove 117 is called as grid contact trench or grid lead groove, is deposited in the groove because be connected to the metal level 172a of signal.By the interconnection in third dimension degree (not shown) between groove 111,113 and 115, signal is presented to active grid 133 and 135.Metal level 172a separates with metal level 172b, and metal level 172b is connected to source area and this tagma by contact trench 112a-112b, so that power supply to be provided.In the example shown, active region contact trench and grid contact trench have the substantially the same degree of depth.
Device 100 has active region contact trench 112a-112b, and they are all shallow than body.This configuration provides good breakdown performance, lower resistance and lower leakage current.In addition, because active contact trench and grid contact trench are to use a step process to form, they have the identical degree of depth thus, can avoid the grid contact trench to pass grid lead such as 131 so have the active contact trench more shallow than body.
In the example shown, the FET raceway groove forms along the active area gate trench sidewalls between source/body knot and the body/drain junction.In the device with short channel district, along with the increase of voltage between source electrode and the drain electrode, depletion region enlarges, and may finally arrive source junction.This phenomenon is called puncture, has limited the degree that raceway groove can be shortened.In certain embodiments, for fear of puncture, utilize P-type material to come such as carrying out heavy doping along the zone of the regional 170a-170d of active region contact trench wall to form P
+The type district.P
+The type district has avoided depletion region to occupy source area.Like this, these injections are sometimes referred to as to resist and wear injection or avoid puncturing injection.In certain embodiments, wear effect, P for the resistance that realizes claiming
+The district is near and/or as manufacturing alignment ability and P from channel region as much as possible
+It is near like that wall doping infiltration control is allowed.In certain embodiments, the misalignment between groove contact and the groove minimizes by autoregistration is carried out in contact, and the groove contact is placed as far as possible near the center between the groove.These structural enhancings allow raceway grooves to be shortened, and make net charge in the raceway groove per unit area suitably be lower than and avoid puncturing required lowest charge in desirable not protected structure.Except improving the body contact resistance, resist and to wear injection and also make and make up very that the short channel device of shallow trench becomes possibility.In the embodiment shown, contact trench 112a-112b is more shallow than this tagma 140a-140d, and can not extend in this tagma always.The conducting resistance R of device
DsonBe reduced with grid capacitance.
Arrange that in contact trench 112a-112b and gate trench 117 electric conducting material is to form contact electrode.In active area, owing to puncture to inject sidewall setting, and be not provided with, so contact electrode and N along the bottom of contact trench along contact trench
-Drain region 104 contacts.Contact electrode and drain region have formed Schottky diode (parallel with body diode) together.Schottky diode has reduced the body diode forward voltage drop and charge stored has been minimized, and makes MOSFET more efficient.Can be formed into N simultaneously
-The Schottky contacts of drain electrode and to P
+Body and N
+A kind of metal of the good Ohmic contact of source electrode is used to form electrode 180a-180b.Can use such as titanium (Ti), platinum (Pt), palladium (Pd), tungsten (W) or any other proper metal.In certain embodiments, metal level 172 is made by aluminium (Al) or by the Ti/TiN/Al lamination.
The leakage current of Schottky diode is relevant with schottky barrier height.Along with the increase of barrier height, leakage current reduces, and forward voltage drop also increases.In the example shown, inject thin alloy layer, optional schottky barrier controlling layer 190a-190b (being also referred to as Shannon (Shannon) layer) is formed under the contact electrode by bottom periphery at active area groove 112a-112b.In this example, alloy has the polarity opposite with epitaxial loayer, and belongs to the P type.Shannon injects superficial and is low dosage; Therefore, depleted fully and irrelevant with bias voltage.Schottky barrier controlling layer is used for controlling schottky barrier height, thereby allows leakage current is better controlled, and the reverse recovery characteristic that improves Schottky diode.The details that forms schottky barrier controlling layer is below described.
Figure 1B is the viewgraph of cross-section of another embodiment of DMOS device.Device 102 also comprises schottky barrier controlling layer 190a-190b, is positioned at the bottom periphery of active region contact trench.In this example, the degree of depth of grid contact trench 117 is different with the degree of depth of active region contact trench 112a-112b.Active region contact trench is darker than this tagma 140a-140d, and active region contact trench has extended beyond this tagma.Because active contact trench is darker,, and brought better non-clamp inductive switch (UIS) ability so active contact trench provides more multizone for making ohmic contact along sidewall.And, by making the grid contact trench more shallow than active contact trench, the grid contact trench will unlikely penetrate the grid lead polysilicon during etch process, and this for the device with shallow relatively grid polycrystalline silicon (such as, the device that uses this sampling technology to make, that is, this technology can cause grid polycrystalline silicon can not extend on the top surface of body) be useful.
Fig. 1 C is another embodiment of DMOS device.In this example, grid contact trench 117 has the different degree of depth with active region contact trench 112a-112b.In addition, the degree of depth of each active region contact trench is also inconsistent, because gash depth is being parallel on the direction of substrate surface and can changing.As described in more detail below, active region contact trench is to use two step process to form, and causes first contact openings (for example, 120a-120b) (for example, 119a-119b) wide than second contact openings.The contour shape of active region contact trench allows bigger ohmic contact zone and wears injection 170a-170d by resistance and better avoid puncturing, and has improved the UIS ability of device.Shannon injects along the sidewall of second contact openings and bottom and distributes, and has formed schottky barrier controlling layer 190a-190b.
Fig. 1 D-1F shows the embodiment of the DMOS device with integrated low injection body diode.Device 106,108 and 110 has the active region contact trench more shallow than this tagma.In certain embodiments, the thin layer in this tagma separates the bottom of active area groove with epitaxial loayer, formed the low injection diode under body/drain junction.The thickness of thin body layer and doped level (this thin body layer is between active region contact trench and drain electrode) are adjusted, so that in reverse biased, this thin body layer almost completely exhausts, and in forward bias, the body layer can not exhaust.In certain embodiments, the thickness of this layer is about 0.01～0.5 μ m.Because charge carrier greatly reduces, so the integrated body diode than routine of this low injection diode in device 106,108 and 110 provides the improvement on the performance.Suitably controlling under the situation of thin body layer, the low body diode of injecting can provide the performance suitable with Schottky diode, and the advantage of bringing is: because the formation that can save schottky barrier controlling layer, and the simplification technology of bringing.
Fig. 2 shows the schematic diagram of buck converter circuit example.In this example, circuit shown in 200 has used high-end FET device 201 and low side FET device 207.High-end device 201 comprises transistor 202 and body diode 204.Low side devices impose 207 can use 100,102 or 104 device shown in Figure 1A-1F to realize.Device 207 comprises transistor 208, body diode 210 and Schottky diode 212.Load comprises inductor 214, capacitor 216 and resistor 218.During normal running, device 201 is switched on so that power is sent to load from input source.This can cause that electric current rises in inductor.When device 201 was cut off, inductor current still flowed, and conversion direction is to the body diode 210 of device 207.After of short duration delay, control circuit makes device 207 conductings, the raceway groove of its turn-on transistor 208, and reduce significantly along the forward voltage drop of the drain electrode-source terminal of device 208.Under the situation that does not have Schottky diode 212, the body diode conduction loss and remove the loss that charge stored is brought in the body diode 210 of device 207 may be bigger.Yet, if Schottky diode 212 is structured in the device 207, and if Schottky diode have low forward voltage drop, conduction loss can greatly reduce.Owing to the knot pressure drop that is lower than body diode along the low forward voltage drop of Schottky diode,, further improved the related loss of diode recovery so when Schottky diode conducts, do not have charge stored to inject.
Fig. 3 shows the flow chart of the embodiment of the manufacturing process that is used to make up the DMOS device.302, in the epitaxial loayer that covers Semiconductor substrate, form gate trench.304, grid material is deposited in the gate trench.306 and 308, form body and source electrode.310, form contact trench.As following described in more detail, in certain embodiments, in a step, form active region contact trench and gate regions groove; In certain embodiments, groove forms in a plurality of steps, to obtain the different degree of depth.312, contact electrode is arranged in the contact trench.Technology 300 and step thereof can be revised, to produce the different embodiment of MOS device, the 102-110 shown in Figure 1A-1F.
Fig. 4 A-4U is the viewgraph of cross-section of device, shows in detail the exemplary manufacturing process that is used to make the MOS device.In this example, (that is, growth has N to N type substrate on it
-The N of epitaxial loayer
+Silicon chip) is used as the drain electrode of device.
Fig. 4 A-4J shows the formation of grid.In Fig. 4 A,, on N type substrate 400, form SiO by deposition or thermal oxidation
2Layer 402.In various embodiments, the thickness of silica is 100
-30000
Scope.Other thickness also can use.This thickness can depend on the gate height of expectation and adjust.Photoresist layer 404 is spin-coated on the top of oxide skin(coating), and uses trench mask to come composition.
In Fig. 4 B, the SiO in the exposed region
2Be removed, stayed and be used for the etched SiO of silicon
2Hard mask 410.In Fig. 4 C, anisotropically etching silicon has stayed the groove such as 420.Grid material is deposited in the groove.The grid that is formed on afterwards in the groove has vertical with the top surface of substrate basically side.In Fig. 4 D, to SiO
2 Hard mask 410 carries out a certain amount of etch-back, makes trench wall keep aiming at the limit of hard mask basically after etching step after a while.SiO
2Be the mask material that uses in the present embodiment, because use SiO
2The etching meeting of hard mask stays the relative straight trench wall of aiming at mutually with the sidepiece of mask.If suitable, also can use other materials.The material that is used for etched some other types of hard mask traditionally is such as Si
3N
4, can stay the trench wall after the etching that has curvature, this is not for good enough for forming grid in the following step.
In Fig. 4 E, isotropically etch substrate is with the bottom sphering with groove.In certain embodiments, it is dark that groove is about 0.5-2.5 μ m, and it is wide to be about 0.2-1.5 μ m; Other sizes also can be used.For smooth surface being provided for the growth grid dielectric material, SiO grows in groove
2Sacrifice layer 430.Then, remove this sacrifice layer by wet etching process.In Fig. 4 G, heat growth SiO in groove
2Layer 432 as dielectric material.
In Fig. 4 H, deposit spathic silicon 440 is with filling groove.In this case, polysilicon is doped to obtain suitable resistance.In certain embodiments, when (original position) deposit spathic silicon layer, mix.In certain embodiments, after deposition, polysilicon is mixed.In Fig. 4 I, to SiO
2Polysilicon layer on the top carries out etch-back to form the grid such as 442.In this, the top surface 444 of grid is with respect to SiO
2 Top surface 448 remain depression; Yet, depending on the thickness of hard mask layer 410, the top surface 444 of grid can be higher than the top layer 446 of silicon.In certain embodiments, in the polysilicon etch-back, do not use mask.In certain embodiments, in the polysilicon etch-back, use mask to avoid in following body injection technology, using additional mask.In Fig. 4 J, remove SiO
2Hard mask.In certain embodiments, use dry ecthing to remove hard mask.Etch process stops when running into top silicon surface, extends thereby polysilicon gate is gone up at substrate surface (wherein will inject source dopant and bulk doped thing).In certain embodiments, grid extends about 300 on substrate surface
-20000
Other values also can be used.Use SiO in these embodiments
2Hard mask is because it provides the grid of expectation amount to extend on the Si surface with controllable mode.Subsequently, can be on wafer the growth mask oxide.Above processing step can at manufacturing have depression grid polycrystalline silicon device and simplify.For example, in certain embodiments, during forming groove, use photoresist mask or extremely thin SiO
2Hard mask, and therefore resulting grid polycrystalline silicon can not extend on the Si surface.
Fig. 4 K-4N shows the formation of source electrode and body.In Fig. 4 K, use the body mask on body surface, photoresist layer 450 to be carried out composition.Unshielded zone is injected with the bulk doped thing.Alloy such as the boron ion is injected into.Among unshowned herein some embodiment, under the situation that does not have body obstacle 450, carry out body and inject, thereby between active groove, formed this continuous tagma.In Fig. 4 L, remove photoresist, and heated chip is to drive the bulk doped thing thermal diffusion of the technology of (body drive) with injection by being sometimes referred to as body.Subsequently, formed this tagma 460a-460d.In certain embodiments, the energy that is used for injecting the bulk doped thing is between 30～600keV, and dosage is about 5e12-4e13 ion/cm
2, and the resulting final body degree of depth is between 0.3-2.4 μ m.By changing the factor, comprise and inject energy, dosage and diffusion temperature, can obtain the different degree of depth.During diffusion technology, formed oxide skin(coating) 462.
In Fig. 4 M, use source mask that photoresist layer 464 is carried out composition.In the embodiment shown, source mask 464 can not stop any zone between the active groove.In certain embodiments, source mask 464 also stops the middle section (not shown) between the active groove.Source dopant is injected not masking regional 466.In this example, arsenic ion infiltrates the silicon in the masking regional not, to form N
+The type source electrode.In certain embodiments, the energy that is used to inject source dopant is between 10～100keV, and dosage is about 1e15-1e16 ion/cm
2Between, and the resulting source electrode degree of depth is between 0.05-0.5 μ m.Can such as implant energy and dosage, realize that the further degree of depth reduces by changing the factor.Suitable, other injection technologies also can be used.In Fig. 4 N, remove photoresist, and heated chip is to come that by source drive technology the source dopant of injecting is carried out thermal diffusion.After source drive, (for example, BPSG) layer 465 is arranged on the top surface of device, and alternatively, in certain embodiments can be with its densification with dielectric.
Fig. 4 O-4T shows the formation of contact trench and along the various injections of contact trench.In Fig. 4 O, photoresist layer 472 is deposited on the dielectric layer, and uses the contact mask to come composition.Carry out first contact etch and form groove 468 and 470.In certain embodiments, the degree of depth of first contact trench is between 0.2-2.5 μ m.
In Fig. 4 P, remove the photoresist layer, utilize the ion that injects to bombard groove 470 bottom periphery zones and prevent layer to form to puncture.In certain embodiments, using dosage is about 1-5e15 ion/cm
2The boron ion.Inject energy and be about 10-60keV.In certain embodiments, using dosage is about 1-5e15 ion/cm
2, to inject energy be the BF of 40-100keV
2Ion.In certain embodiments, inject BF
2Prevent layer with boron to form to puncture.Inject the inclination angle between the 0-45 degree.In Fig. 4 Q, infusion is carried out thermal diffusion.
In Fig. 4 R, carry out second contact etch.Because etch process can not influence dielectric layer, so second contact etch does not need extra mask.In certain embodiments, the degree of depth of groove has increased 0.2-0.5 μ m.Puncture is prevented that layer etching from wearing, stay to resist along trench wall and wear infusion 474a-474b.In Fig. 4 S, use ion to inject and form the shallow P type of low dosage schottky barrier controlling layer 476.In certain embodiments, using dosage is at 2e11-3e13 ion/cm
2Between, inject boron or the BF of energy between 10-100keV
2In Fig. 4 T, activate schottky barrier controlling layer by thermal diffusion.Wear to inject with resistance and compare, schottky barrier controlling layer need be than low dosage, and has produced more low-doped and thin implanted layer thus.In certain embodiments, to be about 0.01-0.05 μ m thick for schottky barrier controlling layer.Schottky barrier controlling layer can be adjusted barrier height, because infusion is adjusted at the surface energy between contact electrode and the semiconductor.
In Fig. 4 U, show complete device 490.Metal level 478 is deposited, etching and annealing under suitable situation.After deposit passivation layer 480, make passivation opening.Can also carry out the additional step that need be used for finishing manufacturing, such as wafer grinding and rear end metal deposition.
Can use optional technology.For example, for the device 106-110 shown in the shop drawings 1D-1F, the body injection technology shown in Fig. 4 K is made amendment, and in active area, do not have the body obstacle.The bulk doped thing is directly injected, is covered area exposed and formed this continuous tagma between grid.During contact etch, groove is etched into the degree of depth than this tagma bottom shallow, make body layer be lower than contact trench.Alternatively, can with active contact trench only etching pass body, to expose the extension drain region, be to utilize the additional bulk doped of the energy of good control and alloy to inject to pass the contact trench sidewall and thin body layer is formed on the bottom subsequently.
In certain embodiments, in order to form schottky barrier controlling layer, deposit low bandgap material by chemical vapor deposition (CVD), with cambium layer on the top surface of epitaxial loayer such as SiGe.In certain embodiments, the thickness of low bandgap material layer is from 100
To 1000
Scope in.For example, use 200 in certain embodiments
Silicon-rich SiGe layer.In certain embodiments, Silicon-rich SiGe layer comprises 80% Si and 20% Ge.In certain embodiments, utilize N type alloy with 2e17-2e18/cm
3Concentration come to carry out in-situ doped to the low bandgap material layer.Subsequently, on narrow bandgap layer, deposit low temperature oxide layer, then this low temperature oxide layer is carried out composition to form hard mask, be used for the groove dry corrosion is carved into epitaxial loayer.During dry etching process, the part of the narrow bandgap layer below the hard mask protection.
Fig. 5 A-6B shows the additional optional embodiment of manufacturing step.For example, Fig. 5 A punctures and prevents layer diffusion (referring to Fig. 4 Q).Use the second contact mask to come photoresist layer 502 is carried out composition, with barrier grid groove 504.In Fig. 5 B, take place second and be etched with the degree of depth that increases active region contact trench 506.Remove photoresist then, and schottky barrier controlling layer is injected in the mode that is similar among Fig. 4 S and the 4T.The additional completing steps that comprises metal deposition and passivation is still implemented (referring to Fig. 4 U).Resulting device is similar to the device 102 of Figure 1B, and wherein gate trench has the degree of depth different with active region contact trench.By using at the etched independent mask of second contact trench, to realize the degree of depth of different gate trench and active region contact trench, it is more shallow that the gate trench contact is made, and can relax for the worry that punctures grid polycrystalline silicon during etching.Like this, use this technology manufacturing to have the device of short gate polysilicon usually, comprise embodiment with the grid polycrystalline silicon that on substrate surface, does not extend.
Fig. 6 A has also carried out puncture and has prevented layer diffusion (referring to Fig. 4 Q).Use the second contact mask to come photoresist layer 602 is carried out composition with barrier grid groove 604, and so that on active region contact trench 606, form than the little contact openings of the first etched contact openings.In Fig. 6 B, carry out second contact etch, to form darker, narrower trench portions 608.Remove photoresist, and implement remaining step from Fig. 4 S-4U.Resulting device is similar to 103 of Fig. 1 C.
Fig. 7-10 shows the optional improvement of manufacturing process, and these improvement can be used in certain embodiments with further enhance device performance.
Optional improvement shown in Fig. 7 can be carried out afterwards and in coating body block mask (Fig. 4 K) before at formation grid (Fig. 4 G).Spread all over epitaxial loayer, deposition has the even thick injection 702 with the epitaxial loayer opposite polarity.In certain embodiments, (5e11-1e13, boron 200-600keV) are used to form even thick injection 702 before forming main body injection for high-energy, low dosage.Even thick injection is used for adjusting the epitaxial loayer profile, and can not cause the semipolar change of epitaxial loayer.Even thick injection has changed the body profile of body bottom section, and at not obvious increase R
DsonSituation under strengthened puncture voltage.
Optional improvement shown in Fig. 8 can the deposition Shannon inject (Fig. 4 S) afterwards, but carry out before in its activation (Fig. 4 T).The tuning injection of epitaxial loayer profile is injected under the active region contact trench.The tuning injection of epitaxial loayer profile has the polarity opposite with epitaxial loayer.In certain embodiments, the boron of high-energy, low dosage or BF
2(for example, 5e11-1e13 60-300keV) is used to inject.This injects tuning epitaxial loayer profile and does not change epitaxial loayer polarity, and has strengthened puncture voltage.
Optional improvement shown in Fig. 9 can the deposition Shannon inject (Fig. 4 S) afterwards, but (Fig. 4 T) carries out before it activates.(1e12-5e13, boron 60-300keV) are injected into to form P type island 902, and this P type island 902 is arranged in the N type epitaxial loayer under the contact trench, and are connected with this tagma disconnection for high-energy, middle dosage.The P type island of floating has also strengthened puncture voltage.
Optional improvement shown in Figure 10 can be injected (Fig. 4 P) and carry out before afterwards and carrying out Shannon forming contact trench (Fig. 4 O).Because sharp-pointed angle can stored charge, produce high electric field and lower puncture voltage, institute so that the angle 1002a-1002b sphering of channel bottom with the accumulation of minimizing electric charge and improve puncture voltage.
Although for clearly understanding this purpose, described previous embodiment in some details, the details that provided is provided in the present invention.Can exist optional mode to realize the present invention.The disclosed embodiments only are schematic rather than restrictive.
Claims (26)
1. semiconductor device that is formed on the Semiconductor substrate comprises:
Drain electrode;
Cover the epitaxial loayer of described drain electrode; And
Active area comprises:
Body, described body places described epitaxial loayer, and has the body top surface;
Source electrode, described source electrode is embedded in the described body, and extends to the described body from described body top surface;
Gate trench, described gate trench extend in the described epitaxial loayer;
Grid, described grid places described gate trench;
Active region contact trench, described active region contact trench extends in the described drain electrode by described source electrode and described body; And
The active area contact electrode, described active area contact electrode places in the described active region contact trench, and wherein said active area contact electrode and described drain electrode form Schottky diode; And
Schottky barrier controlling layer, described schottky barrier controlling layer place the described epitaxial loayer contiguous with described active region contact trench.
2. semiconductor device according to claim 1, wherein said schottky barrier controlling layer place and contiguous place, the bottom of described active region contact trench.
3. semiconductor device according to claim 1, wherein said schottky barrier controlling layer comprise the material thin-layer that is doped with the alloy of described epitaxial loayer opposite polarity.
4. semiconductor device according to claim 1, wherein said schottky barrier controlling layer comprises the thin layer of low bandgap material.
5. semiconductor device according to claim 1, wherein said gate trench are the first grid grooves; And
Described device further comprises gate regions, and described gate regions comprises:
The second grid groove, described second grid groove extends in the described epitaxial loayer;
Second grid, described second grid place described second grid groove; And the grid contact trench, described grid contact trench is formed in the described second grid.
6. semiconductor device according to claim 5, wherein said grid contact trench and described active region contact trench have the approximately uniform degree of depth.
7. semiconductor device according to claim 5, wherein said active region contact trench have and the different degree of depth of described grid contact trench.
8. semiconductor device according to claim 1, wherein said active region contact trench has the inconsistent degree of depth.
9. semiconductor device according to claim 1, wherein:
Described active region contact trench has first degree of depth and second degree of depth;
Described second depth as shallow of described first depth ratio; And
First contact openings ratio corresponding to described first degree of depth is wide corresponding to second contact openings of described second degree of depth.
10. semiconductor device according to claim 1 comprises further resisting and wears injection that described resistance is worn to inject and placed on the sidewall of described active region contact trench.
11. semiconductor device according to claim 10, wherein said resistance are worn to inject and are placed on the described schottky barrier controlling layer.
12. semiconductor device according to claim 1 further comprises even thick injection, described even thick injection is deposited on whole described epitaxial loayer, and wherein said even thick injection has the polarity opposite with described epitaxial loayer.
13. semiconductor device according to claim 1 further comprises the tuning injection of epitaxial loayer profile, the tuning injection of described epitaxial loayer profile is deposited under the described active region contact trench.
14. semiconductor device according to claim 1 further comprises the island district under the described active region contact trench, wherein said island district has the polarity opposite with described epitaxial loayer.
15. semiconductor device according to claim 1, wherein said grid extends on described body top surface.
16. a method of making semiconductor device comprises:
In the epitaxial loayer that covers Semiconductor substrate, form gate trench;
Deposition of gate material in described gate trench;
Form body;
Form source electrode;
Form active region contact trench, described active region contact trench extends in the described drain electrode by described source electrode and described body;
The deposition schottky barrier controlling layer; And
In described active region contact trench, arrange contact electrode.
17. method according to claim 16 wherein deposits described schottky barrier controlling layer and comprises: dopant deposition has the material thin-layer with the alloy of described epitaxial loayer opposite polarity.
18. method according to claim 16, wherein said gate trench are the first grid grooves, and
Described method further comprises the formation gate regions, comprising:
Form the second grid groove, described second grid groove extends in the described epitaxial loayer;
In described second grid groove, form second grid; And
Form the grid contact trench, described grid contact trench is formed in the described second grid.
19. method according to claim 18, wherein said grid contact trench and described active region contact trench have the approximately uniform degree of depth.
20. method according to claim 18, wherein said active region contact trench have and the different degree of depth of described grid contact trench.
21. method according to claim 18, wherein said active region contact trench has the inconsistent degree of depth.
22. method according to claim 16, wherein:
Described active region contact trench formed have first degree of depth and second degree of depth;
Described second depth as shallow of described first depth ratio; And
Make corresponding to first contact openings ratio of described first degree of depth wide corresponding to second contact openings of described second degree of depth.
23. method according to claim 16 further comprises: the even thick injection of deposition in whole described epitaxial loayer, wherein said even thick injection has the polarity opposite with described epitaxial loayer.
24. method according to claim 16 further comprises: form the tuning injection of epitaxial loayer profile, the tuning injection of described epitaxial loayer profile is deposited under the described active region contact trench.
25. method according to claim 16 further comprises: form the island district under described active region contact trench, wherein said island district has opposite polarity with described epitaxial loayer.
26. method according to claim 16 wherein forms described grid on described body top surface and extends.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US12/005,166 US8362547B2 (en) | 2005-02-11 | 2007-12-21 | MOS device with Schottky barrier controlling layer |
| US12/005,166 | 2007-12-21 |
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| Publication Number | Publication Date |
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| CN101465375A true CN101465375A (en) | 2009-06-24 |
| CN101465375B CN101465375B (en) | 2011-04-13 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2008101823208A Expired - Fee Related CN101465375B (en) | 2007-12-21 | 2008-11-21 | MOS device with schottky barrier controlling layer |
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| Country | Link |
|---|---|
| CN (1) | CN101465375B (en) |
| TW (1) | TWI378563B (en) |
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| CN102074501A (en) * | 2009-11-23 | 2011-05-25 | 英特赛尔美国股份有限公司 | Integrated guarded schottky diode compatible with trench-gate DMOS, structure and method |
| CN102214603A (en) * | 2010-04-06 | 2011-10-12 | 科轩微电子股份有限公司 | Power semiconductor structure with schottky diode and manufacturing method thereof |
| CN102299103A (en) * | 2010-06-25 | 2011-12-28 | 茂达电子股份有限公司 | Method for manufacturing semiconductor component |
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2008
- 2008-11-21 CN CN2008101823208A patent/CN101465375B/en not_active Expired - Fee Related
- 2008-11-21 TW TW97145132A patent/TWI378563B/en active
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| CN102214603B (en) * | 2010-04-06 | 2013-09-04 | 科轩微电子股份有限公司 | Power semiconductor structure with schottky diode and manufacturing method thereof |
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| CN102299103B (en) * | 2010-06-25 | 2013-05-08 | 茂达电子股份有限公司 | Method for manufacturing semiconductor component |
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| CN105321945B (en) * | 2014-05-30 | 2020-12-25 | 德克萨斯仪器股份有限公司 | Trench MOSFET with reduced gate charge |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101465375B (en) | 2011-04-13 |
| TW200929551A (en) | 2009-07-01 |
| TWI378563B (en) | 2012-12-01 |
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