TWI455312B - A Power MOSFET Device and Manufacturing Method - Google Patents
A Power MOSFET Device and Manufacturing Method Download PDFInfo
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Description
本發明涉及一種功率MOSFET裝置及其製造方法,特別涉及在同一接觸溝道中通過不同特性金屬分別構造漏極肖特基結和體區歐姆結的功率MOSFET裝置及其製造方法。 The present invention relates to a power MOSFET device and a method of fabricating the same, and more particularly to a power MOSFET device for constructing a drain Schottky junction and a body region ohmic junction by different characteristic metals in the same contact channel, and a method of fabricating the same.
如第1圖所示,是現有功率MOSFET(金屬氧化物半導體場效應電晶體)裝置的結構示意圖,以n溝道的MOSFET為例,其包含一生成在n+底部襯底100上的n-外延層200、在n-外延層200中開設有若干溝槽柵極310,沿該溝槽柵極310的側壁和底部設置有柵極絕緣層320與n-外延層200絕緣隔離。在n-外延層200的頂部部分、圍繞該溝槽柵極310還形成有p型體區400和源極區域450。在上述n-外延層200、溝槽柵極310和源極區域450的頂部表面還沉積有含低溫氧化物和硼磷矽玻璃的介電層500。 As shown in FIG. 1 , it is a schematic structural diagram of a conventional power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) device. Taking an n-channel MOSFET as an example, it includes an n-epitaxial formed on the n + underlying substrate 100. In the layer 200, a plurality of trench gates 310 are disposed in the n- epitaxial layer 200, and a gate insulating layer 320 is disposed along the sidewalls and the bottom of the trench gate 310 to be insulated from the n- epitaxial layer 200. A p-type body region 400 and a source region 450 are also formed around the trench gate 310 at a top portion of the n- epitaxial layer 200. A dielectric layer 500 containing a low temperature oxide and borophosphon glass is also deposited on the top surface of the n- epitaxial layer 200, the trench gate 310, and the source region 450.
通過刻蝕形成若干貫穿介電層500、源極區域450和體區400的接觸溝道600,其底部一直延伸至外延層200中。在上述介電層500的頂部表面和接觸溝道600的側壁及底部表面上沉積由金屬材料構成的介面勢壘導電層700。在介面勢壘導電層700上還沉積有連接金屬層800,該連接金屬層800將接觸溝道600填滿且延伸至所述介電層500頂面上方。後續通過光刻、刻蝕上述連接金屬層800及介面勢壘導電層700形成半導體裝置的電極圖案。 A plurality of contact trenches 600 are formed through the dielectric layer 500, the source regions 450, and the body regions 400 by etching, the bottom portions of which extend all the way into the epitaxial layer 200. An interface barrier conductive layer 700 made of a metal material is deposited on the top surface of the dielectric layer 500 and the sidewalls and the bottom surface of the contact trench 600. Also deposited on the interface barrier conductive layer 700 is a bonding metal layer 800 that fills the contact trench 600 and extends over the top surface of the dielectric layer 500. Subsequently, the electrode patterns of the semiconductor device are formed by photolithography, etching the connection metal layer 800 and the interface barrier conductive layer 700.
上述介面勢壘導電層700的側面與高濃度摻雜的體區400之間,由於金屬-半導體接觸形成歐姆結;而在介面勢壘導電層700的底部 與低濃度摻雜的外延層200之間則形成肖特基結。其中,歐姆結具有電阻小、I-V(電流-電壓)曲線線性對稱的特點,一般如果在介面勢壘導電層700使用功函數較高的金屬材料(如功函數5.65eV的白金Pt等)與半導體接觸,能夠降低金屬與半導體間的勢壘高度,使歐姆結的電阻更小。而肖特基結具有二極體特性的I-V曲線,通常如果使用功函數適中的金屬材料組合半導體參雜濃度變化,能使肖特基結的整流效果更好。上述功函數是指一個電子從費米(Fermi)能級上升到金屬表面靜止狀態(即真空能級)所需的最小能量。 Between the side surface of the interface barrier conductive layer 700 and the high concentration doped body region 400, an ohmic junction is formed due to the metal-semiconductor contact; and at the bottom of the interface barrier conductive layer 700 A Schottky junction is formed between the epitaxial layer 200 doped with a low concentration. Among them, the ohmic junction has the characteristics of small resistance and linear symmetry of the IV (current-voltage) curve. Generally, if a dielectric material having a higher work function (such as a work function of 5.65 eV of platinum Pt, etc.) and a semiconductor are used in the interface barrier conductive layer 700. Contact can reduce the barrier height between the metal and the semiconductor, making the resistance of the ohmic junction smaller. The Schottky junction has an I-V curve with diode characteristics. Generally, if a metal material with a moderate work function is used to combine the semiconductor impurity concentration changes, the Schottky junction can be more rectified. The above work function refers to the minimum energy required for an electron to rise from the Fermi level to the metal surface at rest (ie, the vacuum level).
然而,對於上述現有的功率MOSFET裝置來說,由於介面勢壘導電層700側面形成的歐姆結與底部形成的肖特基結共用同一個介面勢壘導電層700,例如在介面勢壘導電層700使用高功函數的金屬材料雖然能發揮歐姆結電阻小的特性,但由於其必須通過很高的正向電壓才能導通,對於肖特基結的性能發揮有很大影響。為了做到對歐姆接觸和肖特基接觸特性的兼顧,往往只能選擇功函數折衷的金屬材料來製成介面勢壘導電層700,因而不能充分發揮各自的特性。 However, for the above-described conventional power MOSFET device, the ohmic junction formed on the side of the interface barrier conductive layer 700 shares the same interface barrier conductive layer 700 as the Schottky junction formed at the bottom, for example, in the interface barrier conductive layer 700. Although a metal material using a high work function can exhibit a small ohmic junction resistance, it must be turned on by a very high forward voltage, which greatly affects the performance of the Schottky junction. In order to achieve both the ohmic contact and the Schottky contact characteristics, it is often possible to select only the metal material to which the work function is compromised to form the interface barrier conductive layer 700, and thus the respective characteristics cannot be sufficiently exerted.
另外,如第1圖中虛線部分所示,接觸溝道600的底部角落位置沒有被體區400包圍,而是與外延層200接觸形成肖特基結,在底部的肖特基結邊沿角會有電場集中的現象,因而很容易在接觸溝道600底部角落產生很大的反向漏電流。 In addition, as shown by the broken line portion in FIG. 1, the bottom corner position of the contact channel 600 is not surrounded by the body region 400, but is in contact with the epitaxial layer 200 to form a Schottky junction, and the corner of the Schottky junction at the bottom will be There is a phenomenon in which the electric field is concentrated, so that it is easy to generate a large reverse leakage current at the bottom corner of the contact channel 600.
本發明的目的在於提供一種功率MOSFET裝置及其製造方法,能夠通過體區包圍接觸溝道的底部角落來減少反向漏電流;還通過沉積不同功函數的金屬與半導體分別接觸形成肖特基結和歐姆結來發揮其各自的特性。 It is an object of the present invention to provide a power MOSFET device and a method of fabricating the same that can reduce reverse leakage current by surrounding a bottom corner of a contact channel by a body region; and form a Schottky junction by respectively depositing a metal and a semiconductor with different work functions. And ohmic junctions to play their respective characteristics.
為了達到上述目的,本發明的技術方案是提供一種功率MOSFET裝置,包含:設置在底部襯底上的外延層;形成於外延層中的溝槽內的溝槽柵極;形成在外延層的頂部部分,且圍繞溝槽柵極的體區; 形成在體區頂部部分的源極區域;形成在溝槽柵極和源極區域頂部表面上的介電層;若干貫穿介電層、源極區域形成的接觸溝道;其特徵在於,上述接觸溝道底部終止于體區,使上述接觸溝道的底部角落被上述體區包圍;還包含形成在接觸溝道下方中間的體區中、與外延層連接的漂移區;形成在上述接觸溝道的底部中間區域的肖特基結;形成在接觸溝道的側壁和其底部角落表面上的歐姆結。 In order to achieve the above object, the technical solution of the present invention provides a power MOSFET device comprising: an epitaxial layer disposed on a bottom substrate; a trench gate formed in a trench in the epitaxial layer; formed on top of the epitaxial layer Partially, and surrounding the body region of the trench gate; a source region formed at a top portion of the body region; a dielectric layer formed on a top surface of the trench gate and the source region; a plurality of contact channels formed through the dielectric layer and the source region; wherein the contact The bottom of the channel terminates in the body region such that the bottom corner of the contact channel is surrounded by the body region; and further includes a drift region formed in the body region below the contact channel and connected to the epitaxial layer; formed in the contact channel a Schottky junction of the bottom intermediate portion; an ohmic junction formed on the sidewall of the contact channel and the bottom corner surface thereof.
上述的功率MOSFET裝置,還包含覆蓋在歐姆結、肖特基結表面上的連接金屬層,其填滿上述接觸溝道且延伸至介電層的頂面上方。 The power MOSFET device described above further includes a connection metal layer overlying the ohmic junction, Schottky junction surface, filling the contact channel and extending over the top surface of the dielectric layer.
上述肖特基結是由介面勢壘導電材料與上述漂移區接觸形成的。 The Schottky junction is formed by contacting an interface barrier conductive material with the drift region.
上述歐姆結是由介面勢壘導電材料與上述體區接觸形成的。 The ohmic junction is formed by contacting an interface barrier conductive material with the body region.
與上述體區接觸形成歐姆結的介面勢壘導電材料,和與上述漂移區接觸形成肖特基結的介面勢壘導電材料不同。 The interface barrier conductive material that forms an ohmic junction in contact with the body region is different from the interface barrier conductive material that contacts the drift region to form a Schottky junction.
上述體區中還設置有環繞上述接觸溝道側壁及底部角落形成的離子注入區;上述接觸溝道的底部角落被上述離子注入區包圍。 The body region is further provided with an ion implantation region formed around the sidewalls of the contact channel and the bottom corner; the bottom corner of the contact channel is surrounded by the ion implantation region.
一種功率MOSFET裝置的製造方法,包含以下步驟:a.在底部襯底上形成外延層;b.在外延層中形成溝槽柵極;c.在外延層中離子注入形成體區;d.在外延層上部離子注入形成源極區域;e.外延層上方沉積形成介電層;其特徵在於,還包含以下步驟:f.刻蝕介電層形成若干底部延伸至體區的接觸溝道;h.沉積並刻蝕形成間隔層;i.在接觸溝道下部中間的體區中,形成連接外延層的漂移 區;j.沉積第一介面勢壘導電材料,並在接觸溝道底部中間與漂移區接觸形成肖特基結;l.沉積第二介面勢壘導電材料,並在接觸溝道的側壁及其底部角落與體區接觸形成歐姆結;m.歐姆結、肖特基結上沉積形成連接金屬層。 A method of fabricating a power MOSFET device comprising the steps of: a. forming an epitaxial layer on a bottom substrate; b. forming a trench gate in the epitaxial layer; c. forming an organic region by ion implantation in the epitaxial layer; d. The upper portion of the epitaxial layer is ion-implanted to form a source region; e. depositing a dielectric layer over the epitaxial layer; and further comprising the steps of: f. etching the dielectric layer to form a plurality of contact channels extending from the bottom to the body region; Depositing and etching to form a spacer layer; i. forming a drift connecting the epitaxial layer in a body region in the middle of the lower portion of the contact channel a first interface barrier conductive material is deposited, and a Schottky junction is formed in contact with the drift region in the middle of the bottom of the contact channel; 1. a second interface barrier conductive material is deposited, and the sidewall of the contact channel is The bottom corner contacts the body region to form an ohmic junction; the m. ohmic junction and the Schottky junction are deposited to form a connecting metal layer.
在步驟f和步驟h之間,還包含在上述接觸溝道側壁和底部通過傾斜離子注入形成離子注入區的步驟g。 Between step f and step h, a step g of forming an ion implantation region by oblique ion implantation at the sidewalls and the bottom of the contact channel is further included.
上述接觸溝道的底部終止于上述體區或其中的離子注入區中,使上述接觸溝道的底部角落被上述體區或上述離子注入區包圍。 The bottom of the contact channel terminates in the body region or the ion implantation region therein such that the bottom corner of the contact channel is surrounded by the body region or the ion implantation region.
本發明的一個優選實施例中,上述間隔層是通過垂直方向各向異性刻蝕形成在上述接觸溝道側壁及其底部角落,並使上述接觸溝道底部中間區域的表面露出。 In a preferred embodiment of the present invention, the spacer layer is formed by the anisotropic etch in the vertical direction on the side wall of the contact channel and the bottom corner thereof, and exposes the surface of the intermediate portion of the bottom portion of the contact channel.
上述形成間隔層的步驟h,具體是通過沉積絕緣的犧牲材料實現的。 The step h of forming the spacer layer described above is specifically achieved by depositing an insulating sacrificial material.
上述步驟h中,沉積形成間隔層的犧牲材料,是二氧化矽SiO2或氮化矽SiN的絕緣材料。 In the above step h, the sacrificial material which forms the spacer layer is an insulating material of cerium oxide SiO2 or cerium nitride SiN.
上述步驟i和步驟j之間,還包含去除上述絕緣的間隔層的步驟k。 Between the above steps i and j, the step k of removing the insulating spacer layer is further included.
本發明的另一個優選實施例中,上述步驟h中,具體是通過沉積第二介面勢壘導電材料,並刻蝕形成覆蓋在接觸溝道的側壁及其底部角落的間隔層,並使上述間隔層與上述體區接觸形成歐姆結。 In another preferred embodiment of the present invention, in the step h, specifically, by depositing a second interface barrier conductive material, etching and forming a spacer layer covering the sidewall of the contact channel and a bottom corner thereof, and spacing the spacer The layer is in contact with the body region to form an ohmic junction.
上述步驟j中,上述肖特基結是以上述間隔層為掩膜,在上述接觸溝道的底部中間區域沉積可形成矽化物的金屬實現的;上述金屬是鈦Ti,或鉭Ta,或鎳Ni。 In the above step j, the Schottky junction is realized by depositing a metal which can form a germanide in the middle portion of the bottom of the contact channel by using the spacer layer as a mask; the metal is titanium Ti, or tantalum Ta, or nickel. Ni.
上述步驟i具體是在接觸溝道下面中間的體區中,通過離子注入和局部反型該體區,形成上述與外延層連接的漂移區。 In the above step i, specifically, in the body region in the middle of the contact channel, the drift region connected to the epitaxial layer is formed by ion implantation and partial inversion of the body region.
本發明提供的功率MOSFET裝置及其製造方法,與現有技術相比,其優點在於:本發明由於沉積高功函數特性的導電材料,在接觸溝道的側壁和底部角落與重摻雜的體區接觸形成歐姆結;還通過沉積功函 數適中的導電材料,在接觸溝道的底部中間與輕摻雜的外延層接觸形成肖特基結,因而使本發明能在同一接觸溝道中構造P/N兩種不同類型的矽介面,並和不同功函數的金屬形成歐姆接觸和肖特基接觸,因此能夠同時發揮歐姆結電阻小和肖特基結整流的特性。 The power MOSFET device and the manufacturing method thereof provided by the invention have advantages over the prior art in that the present invention deposits a high work function characteristic conductive material in the sidewalls and bottom corners of the contact channel and the heavily doped body region. Contact to form an ohmic junction; a moderately conductive material that contacts the lightly doped epitaxial layer in the middle of the bottom of the contact channel to form a Schottky junction, thereby enabling the present invention to construct two different types of germanium interfaces of P/N in the same contact channel, and An ohmic contact and a Schottky contact are formed with metals of different work functions, so that the characteristics of small ohmic junction resistance and Schottky junction rectification can be simultaneously exhibited.
本發明由於使接觸溝道的底部角落被體區或其中的B+硼P-型離子注入區包圍,能夠在保證肖特基結的接觸特性同時,有效降低接觸溝道角落位置的反向漏電流。而且由於肖特基結被設置在接觸溝道中間這一單一的矽晶面上,因而對肖特基結的一致性也能有效提高。 In the present invention, since the bottom corner of the contact channel is surrounded by the body region or the B+ boron P-type ion implantation region therein, the reverse leakage current of the contact channel corner position can be effectively reduced while ensuring the contact characteristics of the Schottky junction. . Moreover, since the Schottky junction is disposed on the single twin plane in the middle of the contact channel, the uniformity of the Schottky junction can be effectively improved.
MOSFET‧‧‧金屬氧化物半導體場效應電晶體 MOSFET‧‧‧Metal Oxide Semiconductor Field Effect Transistor
10‧‧‧底部襯底 10‧‧‧Bottom substrate
20‧‧‧外延層 20‧‧‧ Epilayer
25‧‧‧漂移區 25‧‧‧ drift zone
30‧‧‧溝槽 30‧‧‧ trench
31‧‧‧溝槽柵極 31‧‧‧ trench gate
32‧‧‧柵極絕緣層 32‧‧‧Gate insulation
40‧‧‧體區 40‧‧‧ body area
41‧‧‧離子注入區 41‧‧‧Ion implantation zone
45‧‧‧源極區域 45‧‧‧Source area
50‧‧‧介電層 50‧‧‧Dielectric layer
60‧‧‧溝道 60‧‧‧Channel
71‧‧‧肖特基結 71‧‧‧Schottky knot
72‧‧‧歐姆結 72‧‧‧ Ohm knot
80‧‧‧連接金屬層 80‧‧‧Connected metal layer
90‧‧‧間隔層 90‧‧‧ spacer
100‧‧‧n+底部襯底 100‧‧‧n+ bottom substrate
200‧‧‧n-外延層 200‧‧‧n-epitaxial layer
310‧‧‧溝槽柵極 310‧‧‧Tray gate
320‧‧‧柵極絕緣層 320‧‧‧Gate insulation
400‧‧‧p型體區 400‧‧‧p type body area
第1圖是現有技術提供的功率MOSFET裝置的結構剖視圖;第2圖是本發明一種功率MOSFET裝置在實施例1中的結構剖視圖;第3圖是本發明一種功率MOSFET裝置的製造方法在實施例1中的步驟流程圖;第4圖至第7圖是本發明一種功率MOSFET裝置的製造方法在實施例1中的步驟示意圖;第8圖是本發明一種功率MOSFET裝置的製造方法在實施例2中的步驟示意圖;第9圖至第12圖是本發明一種功率MOSFET裝置的製造方法在實施例2中的步驟示意圖。。 1 is a cross-sectional view showing a structure of a power MOSFET device provided by the prior art; FIG. 2 is a cross-sectional view showing a structure of a power MOSFET device according to the present invention; and FIG. 3 is a view showing a method of manufacturing a power MOSFET device according to the present invention. 1 is a flow chart of steps in FIG. 4; FIG. 4 is a schematic diagram showing steps of a method for manufacturing a power MOSFET device according to the present invention; and FIG. 8 is a manufacturing method of a power MOSFET device according to the present invention. FIG. 9 to FIG. 12 are schematic diagrams showing the steps of the manufacturing method of a power MOSFET device according to the present invention in Embodiment 2. .
以下結合附圖說明本發明的多項實施方式。 Various embodiments of the present invention are described below in conjunction with the drawings.
實施例1 Example 1
如第2圖所示是本發明一種功率MOSFET裝置的結構剖視圖,以n溝道的該功率MOSFET裝置為例,其包含一n+重摻雜的底部襯底10和在該底部襯底10上生長的一n-外延層20;開設有若干延伸至外延層20中一定深度的溝槽30,並在其中填充諸如多晶矽的導電材料以形成溝槽柵極31;沿該溝槽柵極31的側壁和底部形成有較薄的氧化物,作為柵極絕緣層32將溝槽柵極31與外延層20絕緣隔離。 FIG. 2 is a cross-sectional view showing the structure of a power MOSFET device of the present invention. The n-channel power MOSFET device is exemplified, and includes an n+ heavily doped underlying substrate 10 and grown on the underlying substrate 10. An n- epitaxial layer 20; a plurality of trenches 30 extending to a certain depth in the epitaxial layer 20 are formed, and a conductive material such as polysilicon is filled therein to form the trench gate 31; along the sidewall of the trench gate 31 A thinner oxide is formed on the bottom and the trench gate 31 is insulated from the epitaxial layer 20 as the gate insulating layer 32.
在外延層20的頂部、圍繞溝槽柵極31還形成有p型的體區40,p型的體區40頂部還通過離子注入形成有n++型的源極區域45;該體區40、源極區域45通過柵極絕緣層32與溝槽柵極31絕緣隔離。在外延層20、溝槽柵極31和源極區域45的頂部表面還沉積有由低溫氧化物和硼磷矽玻璃構成的介電層50,用於隔絕溝槽柵極31與源極區域45的接觸。 At the top of the epitaxial layer 20, a p-type body region 40 is further formed around the trench gate 31. The top of the p-type body region 40 is further formed with an n++ type source region 45 by ion implantation; the body region 40, the source The pole region 45 is insulated from the trench gate 31 by a gate insulating layer 32. A dielectric layer 50 composed of a low temperature oxide and borophosphon glass is also deposited on the top surface of the epitaxial layer 20, the trench gate 31 and the source region 45 for isolating the trench gate 31 and the source region 45. s contact.
貫穿介電層50開設有若干接觸溝道60,其一直延伸至體區40中,使接觸溝道60的底部角落被p型的體區40包圍。體區40中還通過離子注入形成有n-漂移區25,使接觸溝道60的底部中間區域通過該漂移區25與n-外延層20接觸,並在該接觸溝道60的底部中間與漂移區25連接的位置沉積第一介面勢壘導電材料(簡稱第一導電材料)形成肖特基結71。 A plurality of contact trenches 60 are formed through the dielectric layer 50, extending all the way into the body region 40 such that the bottom corners of the contact trenches 60 are surrounded by the p-type body regions 40. An n-drift region 25 is also formed in the body region 40 by ion implantation, so that the bottom intermediate portion of the contact channel 60 is in contact with the n- epitaxial layer 20 through the drift region 25, and drifts in the middle of the bottom portion of the contact channel 60. A first interface barrier conductive material (abbreviated as a first conductive material) is deposited at a location where the regions 25 are connected to form a Schottky junction 71.
在介電層50的頂部表面、接觸溝道60的側壁和其底部角落區域的表面、以及肖特基結71上,還沉積有第二介面勢壘導電材料(簡稱第二導電材料),其在接觸溝道60的側壁和其底部角落區域與p型體區20接觸形成歐姆結72。在第二導電材料上還設置有連接金屬層80,其填滿接觸溝道60且延伸至介電層50的頂面上方。 A second interface barrier conductive material (abbreviated as a second conductive material) is further deposited on a top surface of the dielectric layer 50, a surface of the sidewall of the contact trench 60 and a bottom corner region thereof, and a Schottky junction 71. An ohmic junction 72 is formed in contact with the p-body region 20 at the sidewall of the contact channel 60 and its bottom corner region. Also disposed on the second conductive material is a tie metal layer 80 that fills the contact channel 60 and extends over the top surface of the dielectric layer 50.
上述分別形成肖特基結71和歐姆結72的介面勢壘導電材料,是功函數不同的兩種金屬。在接觸溝道60側面和底部角落位置,沉積高功函數的金屬與重摻雜p型的體區40接觸形成歐姆結72;本實施例中,例如可使用功函數5.65eV的白金Pt,或者功函數5.15eV的鎳Ni,或者二矽化鎢WSi2等金屬來製成所述的歐姆結72,使形成的歐姆結72電阻更小。 The above-mentioned interface barrier conductive materials respectively forming the Schottky junction 71 and the ohmic junction 72 are two metals having different work functions. At the side and bottom corner positions of the contact channel 60, a metal having a high work function is deposited in contact with the heavily doped p-type body region 40 to form an ohmic junction 72; in this embodiment, for example, a platinum Pt having a work function of 5.65 eV may be used, or A nickel such as a 5.15 eV work function or a metal such as tungsten germanium WSi2 is used to form the ohmic junction 72, so that the formed ohmic junction 72 has a lower resistance.
而在接觸溝道60的底部中間位置,則使用功函數適中的金屬與輕摻雜n-型的漂移區25接觸形成肖特基結71;本實施例中,例如可使 用功函數4.33eV的鈦Ti,或者功函數4.25eV的鉭Ta等金屬來製成該肖特基結71,使形成的肖特基結71的整流效果更好。 At the intermediate position of the bottom of the contact channel 60, the metal having a moderate work function is used to contact the lightly doped n-type drift region 25 to form the Schottky junction 71; in this embodiment, for example, The Schottky junction 71 is made of a titanium Ti having a work function of 4.33 eV or a metal such as 钽Ta having a work function of 4.25 eV, so that the rectifying effect of the formed Schottky junction 71 is better.
如第7圖所示,在一些更好的實施例中,還可以在p型的體區40中設置環繞上述歐姆結72形成的B+硼p-型離子注入區41,使接觸溝道60的底部角落被B+硼p-型離子注入區41包圍。 As shown in FIG. 7, in some preferred embodiments, a B+ boron p-type ion implantation region 41 formed around the ohmic junction 72 may be disposed in the p-type body region 40 to contact the channel 60. The bottom corner is surrounded by a B+ boron p-type ion implantation region 41.
以下結合第3圖至第7圖說明上述設置有B+硼p-型離子注入區41的功率MOSFET裝置的製造方法,其中第3圖是該製造方法的步驟流程圖。 The method of manufacturing the power MOSFET device provided with the B+ boron p-type ion implantation region 41 described above will be described below with reference to FIGS. 3 to 7, and FIG. 3 is a flow chart showing the steps of the manufacturing method.
首先在步驟a中,在n+重摻雜的底部襯底10上生長形成一n-外延層20;步驟b,在n-外延層20的表面上形成一由二氧化矽構成的溝槽30掩模,並以非等向性(anis-tropically)蝕刻在穿過該溝槽30掩模後將n-外延層20蝕刻至預設深度,形成若干溝槽30;沿溝槽30的側壁和底部,通過標準的犧牲氧化層生長和蝕刻工序,形成通常由氧化物構成的柵極絕緣層32;在溝槽30內的剩餘空間中以及二氧化矽溝槽30掩模上沉積n+摻雜多晶矽以形成溝槽柵極31;再對二氧化矽溝槽30掩模上的n+摻雜多晶矽進行回蝕刻,並剝離該溝槽30掩模。 First, in step a, an n- epitaxial layer 20 is grown on the n+ heavily doped underlying substrate 10; in step b, a trench 30 composed of hafnium oxide is formed on the surface of the n- epitaxial layer 20. Mode, and anisotropically etching the n- epitaxial layer 20 to a predetermined depth after passing through the trench 30 mask to form a plurality of trenches 30; along the sidewalls and bottom of the trench 30 Forming a gate insulating layer 32 generally composed of an oxide by a standard sacrificial oxide layer growth and etching process; depositing n+ doped polysilicon in the remaining space in the trench 30 and on the ceria trench 30 mask to A trench gate 31 is formed; the n+ doped polysilicon on the mask of the ceria trench 30 is etched back, and the trench 30 mask is stripped.
步驟c至步驟d中,在所述的n-外延層20的頂部部分通過p-離子注入和擴散形成p-體區40,之後通過n離子注入,在p-體區40中圍繞溝槽30的柵極絕緣層32形成n++的源極區域45。步驟e,在溝槽柵極31、n-外延層20及n++源極區域45上還沉積有低溫氧化物和硼磷矽玻璃的介電層50,用於與溝槽柵極31的絕緣隔離。步驟f中,通過刻蝕貫穿介電層50和源極區域45生成若干接觸溝道60,使接觸溝道60底部延伸至p型體區40中。 In steps c to d, the p-body region 40 is formed by p-ion implantation and diffusion at the top portion of the n- epitaxial layer 20, and then the trench 30 is surrounded in the p-body region 40 by n ion implantation. The gate insulating layer 32 forms a source region 45 of n++. Step e, a dielectric layer 50 of low temperature oxide and borophosphon glass is deposited on the trench gate 31, the n- epitaxial layer 20 and the n++ source region 45 for isolation from the trench gate 31 . In step f, a plurality of contact trenches 60 are formed through the dielectric layer 50 and the source region 45 by etching, such that the bottom of the contact trench 60 extends into the p-type body region 40.
如第4圖所示,步驟g通過傾斜p-型離子注入方式在p型體區40中形成圍繞接觸溝道60側壁及底部的B+硼P-型離子注入區41,以強化p-型的特性,確實地將接觸溝道60底部包圍在B+硼P-型離子注入區41中。 As shown in FIG. 4, step g forms a B+ boron P-type ion implantation region 41 surrounding the sidewalls and the bottom of the contact channel 60 in the p-type body region 40 by oblique p-type ion implantation to enhance the p-type. Characteristic, the bottom of the contact channel 60 is surely surrounded by the B+ boron P-type ion implantation region 41.
如第5圖所示,步驟h中通過化學氣相沉積(CVD)的方法,沉積如SiO2或SiN等絕緣材料形成間隔層90,並在垂直方向通過非等向性幹刻後,使剩餘的間隔層90覆蓋在介電層50及接觸溝道60的側壁、 接觸溝道60的底部角落位置,但是使得接觸溝道60的底部中間區域的表面露出。 As shown in FIG. 5, in step h, a spacer layer 90 is formed by depositing an insulating material such as SiO2 or SiN by chemical vapor deposition (CVD), and after the anisotropic dry etching in the vertical direction, the remaining The spacer layer 90 covers the sidewalls of the dielectric layer 50 and the contact channel 60, The bottom corner position of the channel 60 is contacted, but the surface of the bottom intermediate portion of the contact channel 60 is exposed.
隨後在步驟i中,將上述間隔層90作為掩膜,在接觸溝道60下方中間位置的體區40中通過磷離子注入和局部反型,將接觸溝道60底部的B+硼P-型離子注入區41和p型體區40阻斷,形成連接n-外延層20的n-漂移區25。由第5圖可見,此時該接觸溝道60底部中間區域與n-漂移區25直接接觸,而接觸溝道60的底部角落則被p型體區40中的B+硼p-型離子注入區41所包圍。 Subsequently, in step i, the spacer layer 90 is used as a mask, and the B+ boron P-type ions at the bottom of the channel 60 are contacted by phosphorus ion implantation and partial inversion in the body region 40 at an intermediate position below the contact channel 60. The implantation region 41 and the p-type body region 40 are blocked to form an n-drift region 25 connecting the n- epitaxial layer 20. As can be seen from FIG. 5, at this time, the middle portion of the bottom of the contact channel 60 is in direct contact with the n-drift region 25, and the bottom corner of the contact channel 60 is surrounded by the B+ boron p-type ion implantation region in the p-type body region 40. Surrounded by 41.
如第6圖所示,在步驟j中同樣利用間隔層90做掩模,在該接觸溝道60底部中間與n-漂移區25連接的位置,沉積第一導電材料與n-漂移區25接觸而形成肖特基結71。如上所述,沉積的第一導電材料是功函數適中的金屬,本實施例中,可使用鈦Ti,或鉭Ta等金屬與來漂移區25接觸形成該肖特基結71,使該肖特基結71的整流效果更好。 As shown in FIG. 6, in step j, spacer layer 90 is also used as a mask, and a first conductive material is deposited in contact with n-drift region 25 at a position intermediate the bottom of contact channel 60 and n-drift region 25. The Schottky junction 71 is formed. As described above, the deposited first conductive material is a metal having a moderate work function. In this embodiment, a Ti or a metal such as tantalum Ta may be used in contact with the drift region 25 to form the Schottky junction 71. The rectifying effect of the base junction 71 is better.
如第7圖所示,步驟k中通過濕法清洗工藝去除絕緣的間隔層90。之後的步驟l中,在介電層50的頂部表面、接觸溝道60的側壁和其底部角落區域的表面、以及肖特基結71上,沉積第二導電材料與p型體區40接觸形成歐姆結72。如上所述,沉積的第二導電材料是高功函數的金屬,本實施例中,可使用白金Pt,或鎳Ni,或二矽化鎢WSi2等金屬來形成該歐姆結72,使該歐姆結72電阻更小。 As shown in Fig. 7, the insulating spacer layer 90 is removed by a wet cleaning process in step k. In the subsequent step 1, a second conductive material is deposited in contact with the p-type body region 40 on the top surface of the dielectric layer 50, the surface of the sidewall of the contact trench 60 and the bottom corner region thereof, and the Schottky junction 71. Ohmic junction 72. As described above, the deposited second conductive material is a high work function metal. In this embodiment, a metal such as platinum Pt, or nickel Ni, or tungsten germanium WSi2 may be used to form the ohmic junction 72 to make the ohmic junction 72. The resistance is smaller.
步驟m中,在第二導電材料上沉積形成連接金屬層80,其填滿接觸溝道60且延伸至介電層50的頂面上方。其餘可按標準程式完成整個設置有B+硼p-型離子注入區41的功率MOSFET裝置的製造。 In step m, a connection metal layer 80 is deposited over the second conductive material that fills the contact trench 60 and extends over the top surface of the dielectric layer 50. The remainder of the fabrication of the power MOSFET device provided with the B+ boron p-type ion implantation region 41 can be completed in a standard manner.
若僅去除上述通過離子注入在p型體區40中形成圍繞接觸溝道60側壁和其底部角落區域的B+硼p-型離子注入區41的步驟g,則該步驟a至步驟f、步驟h至步驟m的工藝流程可同樣適用於製造如第2圖所示不設置B+硼p-型離子注入區41的功率MOSFET裝置。 If only the step g of forming the B+ boron p-type ion implantation region 41 surrounding the sidewall of the contact channel 60 and the bottom corner region thereof in the p-type body region 40 by ion implantation is removed, the step a to the step f, the step h The process flow to step m is equally applicable to the fabrication of a power MOSFET device in which the B+ boron p-type ion implantation region 41 is not provided as shown in FIG.
實施例2 Example 2
如第12圖所示,本實施例中功率MOSFET裝置與實施例1、2中結構相似,即在n溝道的功率MOSFET裝置中,包含一n+的底部 襯底10和在該底部襯底10上的一n-外延層20;若干溝槽30延伸至外延層20中,填充導電材料後形成溝槽柵極31,並設置柵極絕緣層32來與外延層20絕緣隔離。在外延層20的頂部、圍繞溝槽柵極31形成有p型的體區40;p型的體區40頂部還通過離子注入形成有n++型的源極區域45;在外延層20、溝槽柵極31和源極區域45的頂部表面還沉積有低溫氧化物和硼磷矽玻璃的介電層50。介電層50中貫穿開設若干接觸溝道60,使接觸溝道60的底部角落被p型的體區40包圍;而在接觸溝道60下方中間形成有n-漂移區25與外延層20連接,使接觸溝道60的底部中間區域與該n-漂移區25接觸。 As shown in FIG. 12, the power MOSFET device of this embodiment is similar in structure to the first and second embodiments, that is, the n-channel power MOSFET device includes an n+ bottom. a substrate 10 and an n- epitaxial layer 20 on the underlying substrate 10; a plurality of trenches 30 extending into the epitaxial layer 20, filling a conductive material to form a trench gate 31, and providing a gate insulating layer 32 to The epitaxial layer 20 is insulated and isolated. At the top of the epitaxial layer 20, a p-type body region 40 is formed around the trench gate 31; the top of the p-type body region 40 is further formed with an n++ type source region 45 by ion implantation; in the epitaxial layer 20, the trench The top surface of the gate 31 and source region 45 is also deposited with a dielectric layer 50 of low temperature oxide and borophosphon glass. A plurality of contact channels 60 are formed in the dielectric layer 50 such that a bottom corner of the contact channel 60 is surrounded by the p-type body region 40; and an n-drift region 25 is formed in the middle of the contact channel 60 to be connected to the epitaxial layer 20. The bottom intermediate portion of the contact channel 60 is brought into contact with the n-drift region 25.
唯一不同點在於,本實施例中所包含的間隔層具體是沉積並刻蝕形成在上述接觸溝道60側壁和其底部角落區域上的第二導電材料。該導電的間隔層在接觸溝道60側面和底部角落位置,與重摻雜p型的體區40接觸形成的歐姆結72。所述第二導電材料是具有高功函數特性的WSi2(二矽化鎢)、p+多晶矽等等材料,因此其與重摻雜p型的體區40接觸形成的歐姆結72電阻更小。 The only difference is that the spacer layer included in the embodiment specifically deposits and etches a second conductive material formed on the sidewall of the contact channel 60 and the bottom corner region thereof. The electrically conductive spacer layer contacts the heavily doped p-type body region 40 to form an ohmic junction 72 at the side and bottom corners of the contact channel 60. The second conductive material is WSi2 (tungsten tungsten), p+ polysilicon or the like having a high work function characteristic, and thus the ohmic junction 72 formed in contact with the heavily doped p-type body region 40 has a smaller resistance.
在接觸溝道60底部的第二導電材料之間、與n-漂移區25連接的位置沉積有第一導體材料。與上述實施例相同,該第一導體材料是功函數適中的鈦Ti、鉭Ta等金屬,使其與輕摻雜n-型的漂移區25接觸形成的肖特基結71整流特性更好。 A first conductor material is deposited between the second conductive material at the bottom of the contact channel 60 and at a location connected to the n-drift region 25. As in the above embodiment, the first conductor material is a metal such as titanium Ti or tantalum Ta having a moderate work function, and the Schottky junction 71 formed by contact with the lightly doped n-type drift region 25 is better in rectifying characteristics.
覆蓋在接觸溝道60側壁的第二導電材料、以及接觸溝道60底部中間區域的第一導電材料上,還設置有連接金屬層80,其填滿接觸溝道60且延伸至介電層50的頂面上方。 Covering the second conductive material on the sidewall of the contact channel 60 and the first conductive material contacting the bottom region of the bottom of the trench 60, a connection metal layer 80 is also provided which fills the contact trench 60 and extends to the dielectric layer 50. Above the top.
在一些更好的實施例中,還可以在p型的體區40中設置環繞上述歐姆結72形成的B+硼P-型離子注入區41,使接觸溝道60的底部角落區域被B+硼P-型離子注入區41所包圍。 In some preferred embodiments, a B+ boron P-type ion implantation region 41 formed around the ohmic junction 72 may be disposed in the p-type body region 40 such that the bottom corner region of the contact channel 60 is B+ boron P. The -type ion implantation region 41 is surrounded.
以下結合第8圖至第12圖說明上述設置有B+硼P-型離子注入區41的功率MOSFET裝置的製造方法,其中第8圖是該製造方法的步驟流程圖。 The manufacturing method of the power MOSFET device provided with the B+ boron P-type ion implantation region 41 described above will be described below with reference to Figs. 8 to 12, wherein Fig. 8 is a flow chart showing the steps of the manufacturing method.
與實施例1中類似,首先在步驟a中,在n+重摻雜的底部襯底10上生長形成一n-外延層20;步驟b時,在n-外延層20的表面上形 成一由二氧化矽構成的溝槽30掩模,並以非等向性(anis-tropically)蝕刻在穿過該溝槽30掩模後將n-外延層20蝕刻至預設深度,形成若干溝槽30;沿溝槽30的側壁和底部,通過標準的犧牲氧化層生長和蝕刻工序,形成通常由氧化物構成的柵極絕緣層32;在溝槽30內的剩餘空間中以及二氧化矽溝槽30掩模上沉積n+摻雜多晶矽以形成溝槽柵極31;再對二氧化矽溝槽30掩模上的n+摻雜多晶矽進行回蝕刻,並剝離該溝槽30掩模。 Similar to the first embodiment, first in step a, an n- epitaxial layer 20 is grown on the n+ heavily doped underlying substrate 10; in step b, on the surface of the n- epitaxial layer 20 Forming a trench 30 composed of cerium oxide and etching the n- epitaxial layer 20 to a predetermined depth after passing through the mask of the trench 30 by an anis-tropically etching to form a plurality of trenches a trench 30; along the sidewalls and bottom of the trench 30, through a standard sacrificial oxide growth and etching process to form a gate insulating layer 32, typically composed of an oxide; in the remaining space within the trench 30, and in the ruthenium dioxide trench An n+ doped polysilicon is deposited on the trench 30 mask to form the trench gate 31; the n+ doped polysilicon on the mask of the ceria trench 30 is etched back and the trench 30 mask is stripped.
步驟c至步驟d中,在所述的n-外延層20的頂部部分通過p-離子注入和擴散形成p-體區40,之後通過n離子注入,在p-體區40中圍繞溝槽30的柵極絕緣層32形成n++的源極區域45。步驟e,在溝槽柵極31、n-外延層20及n++源極區域45上還沉積有低溫氧化物和硼磷矽玻璃的介電層50,用於與溝槽柵極31的絕緣隔離。步驟f中,通過刻蝕貫穿介電層50和源極區域45生成若干接觸溝道60,使接觸溝道60底部延伸至p型體區40中。 In steps c to d, the p-body region 40 is formed by p-ion implantation and diffusion at the top portion of the n- epitaxial layer 20, and then the trench 30 is surrounded in the p-body region 40 by n ion implantation. The gate insulating layer 32 forms a source region 45 of n++. Step e, a dielectric layer 50 of low temperature oxide and borophosphon glass is deposited on the trench gate 31, the n- epitaxial layer 20 and the n++ source region 45 for isolation from the trench gate 31 . In step f, a plurality of contact trenches 60 are formed through the dielectric layer 50 and the source region 45 by etching, such that the bottom of the contact trench 60 extends into the p-type body region 40.
如第9圖所示,步驟g通過傾斜p-型離子注入方式在p型體區40中形成圍繞接觸溝道60側壁及底部的B+硼p-型離子注入區41,以強化p-型的特性,確實地將接觸溝道60底部包圍在B+硼p-型離子注入區41中。 As shown in FIG. 9, step g forms a B+ boron p-type ion implantation region 41 surrounding the sidewalls and the bottom of the contact channel 60 in the p-type body region 40 by oblique p-type ion implantation to enhance the p-type. Characteristic, the bottom of the contact channel 60 is surely surrounded by the B+ boron p-type ion implantation region 41.
從步驟h開始與上述實施例不同,如第10圖所示,沉積如WSi2(二矽化鎢)或p+多晶矽的第二導電材料作為間隔層,進行非等向性幹刻後,使其覆蓋介電層50及接觸溝道60的側壁、接觸溝道60的底部角落位置,同時使接觸溝道60的底部中間區域的表面露出。該第二導電材料具有高功函數特性,並在接觸溝道60側面和底部角落位置與重摻雜p型的體區40接觸形成歐姆結72。 Starting from step h, unlike the above embodiment, as shown in FIG. 10, a second conductive material such as WSi2 (tungsten tungsten dioxide) or p+ polycrystalline germanium is deposited as a spacer layer, and after anisotropic dry etching, it is covered. The electrical layer 50 and the sidewalls of the contact trench 60, the bottom corner of the contact trench 60, expose the surface of the bottom intermediate region of the contact trench 60. The second electrically conductive material has a high work function characteristic and contacts the heavily doped p-type body region 40 at the side and bottom corners of the contact channel 60 to form an ohmic junction 72.
隨後在步驟i中,將上述第二導電材料作為掩膜,在接觸溝道60下方中間位置的體區40中通過磷離子注入和局部反型,將接觸溝道60底部的B+硼p-型離子注入區41和p型體區40阻斷,形成連接n-外延層20的n-漂移區25。由第10圖可見,此時該接觸溝道60底部中間區域與n-漂移區25直接接觸,而此時接觸溝道60的底部角落則被B+硼p-型離子注入區41所包圍。 Then in step i, the second conductive material is used as a mask, and the B+ boron p-type at the bottom of the contact channel 60 is contacted by phosphorus ion implantation and partial inversion in the body region 40 at the intermediate position below the contact channel 60. The ion implantation region 41 and the p-type body region 40 are blocked to form an n-drift region 25 connecting the n- epitaxial layer 20. As can be seen from Fig. 10, at this time, the middle portion of the bottom of the contact channel 60 is in direct contact with the n-drift region 25, and at this time, the bottom corner of the contact channel 60 is surrounded by the B+ boron p-type ion implantation region 41.
如第11圖所示,步驟j中同樣利用第二導電材料做掩模, 在該接觸溝道60底部中間與n-漂移區25連接的位置,沉積第一導電材料與n-漂移區25接觸而形成肖特基結71。如上所述,沉積的第一導電材料是功函數適中的金屬,本實施例中,可使用鈦Ti,或鉭Ta等金屬與來漂移區25接觸形成該肖特基結71,使該肖特基結71的整流效果更好。 As shown in FIG. 11, the second conductive material is also used as a mask in step j. At a position intermediate the bottom of the contact channel 60 to the n-drift region 25, a first conductive material is deposited in contact with the n-drift region 25 to form a Schottky junction 71. As described above, the deposited first conductive material is a metal having a moderate work function. In this embodiment, a Ti or a metal such as tantalum Ta may be used in contact with the drift region 25 to form the Schottky junction 71. The rectifying effect of the base junction 71 is better.
如第12圖所示,之後的步驟m中沉積形成連接金屬層80,使其覆蓋接觸溝道60側壁的歐姆結72、以及接觸溝道60底部的肖特基結71上,其填滿接觸溝道60且延伸至介電層50的頂面上方。其餘可按標準程式完成整個設置有B+硼p-型離子注入區41的功率MOSFET裝置的製造。 As shown in Fig. 12, in the subsequent step m, a connection metal layer 80 is deposited to cover the ohmic junction 72 contacting the sidewall of the trench 60, and the Schottky junction 71 contacting the bottom of the trench 60, which fills the contact. Channel 60 extends above the top surface of dielectric layer 50. The remainder of the fabrication of the power MOSFET device provided with the B+ boron p-type ion implantation region 41 can be completed in a standard manner.
若僅去除上述通過離子注入在p型體區40中形成圍繞接觸溝道60側壁和其底部角落區域的B+硼p-型離子注入區41的步驟g,則上述工藝流程可同樣適用於製造不設置B+硼p-型離子注入區41的功率MOSFET裝置。 If only the step g of forming the B+ boron p-type ion implantation region 41 surrounding the sidewall of the contact channel 60 and the bottom corner region thereof in the p-type body region 40 by ion implantation is removed, the above process flow can be equally applied to the fabrication. A power MOSFET device of the B+ boron p-type ion implantation region 41 is provided.
本發明中提供的製造方法只要採用與實施例中相反極性的半導體層和摻雜物之後,同樣可適用於P溝道功率MOSFET裝置。 The manufacturing method provided in the present invention is equally applicable to a P-channel power MOSFET device as long as a semiconductor layer and a dopant having opposite polarities as in the embodiment are employed.
綜合上述實施例1、2所述,本發明提供的功率MOSFET裝置及其製造方法,通過沉積高功函數特性的導電材料,使其在接觸溝道60的側壁和底部角落與重摻雜的體區40接觸形成歐姆結72;還通過沉積功函數適中的導電性,使其在接觸溝道60的底部中間區域與輕摻雜的外延層20接觸形成肖特基結71。因而本發明在同一接觸溝道60中通過構造P/N兩種不同類型的矽介面,並和不同功函數的金屬形成歐姆接觸和肖特基接觸,能夠同時發揮歐姆結72電阻小和肖特基結71整流的特性。 In combination with the above embodiments 1 and 2, the power MOSFET device and the method of fabricating the same according to the present invention, by depositing a conductive material having a high work function characteristic, are placed on the sidewalls and bottom corners of the contact channel 60 and the heavily doped body. The region 40 contacts the ohmic junction 72; it also forms a Schottky junction 71 in contact with the lightly doped epitaxial layer 20 at the bottom intermediate portion of the contact channel 60 by depositing a moderate electrical conductivity of the work function. Therefore, in the same contact channel 60, the present invention forms two different types of germanium interfaces of P/N, and forms ohmic contact and Schottky contact with metals of different work functions, which can simultaneously exhibit the small resistance of the ohmic junction 72 and the Schott. The characteristics of the base junction 71 rectification.
另外,接觸溝道60的底部角落由於被體區40或其中的B+硼p-型離子注入區41包圍,能夠在保證肖特基結71的接觸特性同時,有效降低接觸溝道60角落位置的反向漏電流。而且由於肖特基結71被設置在接觸溝道60中間這一單一的矽晶面上,因而對肖特基結71的一致性也能有效提高。 In addition, the bottom corner of the contact channel 60 is surrounded by the body region 40 or the B+ boron p-type ion implantation region 41 therein, which can effectively reduce the contact position of the Schottky junction 71 while effectively reducing the corner position of the contact channel 60. Reverse leakage current. Moreover, since the Schottky junction 71 is disposed on the single twin plane in the middle of the contact channel 60, the uniformity of the Schottky junction 71 can be effectively improved.
儘管本發明的內容已經通過上述優選實施例作了詳細介紹,但應當認識到上述的描述不應被認為是對本發明的限制。在本領域技術人員閱讀了上述內容後,對於本發明的多種修改和替代都將是顯而易見的。因此,本發明的保護範圍應由所附的申請專利範圍來限定。 Although the present invention has been described in detail by the preferred embodiments thereof, it should be understood that the foregoing description should not be construed as limiting. Various modifications and alterations of the present invention will be apparent to those skilled in the art. Therefore, the scope of the invention should be limited by the scope of the appended claims.
10‧‧‧底部襯底 10‧‧‧Bottom substrate
20‧‧‧外延層 20‧‧‧ Epilayer
30‧‧‧溝槽 30‧‧‧ trench
31‧‧‧溝槽柵極 31‧‧‧ trench gate
32‧‧‧柵極絕緣層 32‧‧‧Gate insulation
40‧‧‧體區 40‧‧‧ body area
45‧‧‧源極區域 45‧‧‧Source area
50‧‧‧介電層 50‧‧‧Dielectric layer
60‧‧‧溝道 60‧‧‧Channel
72‧‧‧歐姆結 72‧‧‧ Ohm knot
80‧‧‧連接金屬層 80‧‧‧Connected metal layer
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