CN101465340A - 堆叠式封装结构 - Google Patents

堆叠式封装结构 Download PDF

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CN101465340A
CN101465340A CNA2007101600648A CN200710160064A CN101465340A CN 101465340 A CN101465340 A CN 101465340A CN A2007101600648 A CNA2007101600648 A CN A2007101600648A CN 200710160064 A CN200710160064 A CN 200710160064A CN 101465340 A CN101465340 A CN 101465340A
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packaging body
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connection pads
substrate
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陈建宏
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Powertech Technology Inc
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    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
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    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
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    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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Abstract

本发明涉及一种堆叠式封装结构，包括一第二封装体利用多个第二导电焊球堆叠于一第一封装体上。第一封装体为一球栅阵列封装体且包括：一第一基板，具有一上表面与一下表面；至少一第一芯片设置于第一基板的上表面；多个第一导电接垫设置于第一基板的上表面；以及多个第一导电焊球设置于第一基板的下表面上。第二导电焊球设置于第一导电接垫上。另，第二封装体为一四方扁平无接脚封装体。多个第二导电接垫为矩形且环绕设置于第二封装体底部周缘。多个第二导电焊接部设置于第二导电接垫上凸出第二封装体下表面且第二导电焊球与第二导电焊接部连接。

Description

堆叠式封装结构
技术领域
本发明涉及芯片封装技术，特别是一种堆叠式封装结构。
背景技术
于轻薄短小且多功能的趋势发展下，传统的单芯片封装技术已逐渐无法满足需求。因此，将各种不同功能的芯片利用各种堆叠的封装方式来减少封装体积和封装厚度，即为目前封装技术的发展重点。堆叠式封装(Package on Package，POP)即为其中一种封装技术。
堆叠式封装是将两个独立封装完成的封装体以制程技术加以堆叠。由于两个封装体是分别经封装、测试后，再彼此堆叠黏着在一起。现有的堆叠式封装是以焊锡来电性连接两个封装件。然而，如何克服翘曲时冷接点的问题与提升堆叠式封装产品良率仍是目前极需努力克服的问题。
发明内容
为了解决上述问题，本发明目的之一在于克服现有技术的不足与缺陷，提供一种堆叠式封装结构，利用四方扁平无接脚封装体作为顶部封装体，故其底部的接垫数量少且面积大可增加堆叠式封装的结构强度。
本发明目的之一在于，提出一种堆叠式封装结构，利用四方扁平无接脚封装体作为顶部封装体，于底部的接垫上增加一焊接部凸出于底部表面，除增加堆叠的强度外更可克服翘曲时冷接点的问题。
为了达到上述目的，本发明一实施例提供一种堆叠式封装结构，包括：一第一封装体；多个第二导电焊球；以及一第二封装体。第二封装体利用第二导电焊球堆叠于第一封装体上。其中，第一封装体为一球栅阵列封装体，且第一封装体包括：一第一基板，具有一上表面与一下表面；至少一第一芯片设置于第一基板的上表面；多个第一导电接垫设置于第一基板的上表面；以及多个第一导电焊球设置于第一基板的下表面上。第二导电焊球设置于第一导电接垫上。另，第二封装体为一四方扁平无接脚封装体。多个第二导电接垫环绕设置于第二封装体底部周缘且第二导电接垫为矩形。多个第二导电焊接部设置于第二导电接垫上并凸出第二封装体下表面且第二导电焊球与第二导电焊接部连接。
本发明具有以下有益技术效果：本发明利用四方扁平无接脚封装体作为顶部封装体堆叠于一球栅阵列封装体上。四方扁平无接脚封装体底部的接垫数量少且接垫的面积大。除便于堆叠外，于焊接后可增加堆叠式封装的结构强度。且于四方扁平无接脚封装体底部的接垫上增加一焊接部凸出于底部表面，于堆叠焊接后更可克服翘曲时冷接点的问题。
附图说明
图1所示为根据本发明一实施例的示意图；
图2所示为根据本发明一实施例中的四方扁平无接脚封装体的底部示意图；
图3所示为根据本发明一实施例的示意图；
图4A、图4B与图4C所示为根据本发明实施例中的不同球栅阵列封装体的示意图。
图中符号说明
100  第一封装体
200  第二封装体
10   第一基板
12   第一芯片
14   第一导电接垫
15   第一导电焊接部
16   第一导电焊球
17   第三导电接垫
18   第三导电焊接部
20   第二基板
22   第二芯片
24   第二导电接垫
26   第二导电焊接部
30   第二导电焊球
具体实施方式
图1所示为根据本发明一实施例的示意图，于本实施例中，堆叠式封装结构包括：一第一封装体100；多个第二导电焊球30；以及一第二封装体200。第二封装体100利用第二导电焊球30堆叠于第一封装体100上。
如图1所示，第一封装体100为一球栅阵列封装体。此第一封装体100包括一第一基板10，具有一上表面与一下表面。至少一第一芯片12设置于第一基板10的上表面。多个第一导电接垫14则设置暴露于第一基板10的上表面；以及多个第一导电焊球16设置于第一基板的下表面上。第二导电焊球30设置于第一导电接垫14上。
另，第二封装体200为一四方扁平无接脚封装体。请参照图2，多个第二导电接垫24环绕设置于第二封装体200底部周缘且第二导电接垫24为矩形。请参照图1，于本实施例中，多个第二导电焊接部26设置于第二导电接垫24上。第二导电焊接部26并凸出第二封装体200下表面且第二导电焊球30与第二导电焊接部26连接。
接续上述说明，第二封装体200利用与第二导电焊球30焊接而堆叠于第一封装体100上。由于，第二导电焊接部26凸出第二封装体200下表面，第二导电焊球30包覆导电焊接部26。如此，增加第二导电焊球30与焊接部位的接触面积，故可增加堆叠后的结构强度。
如图1所示，于一实施例中，第二导电焊球30的尺寸大于第一导电焊球16，而第二导电焊球30的高度使第一封装体100与第二封装体200间具有一间隙。另，第一芯片12与第一基板10电性连接且第一封装体100更包含一封装材料(图上未标)用以包覆第一芯片12。
请参照图3，于一实施例中，第二封装体200包括：一第二基板20；第二芯片22；以及一封装材料(图上未标)。第二基板20具有一上表面与一下表面。第二芯片22设置于第二基板20的上表面。第二芯片22与第二基板20电性连接且封装材料包覆第二芯片22。第二导电接垫24环绕设置于第二封装体200底部周缘。第二导电焊接部26则设置于第二导电接垫24上并凸出第二封装体200的下表面。
接续上述说明，第二封装体200利用与第二导电焊球30焊接而堆叠于第一封装体100上。第二导电焊接部26凸出第二封装体200下表面，第二导电焊球30包覆导电焊接部26。此第二导电焊接部26可利用电镀制程直接形成于第二导电接垫24上。第二导电焊接部26与第二导电接垫24亦可为一体成型的结构，于制作第二基板20时所制成。
于一实施例中，第一封装体100可设置多个第一导电焊接部15设置于第一导电接垫14上并凸出第一封装体100上表面。因此，可增加第二导电焊球30与第一封装体100的焊接强度。于另一实施例中，第一封装体100更设置多个第三导电接垫17设置于第一封装体100下表面，且第一导电焊球16与第三导电接垫17连接。又，第一封装体100更可设置多个第三导电焊接部18于第三导电接垫17上并凸出第一封装体100下表面。
如图4A、图4B与图4C所示，于本发明中，第一封装体可为单芯片球栅阵列封装体、多芯片堆叠式球栅阵列封装体、多芯片并排式球栅阵列封装体(图上未示)、覆晶式球栅阵列封装体或开窗型球栅阵列封装体。
综合上述，本发明利用四方扁平无接脚封装体作为顶部封装体堆叠于一球栅阵列封装体上。四方扁平无接脚封装体底部的接垫数量少且接垫的面积大。除便于堆叠外，于焊接后可增加堆叠式封装的结构强度。且于四方扁平无接脚封装体底部的接垫上增加一焊接部凸出于底部表面，于堆叠焊接后更可克服翘曲时冷接点的问题。
以上所述的实施例仅为说明本发明的技术思想及特点，其目的在使本领域技术人员能够了解本发明的内容并据以实施，当不能以之限定本发明的专利范围，即大凡依本发明所揭示的精神所作的均等变化或修饰，仍应涵盖在本发明的专利范围内。

Claims (10)

1.一种堆叠式封装结构，其特征在于，包含：
一第一封装体，其中该第一封装体为一球栅阵列封装体，且该第一封装体包含：
一第一基板，具有一上表面与一下表面；
至少一第一芯片设置于该第一基板的该上表面；
多个第一导电接垫设置于该第一基板的该上表面；以及
多个第一导电焊球设置于该第一基板的该下表面上；
多个第二导电焊球，设置于该些第一导电接垫上；以及
一第二封装体，利用该些第二导电焊球堆叠于该第一封装体上，其中
该第二封装体为一四方扁平无接脚封装体；
多个第二导电接垫环绕设置于该第二封装体底部周缘且该些第二导电接垫为矩形；
多个第二导电焊接部设置于该些第二导电接垫上并凸出该第二封装体下表面；以及
该些第二导电焊球与该些第二导电焊接部连接。
2.如权利要求1所述的堆叠式封装结构，其特征在于，该些第二导电焊球的高度使该第一封装体与该第二封装体间具有一间隙。
3.如权利要求1所述的堆叠式封装结构，其特征在于，该些第二导电焊球包覆该些导电焊接部。
4.如权利要求1所述的堆叠式封装结构，其特征在于，该些第二导电焊球的尺寸大于该些第一导电焊球。
5.如权利要求1所述的堆叠式封装结构，其特征在于，该第一芯片与该第一基板电性连接且该第一封装体更包含一封装材料包覆该第一芯片。
6.如权利要求1所述的堆叠式封装结构，其特征在于，该第一封装体更包含多个第一导电焊接部设置于该些第一导电接垫上并凸出该第一封装体上表面。
7.如权利要求1所述的堆叠式封装结构，其特征在于，该第一封装体为单芯片球栅阵列封装体、多芯片堆叠式球栅阵列封装体、多芯片并排式球栅阵列封装体、覆晶式球栅阵列封装体或开窗型球栅阵列封装体。
8.如权利要求1所述的堆叠式封装结构，其特征在于，该第一封装体更包含多个第三导电接垫设置于该第一封装体下表面且该些第一导电焊球与该些第三导电接垫连接。
9.如权利要求1所述的堆叠式封装结构，其特征在于，该第一封装体更包含多个第三导电焊接部设置于该些第三导电接垫上并凸出该第一封装体下表面。
10.如权利要求1所述的堆叠式封装结构，其特征在于，该第二封装体更包含：
一第二基板，具有一上表面与一下表面；
至少一第二芯片设置于该第二基板的该上表面；以及
一封装材料包覆该第二芯片，其中该些第二导电接垫环绕设置于该第二封装体底部；以及该些第二导电焊接部设置于该些第二导电接垫上并凸出该第二封装体的该下表面。
CNA2007101600648A 2007-12-21 2007-12-21 堆叠式封装结构 Pending CN101465340A (zh)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103972202A (zh) * 2013-01-31 2014-08-06 联想(北京)有限公司 电路装置及pcb板
CN108630626A (zh) * 2017-03-16 2018-10-09 力成科技股份有限公司 无基板封装结构

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103972202A (zh) * 2013-01-31 2014-08-06 联想(北京)有限公司 电路装置及pcb板
CN108630626A (zh) * 2017-03-16 2018-10-09 力成科技股份有限公司 无基板封装结构

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