CN101465305A - Back face metalization technological process and structure for chip low contact resistance - Google Patents
Back face metalization technological process and structure for chip low contact resistance Download PDFInfo
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- CN101465305A CN101465305A CN 200810121915 CN200810121915A CN101465305A CN 101465305 A CN101465305 A CN 101465305A CN 200810121915 CN200810121915 CN 200810121915 CN 200810121915 A CN200810121915 A CN 200810121915A CN 101465305 A CN101465305 A CN 101465305A
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- chip
- contact resistance
- low contact
- silver
- titanium
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/4827—Materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04026—Bonding areas specifically adapted for layer connectors
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- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
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Abstract
The invention provides a chip low contact resistance backside metalized structure, which is characterized in that the structure sequentially comprises silicon, gold arsenic and backside metalized metals. The backside metalized metals can be titanium, nickel or silver; wherein, the metal titanium can be replaced by vanadium or chromium; and the silver can be replaced by gold or gold-attached silver. At the same time, the invention also provides a low contact resistance backside metallization process method which is easy and can effectively reduce the debris and other abnormity of products, improve the operating efficiency and decrease the production costs. At the same time, the invention provides a chip low contact resistance backside metalized structure-related arsenic alloy material, which can greatly reduce costs.
Description
Technical field
The present invention relates to the semiconductor chip manufacturing technology, relate to the chip back metal metallization processes.
Background technology
Back face metalization is a step critical process of making the discrete device chip.At present in more than the N type substrate 1A, the super-current power unit chip, as VDMOS, GTR etc., adopt when the welding encapsulation technology of scolder is arranged, its back metal generally adopts titanium/nickel/silver (also useful chromium/nickel/silver or vanadium/nickel/silver) three-layer metal structural manufacturing process.Because its substrate generally adopts resistivity to be about 10
-2Ω cm mixes the antimony material piece, and its corresponding impurity concentration is about 10
18/ cm
3If directly carry out attenuate, back face metalization after chip manufacturing is finished, because its substrate doping density is not high enough, substrate silicon is difficult to and back metal forms good Ohmic contact, therefore needs to increase the technology of step raising substrate surface impurity concentration usually behind chip thinning.Because the chip front side metal was made and finished this moment, was not suitable for being higher than 500 ℃ of Temperature Treatment, so generally the method that adopts ion to inject is carried out, and there are some problems in the method that adopts ion to inject:
1. technology is more loaded down with trivial details, needs following flow process: the even glue protection-ion in attenuate-front injects-removes photoresist-clean-anneal-evaporation of the cleaning-back side, the back side;
2. production management difficulty, general ion injection-cleaning-operations such as annealing all are device therefors before the front-side metallization, be mainly used in preceding each working procedure processing of front-side metallization, re-use the risk that equipment has bigger intersection to stain before the front-side metallization behind this technological requirement attenuate, if processing cost is sharply increased for avoiding intersecting risk ion injections-cleaning-operations such as the annealing employing special equipment that stains;
3. the ion implantation dosage behind the attenuate requires greater than 10
15/ cm
2, and this moment, chip was thin slice, and heavy dose of injection can make chip that big stress is arranged, and it is unusual to be prone to fragment etc.
Summary of the invention
The present invention is intended to solve the deficiencies in the prior art, and a kind of easy, low cost, low contact resistance of being easy to production management is provided, and is fit to have the chip low contact resistance backside metalized process of the welding procedure of scolder.
The present invention simultaneously also provides a kind of chip low contact resistance backside metalized structure.
A kind of chip low contact resistance backside metalized process comprises the steps:
(1) chip thinning;
(2) carrying out chip back cleans;
(3) gold-plated arsenic on the chip
(4) carry out back face metalization on the chip;
(5) make golden arsenic thin layer and silicon layer form au-si alloy, the metal that forms low contact resistance contacts with silicon.
The metal of described back face metalization can be titanium, nickel, silver; Wherein said Titanium can also replace with vanadium or chromium; Described silver can also replace with the Jin Dynasty, perhaps adds gold on silver.
The operational environment of step (5) is for using N
2The protection or in the environment of vacuum, working temperature is 380 ~ 450 ℃.
A kind of chip low contact resistance backside metalized structure is characterized in that comprising successively silicon, golden arsenic, backside metalized metals.The metal of described back face metalization can be titanium, nickel, silver; Wherein said Titanium can also replace with vanadium or chromium; Described silver can also replace with the Jin Dynasty, perhaps adds gold on silver.
Foregoing invention be particularly useful for 1A above in, the welding procedure that scolder is arranged of high-current device.
A kind of chip low contact resistance backside metalized technology provided by the invention is easy, the fragment etc. that can effectively reduce product is unusual, improve operating efficiency, reduce production costs, a kind of chip low contact resistance backside metalized structure simultaneously provided by the invention adopts arsenic alloy material, can reduce cost greatly.
Description of drawings:
A kind of chip low contact resistance backside metalized structure of Fig. 1
Embodiment
A kind of chip low contact resistance backside metalized process comprises the steps:
(1) chip thinning;
(2) carrying out chip back cleans;
(3) gold-plated arsenic on the chip
(4) carry out back face metalization on the chip;
(5) make golden arsenic thin layer and silicon layer form au-si alloy, the metal that forms low contact resistance contacts with silicon.
The metal of described back face metalization can be titanium, nickel, silver; Wherein said Titanium can also replace with vanadium or chromium; Described silver can also replace with the Jin Dynasty, perhaps adds gold on silver.
A kind of chip low contact resistance backside metalized structure is characterized in that comprising successively silicon, golden arsenic, backside metalized metals.The metal of described back face metalization can be titanium, nickel, silver; Wherein said Titanium can also replace with vanadium or chromium; Described silver can also replace with the Jin Dynasty, perhaps adds gold on silver.The chip low contact resistance backside metalized structure of a kind of golden arsenic, titanium, nickel, silver-colored structure is provided as shown in Figure 1
Be to be understood that to be that the foregoing description is just to explanation of the present invention, rather than limitation of the present invention, anyly do not exceed the replacement of the unsubstantiality in the connotation scope of the present invention or the innovation and creation of modification all fall within the protection range of the present invention.
Claims (4)
1. a chip low contact resistance backside metalized technology is characterized in that comprising the steps:
(1) chip thinning;
(2) carrying out chip back cleans;
(3) gold-plated arsenic on the chip;
(4) carry out back face metalization on the chip;
(5) make golden arsenic thin layer and silicon layer form au-si alloy, the metal that forms low contact resistance contacts with silicon.
2. chip low contact resistance backside metalized technology as claimed in claim 1 is characterized in that the metal of described back face metalization can be titanium, nickel, silver; Wherein said Titanium can also replace with vanadium or chromium; Described silver can also replace with the Jin Dynasty, perhaps adds gold on silver.
3. a chip low contact resistance backside metalized structure is characterized in that comprising successively silicon, golden arsenic, backside metalized metals.
4. golden arsenic chip low contact resistance backside metalized structure as claimed in claim 1 is characterized in that the metal of described back face metalization can be titanium, nickel, silver; Wherein said Titanium can also replace with vanadium or chromium; Described silver can also replace with the Jin Dynasty, perhaps adds gold on silver.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200810121915 CN101465305A (en) | 2008-10-22 | 2008-10-22 | Back face metalization technological process and structure for chip low contact resistance |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200810121915 CN101465305A (en) | 2008-10-22 | 2008-10-22 | Back face metalization technological process and structure for chip low contact resistance |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101465305A true CN101465305A (en) | 2009-06-24 |
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ID=40805797
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200810121915 Pending CN101465305A (en) | 2008-10-22 | 2008-10-22 | Back face metalization technological process and structure for chip low contact resistance |
Country Status (1)
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| CN (1) | CN101465305A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102254843A (en) * | 2011-06-27 | 2011-11-23 | 江阴新顺微电子有限公司 | Method for metalizing back of semiconductor chip applied to eutectic packaging |
| CN103811293A (en) * | 2012-11-07 | 2014-05-21 | 中芯国际集成电路制造(上海)有限公司 | Wafer backside metallization method |
| CN105405772A (en) * | 2015-10-26 | 2016-03-16 | 北京时代民芯科技有限公司 | Diode chip fusion welding method |
| WO2019200515A1 (en) * | 2018-04-16 | 2019-10-24 | 华为技术有限公司 | Chip, chip package structure, and packaging method |
| CN113299621A (en) * | 2020-01-02 | 2021-08-24 | 南京市产品质量监督检验院 | Lightly doped n-type silicon wafer back metallization structure and manufacturing process thereof |
-
2008
- 2008-10-22 CN CN 200810121915 patent/CN101465305A/en active Pending
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102254843A (en) * | 2011-06-27 | 2011-11-23 | 江阴新顺微电子有限公司 | Method for metalizing back of semiconductor chip applied to eutectic packaging |
| CN102254843B (en) * | 2011-06-27 | 2013-01-09 | 江阴新顺微电子有限公司 | Method for metalizing back of semiconductor chip applied to eutectic packaging |
| CN103811293A (en) * | 2012-11-07 | 2014-05-21 | 中芯国际集成电路制造(上海)有限公司 | Wafer backside metallization method |
| CN103811293B (en) * | 2012-11-07 | 2016-08-03 | 中芯国际集成电路制造(上海)有限公司 | The metallized method of wafer rear |
| CN105405772A (en) * | 2015-10-26 | 2016-03-16 | 北京时代民芯科技有限公司 | Diode chip fusion welding method |
| CN105405772B (en) * | 2015-10-26 | 2018-09-11 | 北京时代民芯科技有限公司 | A kind of diode chip for backlight unit fusion welding method |
| WO2019200515A1 (en) * | 2018-04-16 | 2019-10-24 | 华为技术有限公司 | Chip, chip package structure, and packaging method |
| CN111886684A (en) * | 2018-04-16 | 2020-11-03 | 华为技术有限公司 | Chip, chip packaging structure and packaging method |
| CN111886684B (en) * | 2018-04-16 | 2022-08-09 | 华为技术有限公司 | Chip, chip packaging structure and packaging method |
| CN113299621A (en) * | 2020-01-02 | 2021-08-24 | 南京市产品质量监督检验院 | Lightly doped n-type silicon wafer back metallization structure and manufacturing process thereof |
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Open date: 20090624 |