CN101449375B - 用于集成电路封装中的无导线连接的设备、***和方法 - Google Patents
用于集成电路封装中的无导线连接的设备、***和方法 Download PDFInfo
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- CN101449375B CN101449375B CN2006800547303A CN200680054730A CN101449375B CN 101449375 B CN101449375 B CN 101449375B CN 2006800547303 A CN2006800547303 A CN 2006800547303A CN 200680054730 A CN200680054730 A CN 200680054730A CN 101449375 B CN101449375 B CN 101449375B
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Abstract
本发明的一些实施例包括支座和附着到所述支座的至少一个管芯之间的连接结构。所述管芯包括位于所述管芯的表面上的若干管芯接合焊盘。所述连接结构包括多个通孔和沟槽组合。在所述通孔和沟槽组合中形成导电材料,以提供所述管芯接合焊盘和所述支座上的接合焊盘之间的连接器。还描述了其他实施例,并要求对其进行保护。
Description
技术领域
本发明的实施例涉及集成电路封装,具体而言,涉及集成电路封装中的布线连接。
背景技术
计算机和电子装置往往包括集成电路(IC)封装。IC封装通常可以具有安装在IC封装的基座或支座上的管芯。所述管芯可以包括用于执行电学功能的电路。
一些IC封装具有耦合在管芯和支座之间的金线或铜线,从而允许将电信号传送到管芯中的电路以及允许将电信号从管芯中的电路传出。
在一些情况下,太多的导线可能导致不应有的信号干扰,提高布线材料成本,增加用于保护导线的封装尺寸,增大在导线当中发生短路的可能性,以及使制造过程复杂化。
附图说明
图1到图3示出根据本发明的实施例的包括具有连接结构的管芯的设备;
图4示出根据本发明的另一实施例的包括具有连接结构的管芯的设备;
图5到图7示出根据本发明的实施例的包括具有连接结构的管芯叠置体的设备;
图8到图14示出用于形成根据本发明的实施例的连接结构的各个过程;
图15是示出根据本发明的实施例的方法的流程图;
图16示出根据本发明的实施例的***。
具体实施方式
图1到图3示出根据本发明的实施例的包括具有连接结构110的管芯101的设备100。图1基于沿图2所示的设备100的顶视平面图的剖面线1-1的截面示出了设备100的截面。图3是示出了通孔和沟槽组合的细节的设备100的一部分的三维图。图1和图2中的设备100的管芯101可以包括用于执行诸如处理器、存储装置、通信装置或其的一些组合的半导体装置的功能的电路。设备100可以是IC封装的一部分。在一些实施例中,设备100可以存在于诸如计算机或蜂窝电话的***或装置中。在图1中,连接结构110使得能够将信号传送到管芯101以及能够将信号从管芯101传出。
为了清晰起见,在通过截面图示出本文所述的一些特征(例如,图1中的管芯101)时,可以采用实线而不是剖面线符号(交叉阴影线)描绘所述特征。同样为了清晰起见,在通过平面图示出本文所述的一些特征(例如,图2中的管芯101)时,可以采用实线而不是隐线符号(虚线)描绘所述特征。在图1中,设备100包括将管芯101附着到支座120的附着物131。附着物131可以包括粘合剂材料。支座120可以是IC封装的基板,设备100可以位于所述IC封装中。如图1到图3所示,连接结构110包括覆盖管芯101的至少一部分的电介质层199、通孔141、通孔148、沟槽147以及连接器150,所述连接器150具有导电段151、导电段158以及桥接导电段151和158的导电段157。
图3是示出了在形成图1中的连接器150之前的通孔和沟槽的组合的细节的设备100的部分133的三维图,所述组合包括通孔141和148以及沟槽147。在形成连接器150之后(图1),连接器150的导电材料填充通孔141和148以及沟槽147。在一些实施例中,连接器150的导电材料包括金属。连接器150将位于管芯101的表面104上的管芯接合焊盘111耦合到支座120的表面124上的支座接合焊盘128,从而允许电信号在管芯接合焊盘111和支座接合焊盘128之间传送。支座接合焊盘128可以耦合到其他部件,从而允许信号在管芯101中的电路和其他部件之间传送。
如图2所示,管芯101包括位于表面104上的若干个管芯接合焊盘111,支座120包括位于表面124上的若干支座接合焊盘128。图2中的管芯接合焊盘111和支座接合焊盘128的数量和布局只是作为例子示出。在一些实施例中,管芯接合焊盘111和支座接合焊盘128的数量和布局可以与图2中不同。例如,管芯101和支座120可以只在两个边上具有接合焊盘,而不是如图2所示那样在所有四个边上都具有接合焊盘。
图2示出了管芯接合焊盘111和支座接合焊盘128中的每一个的直径大于通孔141和148中的每一个的直径的例子。在一些实施例中,管芯接合焊盘111和支座接合焊盘128中的每一个的直径可以小于或等于通孔141和148中的每一个的直径。
图1示出了电介质层199的表面114,其相对于支座120的表面124成一定的角度,使得沟槽147和导电段也相对于支座120的表面124成一定的角度。在一些实施例中,电介质层199的表面114基本上平行于支座120的表面124,使得沟槽147和导电段也基本上平行于支座120的表面124。
图4示出了根据本发明的另一实施例的具有连接结构410的设备400。如图4所示,连接结构410包括表面414,其基本上平行于支座420的表面424,使得沟槽447和连接器450的导电段457也基本平行于支座420的表面424。
图5到图7示出了根据本发明的实施例的具有管芯叠置体570和连接结构510的设备500。图5基于沿图6所示的设备500的顶视平面图的剖面线5-5的截面示出了设备500的截面。图7是示出了通孔和沟槽组合的细节的设备500的一部分的三维图。设备500可以是IC封装的一部分。
如图5所示,管芯叠置体570包括在支座520上以叠置的形式设置的管芯501、502和503。管芯501、502和503包括相应的管芯接合焊盘511、512和513。附着物531、532和533使管芯501、502和503彼此附着,并将其附着到支座520。连接结构510包括覆盖管芯501、502和503的至少一部分的电介质层599以及连接器550,所述连接器550包括耦合到管芯接合焊盘511、512、513和位于支座520的表面524上的支座接合焊盘528的导电段551、552、553、557和558。在通孔和沟槽的组合中形成导电段551、552、553、557和558,在图7中将其详细示出。图7示出了形成图5中的连接器550之前的通孔和沟槽组合,其包括通孔541、542、543和548以及沟槽547。在形成连接器550之后(图5),连接器550的导电材料填充通孔541、542、543和548,以形成导电段551、552、553和558。连接器550的导电材料还填充沟槽547,以形成桥接导电段551、552、553和558的导电段557。图5示出了包括三个管芯的设备500的例子。在一些实施例中,设备500的管芯的数量可以发生变化。例如,设备500的管芯的数量可以是两个或超过三个。
图8到图14示出了用于形成根据本发明的实施例的连接结构的各个过程。
图8示出了具有叠置在支座820上的管芯801、802和803的管芯叠置体870。管芯801、802和803包括相应的管芯接合焊盘811、812和813。支座820包括位于支座表面824上的支座接合焊盘828。管芯叠置体870可以包括处于管芯之间以及处于管芯和支座820之间的附着物(例如,粘合剂)。从图8中省略了所述附着物。在一些实施例中,管芯801、802和803中的一个或多个可以具有独立的小于300μm(微米)的管芯厚度。在一些实施例中,管芯801、802和803的相对较小的管芯厚度可以促进根据本文所述的连接结构的形成。
图9示出了形成在管芯801、802和803以及形成在支座820的表面部分821上的电介质层899。如图9所示,电介质材料899覆盖管芯801、802和803以及支座部分821。可以通过在管芯801、802和803以及在支座820的支座部分821上沉积电介质材料来形成电介质层899。在一些实施例中,沉积电介质材料以形成电介质层899可以包括利用电介质材料涂覆管芯801、802和803以及支座部分821。在其他实施例中,沉积电介质材料以形成电介质层899可以包括利用电介质材料对管芯801、802和803以及支座部分821进行成型。也可以采用其他技术来形成电介质层899。
图10示出了形成在电介质层899中的若干通孔841、842、843和848。通孔841、842、843和848基本垂直于基板表面824。如图10所示,在管芯接合焊盘811、812和813以及支座接合焊盘828上形成通孔841、842、843和848,以提供至管芯接合焊盘811、812和813以及支座接合焊盘828中的每一个的通路。所述通路允许在随后的过程中实现与管芯接合焊盘811、812、813和支座接合焊盘828的连接。在一些实施例中,可以通过向电介质层899施加激光来形成通孔841、842、843和848。在其他实施例中,可以通过对电介质层899进行机械钻孔来形成通孔841、842、843和848。例如,可以使用钻头对电介质层899进行钻孔,以形成通孔841、842、843和848。在其他一些实施例中,可以采用光刻技术去除(例如,通过蚀刻)电介质层899的部分,以形成通孔841、842、843和848。可以采用其他技术来形成通孔841、842、843和848。
图11是在形成通孔841、842、843和848之后的电介质层899的一部分的三维图。
图12示出了形成在电介质层899中以及形成在通孔841、842、843和848上的沟槽847。通孔841、842、843和848以及沟槽847形成通孔和沟槽组合。在一些实施例中,可以通过向电介质层899施加激光来形成沟槽847。在其他实施例中,可以通过对电介质层899进行机械钻孔来形成沟槽847。例如,可以使用钻头对电介质层899进行钻孔,以形成沟槽847。在其他一些实施例中,可以采用光刻技术去除电介质层899的部分,以形成沟槽847。可以采用其他技术来形成沟槽847。
图12还示出了这样的例子,其中引入焊球1266使得可以将焊球1266置于沟槽847中,或者置于通孔841、842、843和848中,或者既置于沟槽847中又置于通孔841、842、843和848中。随后的过程可以使焊球1266熔化,从而使焊球1266可以填充通孔841、842、843和848以及沟槽847,以形成导电连接。在一些实施例中,不是将焊球1266而是可以将具有除球状以外的其他形状的焊接材料置于沟槽847中。随后的过程可以使所述焊接材料熔化,从而使所述焊接材料可以填充通孔841、842、843和848以及沟槽847,以形成导电连接。
在图11和图12所示的过程中,可以采用以下技术中的一项或多项来形成通孔841、842、843和848以及沟槽847:激光、机械钻孔和光刻。
图13示出了形成通孔841、842、843和848以及沟槽847之后的电介质层899。
图14示出了具有连接结构1410的设备1400。连接结构1410包括电介质层899以及将管芯接合焊盘811、812、813耦合到支座接合焊盘828的连接器1450。在一些实施例中,连接器1450可以通过如下方式形成:在沟槽847以及通孔841、842、843和848中放置诸如焊球1266(图12)的焊球,然后使焊球1266熔化,从而使焊球1266可以填充通孔841、842、843和848以及沟槽847,以形成连接器1450。在采用焊球形成连接器1450的实施例中,可以使用助熔剂来处理沟槽847以及通孔841、842、843和848,以改善焊料润湿。在其他实施例中,可以将导电膏放置、印刷或按压到沟槽847以及通孔841、842、843和848上,以形成连接器1450。可以执行导电膏的固化或烘焙。导电膏可以是单一材料或者两种或多种材料的组合。例如,导电膏可以是铜膏、锡膏和银膏的组合、焊膏或者其他导电膏材料。可以采用其他技术来利用导电材料填充沟槽847以及通孔841、842、843和848,以形成连接器1450。如图14所示,连接器1450包括形成在通孔841、842、843和848内并且耦合到管芯接合焊盘811、812和813以及支座接合焊盘828的导电段1451、1452、1453和1458,以及形成在沟槽847中桥接导电段1451、1452、1453和1458的导电段1457。导电段1451、1452、1453和1458可以基本上垂直于支座表面824。图14所示的设备1400可以是IC封装的一部分。
如图8到图14所述,由于在形成连接器1450(图14)之前已经形成了沟槽847以及通孔841、842、843和848(图13),因此可以例如通过同时利用导电材料填充沟槽847以及通孔841、842、843和848而在一个处理步骤(从图13到图14的步骤)中形成连接器1450的导电段1451、1452、1453、1458和1457。在一个处理步骤中或者同时形成导电段1451、1452、1453、1458和1457意味着支座接合焊盘828和管芯接合焊盘811、812和813中的每一个之间的连接并非是在独立的处理步骤中形成的。因此,可以简化或加快或者既简化又加快支座820与管芯801、802和803之间的连接器的制造过程,这样可以降低加工成本。此外,如图1到图14所述和所示,连接器150、450、550和1450不含有导线(无导线),所述导线例如为连接在管芯的接合焊盘和支座或基板之间的常规导线。由此,因为有导线的连接器中的导线材料(例如,金)的成本可能相对高于诸如连接器150、450、550和1450的无导线连接器的材料的成本,所以还可以降低材料成本。
如图1到图14所述,在设备100、400、500和1400中,由于连接器150、450、550和1450未使用导线,因此可以降低与导线有关的寄生电感、电阻、电容或其组合。由此,可以提高设备100、400、500或1400的电性能。此外,诸如如图1到图14所述的连接器150、450、550或1450的连接器可以相对短于具有导线的连接器。因此,与有导线的连接器相比,连接器150、450、550或1450中的电信号延迟可以较小,从而具有设备100、400、500或1400的IC封装中的信号速度可以相对高于具有有导线的连接器的IC封装中的信号速度。此外,由于图1到图14所述的连接器150、450、550或1450不包括导线,因此可以减少由导线导致的短路。因此,在设备100、400、500或1400中,成品率、质量、可靠性及其组合都可以得到提高。
图8到图14所述的过程形成了多个管芯的叠置体和支座之间的连接结构(例如,图5或图14所示的连接结构510或1410)。在一些实施例中,可以采用图8到图14所述的过程形成单个管芯和支座之间的连接结构,例如,图1所示的连接结构110或者图4所示的连接结构410。
图15是示出了根据本发明的实施例的方法1500的流程图。方法1500形成至少一个管芯和附着到所述管芯的支座之间的连接结构。方法1500的动作1510在管芯和支座上形成电介质层。动作1520在所述电介质层中形成通孔和沟槽组合。动作1530在所述通孔和沟槽组合中形成连接器。所述连接器使所述管芯上的管芯接合焊盘与所述支座上的支座接合焊盘耦合。由方法1500形成的连接结构可以包括图1到图14所示的连接结构110、410、510和1410的实施例。方法1500的动作可以包括图1到图14所述的动作或过程。不必按照所示的顺序或者任何特定的顺序来执行方法1500的各个动作。可以重复一些动作,而其他动作可能只发生一次。本发明的各个实施例所具有的动作可以多于或少于图15所示的动作。
图16示出了根据本发明的实施例的***。***1600包括处理器1610、存储装置1620、存储器控制器1630、图形控制器1640、输入和输出(I/O)控制器1650、显示器1652、键盘1654、点击装置1656、***装置1658和总线1660。
处理器1610可以是通用处理器或专用集成电路(ASIC)。存储装置1620可以是动态随机存取存储(DRAM)装置、静态随机存取存储(SRAM)装置、闪速存储装置或者这些存储装置的组合。I/O控制器1650可以包括用于有线通信或无线通信的通信模块。***1600所示的部件中的一个或多个可以包括诸如图1到图14所示的设备100、400、500或1400的设备。***1600所示的部件中的一个或多个可以包含在一个或多个IC封装内。例如,可以使处理器1610、或存储装置1620、或I/O控制器1650的至少一部分或这些部件的组合包含在IC封装内,其中所述IC封装可以包括诸如图1到图14所示的设备100、400、500或1400的设备。由此,***1600所示的部件中的一个或多个可以包括诸如图1到图14所示的连接结构110、410、510或1410的连接结构。
***1600可以包括计算机(例如,台式机、膝上型电脑、手提计算机、服务器、Web设备、路由器等)、无线通信装置(例如,蜂窝电话、无绳电话、寻呼机、个人数字助理等)、计算机相关***设备(例如,打印机、扫描仪、监视器等)、娱乐装置(例如,电视、收音机、立体声***、磁带和光盘播放器、录像机、摄像放像一体机、数字照相机、MP3(运动图像专家组,音频层3)播放器、视频游戏机、手表等)等等。
上述说明和附图给出了本发明的一些具体实施例,其足以使本领域技术人员能够实施本发明的实施例。其他实施例可以包含结构、逻辑、电、处理方面的变化或其他变化。在附图中,采用类似的特征或类似的数字描述若干视图中基本类似的特征。例子只是用来代表可能的变化。一些实施例的部分和特征可以包含在其他实施例的部分或特征中或者将其替代。在阅读并理解了上述说明的情况下,很多其他实施例对于本领域技术人员而言是显而易见的。因此,由权利要求书及其等同范围决定各个实施例的范围。
Claims (23)
1.一种用于集成电路封装中的布线连接的设备,包括:
支座,其包括支座表面和位于所述支座表面上的支座接合焊盘;
第一管芯,其包括管芯表面和位于所述管芯表面上的第一管芯接合焊盘;
位于所述第一管芯之外的电介质层,所述电介质层包括耦合到所述第一管芯接合焊盘和所述支座接合焊盘的通孔和沟槽组合;以及
耦合到所述第一管芯接合焊盘和所述支座接合焊盘的连接器,其中所述连接器包括至少一个处于所述通孔和沟槽组合内的导电段。
2.根据权利要求1所述的设备,其中所述电介质层覆盖所述管芯表面的至少一部分以及所述支座表面的至少一部分。
3.根据权利要求1所述的设备,其中所述通孔和沟槽组合包括:
位于所述电介质层中并且位于所述第一管芯接合焊盘上的第一通孔;
位于所述电介质层中并且位于所述支座接合焊盘上的第二通孔;以及
位于所述电介质层中并且桥接所述第一通孔和所述第二通孔的沟槽。
4.根据权利要求3所述的设备,其中所述第一通孔和所述第二通孔位于所述沟槽和所述支座表面之间。
5.根据权利要求3所述的设备,其中所述连接器包括:
位于所述第一通孔内并且耦合到所述第一管芯接合焊盘的第一导电段;
位于所述第二通孔内并且耦合到所述支座接合焊盘的第二导电段;以及
位于所述沟槽内并且耦合到所述第一和第二导电段的第三导电段。
6.根据权利要求5所述的设备,其中所述第一和第二导电段基本垂直于所述支座表面。
7.根据权利要求6所述的设备,其中所述连接器包括金属。
8.根据权利要求1所述的设备,还包括:
以与所述第一管芯叠置的方式设置的第二管芯,所述第二管芯包括管芯表面和位于所述管芯表面上的第二管芯接合焊盘;
其中所述通孔和沟槽组合还包括位于所述第二管芯接合焊盘上的第三通孔;并且
其中所述连接器还包括位于所述第三通孔内并且耦合到所述第二管芯接合焊盘和所述沟槽内的第三导电段的第四导电段。
9.根据权利要求8所述的设备,其中所述电介质层覆盖所述第二管芯的所述管芯表面的至少一部分。
10.根据权利要求8所述的设备,还包括:
以与所述第一和第二管芯叠置的方式设置的第三管芯,所述第三管芯包括管芯表面和位于所述管芯表面上的第三管芯接合焊盘;
其中所述通孔和沟槽组合还包括位于所述第三管芯接合焊盘上的第四通孔;并且
其中所述连接器还包括位于所述第四通孔内并且耦合到所述第三管芯接合焊盘和所述沟槽内的所述第三导电段的第五导电段。
11.一种用于集成电路封装中的布线连接的***,包括:
集成电路封装,包括:
支座,其包括支座表面和位于所述支座表面上的支座接合焊盘;
第一管芯,其包括管芯表面和位于所述管芯表面上的第一管芯接合焊盘;
位于所述第一管芯之外的电介质层,所述电介质层包括耦合到所述第一管芯接合焊盘和所述支座接合焊盘的通孔和沟槽组合;以及
耦合到所述第一管芯接合焊盘和所述支座接合焊盘的连接器,其中所述连接器包括至少一个处于所述通孔和沟槽组合内的导电段;以及
耦合到所述支座接合焊盘的动态随机存取存储装置。
12.根据权利要求11所述的***,还包括:
以与所述第一管芯叠置的方式设置的第二管芯,所述第二管芯包括管芯表面和位于所述管芯表面上并耦合到所述支座接合焊盘的第二管芯接合焊盘。
13.根据权利要求12所述的***,其中所述通孔和沟槽组合包括:
位于所述电介质层内并且位于所述第一管芯的所述第一管芯接合焊盘上的第一通孔;
位于所述电介质层内并且位于所述第二管芯接合焊盘上的第二通孔;
位于所述电介质层内并且位于所述支座接合焊盘上的第三通孔;以及
位于所述电介质层内并且桥接所述第一、第二和第三通孔的沟槽。
14.根据权利要求13所述的***,其中所述连接器包括:
位于所述第一通孔内并且耦合到所述第一管芯的所述第一管芯接合焊盘的第一导电段;
位于所述第二通孔内并且耦合到所述第二管芯接合焊盘的第二导电段;
位于所述第三通孔内并且耦合至所述支座接合焊盘的第三导电段;以及
位于所述沟槽内并且耦合到所述第一、第二和第三导电段的第四导电段。
15.一种用于集成电路封装中的布线连接的方法,包括:
在至少一个管芯上并且在附着到所述管芯的支座的一部分上形成电介质层;
在所述电介质层中形成多个通孔和沟槽组合,其中所述通孔和沟槽组合中的每一个提供至所述管芯上的多个管芯接合焊盘的通路、以及至所述支座上的多个支座接合焊盘的通路;以及
在所述通孔和沟槽组合中形成多个连接器,其中将所述连接器中的每一个耦合到管芯接合焊盘之一和所述支座接合焊盘之一。
16.根据权利要求15所述的方法,其中在一个处理步骤中形成所述连接器。
17.根据权利要求15所述的方法,其中形成所述通孔和沟槽组合包括:
在所述电介质层中形成第一通孔,以提供至所述多个管芯接合焊盘中的第一管芯接合焊盘的通路;
在所述电介质层中形成第二通孔,以提供至所述多个支座接合焊盘中的第一支座接合焊盘的通路;以及
在所述电介质层中形成沟槽,以桥接所述第一通孔和所述第二通孔。
18.根据权利要求17所述的方法,其中形成所述连接器包括:
利用导电材料填充所述第一和第二通孔以及所述沟槽。
19.根据权利要求17所述的方法,其中形成所述连接器包括:
将导电材料置于所述沟槽中;以及
执行使所述导电材料熔化、使所述导电材料固化以及对所述导电材料进行烘焙中的至少一种。
20.根据权利要求19所述的方法,其中所述导电材料包括焊球和导电膏中的一种。
21.根据权利要求20所述的方法,其中所述导电膏包括铜膏。
22.根据权利要求20所述的方法,其中所述导电膏包括锡膏和银膏的组合。
23.根据权利要求20所述的方法,其中所述导电膏包括焊膏。
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PCT/CN2006/001507 WO2008014633A1 (en) | 2006-06-29 | 2006-06-29 | Apparatus, system, and method for wireless connection in integrated circuit packages |
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Families Citing this family (62)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101313391B1 (ko) | 2004-11-03 | 2013-10-01 | 테세라, 인코포레이티드 | 적층형 패키징 |
US8058101B2 (en) | 2005-12-23 | 2011-11-15 | Tessera, Inc. | Microelectronic packages and methods therefor |
KR101043484B1 (ko) | 2006-06-29 | 2011-06-23 | 인텔 코포레이션 | 집적 회로 패키지를 포함하는 장치, 시스템 및 집적 회로 패키지의 제조 방법 |
US7901989B2 (en) | 2006-10-10 | 2011-03-08 | Tessera, Inc. | Reconstituted wafer level stacking |
US8551815B2 (en) * | 2007-08-03 | 2013-10-08 | Tessera, Inc. | Stack packages using reconstituted wafers |
US7956453B1 (en) * | 2008-01-16 | 2011-06-07 | Amkor Technology, Inc. | Semiconductor package with patterning layer and method of making same |
US8742603B2 (en) * | 2010-05-20 | 2014-06-03 | Qualcomm Incorporated | Process for improving package warpage and connection reliability through use of a backside mold configuration (BSMC) |
US8482111B2 (en) | 2010-07-19 | 2013-07-09 | Tessera, Inc. | Stackable molded microelectronic packages |
US9159708B2 (en) | 2010-07-19 | 2015-10-13 | Tessera, Inc. | Stackable molded microelectronic packages with area array unit connectors |
KR101075241B1 (ko) | 2010-11-15 | 2011-11-01 | 테세라, 인코포레이티드 | 유전체 부재에 단자를 구비하는 마이크로전자 패키지 |
US20120146206A1 (en) | 2010-12-13 | 2012-06-14 | Tessera Research Llc | Pin attachment |
KR101128063B1 (ko) | 2011-05-03 | 2012-04-23 | 테세라, 인코포레이티드 | 캡슐화 층의 표면에 와이어 본드를 구비하는 패키지 적층형 어셈블리 |
US8618659B2 (en) | 2011-05-03 | 2013-12-31 | Tessera, Inc. | Package-on-package assembly with wire bonds to encapsulation surface |
US10388584B2 (en) * | 2011-09-06 | 2019-08-20 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming Fo-WLCSP with recessed interconnect area in peripheral region of semiconductor die |
KR101887084B1 (ko) * | 2011-09-22 | 2018-08-10 | 삼성전자주식회사 | 멀티-칩 반도체 패키지 및 그 형성 방법 |
US8404520B1 (en) | 2011-10-17 | 2013-03-26 | Invensas Corporation | Package-on-package assembly with wire bond vias |
US8946757B2 (en) | 2012-02-17 | 2015-02-03 | Invensas Corporation | Heat spreading substrate with embedded interconnects |
US8372741B1 (en) | 2012-02-24 | 2013-02-12 | Invensas Corporation | Method for package-on-package assembly with wire bonds to encapsulation surface |
US9349706B2 (en) | 2012-02-24 | 2016-05-24 | Invensas Corporation | Method for package-on-package assembly with wire bonds to encapsulation surface |
US8835228B2 (en) | 2012-05-22 | 2014-09-16 | Invensas Corporation | Substrate-less stackable package with wire-bond interconnect |
US9391008B2 (en) | 2012-07-31 | 2016-07-12 | Invensas Corporation | Reconstituted wafer-level package DRAM |
US9502390B2 (en) | 2012-08-03 | 2016-11-22 | Invensas Corporation | BVA interposer |
US8975738B2 (en) | 2012-11-12 | 2015-03-10 | Invensas Corporation | Structure for microelectronic packaging with terminals on dielectric mass |
KR102190382B1 (ko) | 2012-12-20 | 2020-12-11 | 삼성전자주식회사 | 반도체 패키지 |
US8878353B2 (en) | 2012-12-20 | 2014-11-04 | Invensas Corporation | Structure for microelectronic packaging with bond elements to encapsulation surface |
US9136254B2 (en) | 2013-02-01 | 2015-09-15 | Invensas Corporation | Microelectronic package having wire bond vias and stiffening layer |
US8883563B1 (en) | 2013-07-15 | 2014-11-11 | Invensas Corporation | Fabrication of microelectronic assemblies having stack terminals coupled by connectors extending through encapsulation |
US9034696B2 (en) | 2013-07-15 | 2015-05-19 | Invensas Corporation | Microelectronic assemblies having reinforcing collars on connectors extending through encapsulation |
US9023691B2 (en) | 2013-07-15 | 2015-05-05 | Invensas Corporation | Microelectronic assemblies with stack terminals coupled by connectors extending through encapsulation |
CN103441107B (zh) * | 2013-07-24 | 2016-08-10 | 三星半导体(中国)研究开发有限公司 | 半导体封装件及其制造方法 |
US9167710B2 (en) | 2013-08-07 | 2015-10-20 | Invensas Corporation | Embedded packaging with preformed vias |
US9685365B2 (en) | 2013-08-08 | 2017-06-20 | Invensas Corporation | Method of forming a wire bond having a free end |
US20150076714A1 (en) | 2013-09-16 | 2015-03-19 | Invensas Corporation | Microelectronic element with bond elements to encapsulation surface |
US9082753B2 (en) | 2013-11-12 | 2015-07-14 | Invensas Corporation | Severing bond wire by kinking and twisting |
US9087815B2 (en) | 2013-11-12 | 2015-07-21 | Invensas Corporation | Off substrate kinking of bond wire |
US9263394B2 (en) | 2013-11-22 | 2016-02-16 | Invensas Corporation | Multiple bond via arrays of different wire heights on a same substrate |
US9583456B2 (en) | 2013-11-22 | 2017-02-28 | Invensas Corporation | Multiple bond via arrays of different wire heights on a same substrate |
US9379074B2 (en) | 2013-11-22 | 2016-06-28 | Invensas Corporation | Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects |
US9583411B2 (en) | 2014-01-17 | 2017-02-28 | Invensas Corporation | Fine pitch BVA using reconstituted wafer with area array accessible for testing |
US9305866B2 (en) * | 2014-02-25 | 2016-04-05 | International Business Machines Corporation | Intermetallic compound filled vias |
US9214454B2 (en) | 2014-03-31 | 2015-12-15 | Invensas Corporation | Batch process fabrication of package-on-package microelectronic assemblies |
US10381326B2 (en) | 2014-05-28 | 2019-08-13 | Invensas Corporation | Structure and method for integrated circuits packaging with increased density |
US9646917B2 (en) | 2014-05-29 | 2017-05-09 | Invensas Corporation | Low CTE component with wire bond interconnects |
US9412714B2 (en) | 2014-05-30 | 2016-08-09 | Invensas Corporation | Wire bond support structure and microelectronic package including wire bonds therefrom |
US9735084B2 (en) | 2014-12-11 | 2017-08-15 | Invensas Corporation | Bond via array for thermal conductivity |
JP6560496B2 (ja) * | 2015-01-26 | 2019-08-14 | 株式会社ジェイデバイス | 半導体装置 |
US9888579B2 (en) | 2015-03-05 | 2018-02-06 | Invensas Corporation | Pressing of wire bond wire tips to provide bent-over tips |
US9502372B1 (en) | 2015-04-30 | 2016-11-22 | Invensas Corporation | Wafer-level packaging using wire bond wires in place of a redistribution layer |
US9761554B2 (en) | 2015-05-07 | 2017-09-12 | Invensas Corporation | Ball bonding metal wire bond wires to metal pads |
US10504736B2 (en) * | 2015-09-30 | 2019-12-10 | Texas Instruments Incorporated | Plating interconnect for silicon chip |
US9490222B1 (en) | 2015-10-12 | 2016-11-08 | Invensas Corporation | Wire bond wires for interference shielding |
US10490528B2 (en) | 2015-10-12 | 2019-11-26 | Invensas Corporation | Embedded wire bond wires |
US10332854B2 (en) | 2015-10-23 | 2019-06-25 | Invensas Corporation | Anchoring structure of fine pitch bva |
US10181457B2 (en) | 2015-10-26 | 2019-01-15 | Invensas Corporation | Microelectronic package for wafer-level chip scale packaging with fan-out |
US9911718B2 (en) | 2015-11-17 | 2018-03-06 | Invensas Corporation | ‘RDL-First’ packaged microelectronic device for a package-on-package device |
US9659848B1 (en) | 2015-11-18 | 2017-05-23 | Invensas Corporation | Stiffened wires for offset BVA |
US10122420B2 (en) * | 2015-12-22 | 2018-11-06 | Intel IP Corporation | Wireless in-chip and chip to chip communication |
US9984992B2 (en) | 2015-12-30 | 2018-05-29 | Invensas Corporation | Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces |
US9935075B2 (en) | 2016-07-29 | 2018-04-03 | Invensas Corporation | Wire bonding method and apparatus for electromagnetic interference shielding |
US10299368B2 (en) | 2016-12-21 | 2019-05-21 | Invensas Corporation | Surface integrated waveguides and circuit structures therefor |
JP2022002249A (ja) * | 2020-06-19 | 2022-01-06 | キオクシア株式会社 | 半導体装置およびその製造方法 |
JP2022129462A (ja) * | 2021-02-25 | 2022-09-06 | キオクシア株式会社 | 半導体装置および半導体装置の製造方法 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6326244B1 (en) * | 1998-09-03 | 2001-12-04 | Micron Technology, Inc. | Method of making a cavity ball grid array apparatus |
CN1381889A (zh) * | 2002-05-23 | 2002-11-27 | 威盛电子股份有限公司 | 集成电路封装及其制作工艺 |
US6506633B1 (en) * | 2002-02-15 | 2003-01-14 | Unimicron Technology Corp. | Method of fabricating a multi-chip module package |
CN2631038Y (zh) * | 2003-07-29 | 2004-08-04 | 南茂科技股份有限公司 | 裸晶形态的积体电路封装组件 |
US6865084B2 (en) * | 2003-02-07 | 2005-03-08 | Siliconware Precision Industries Co., Ltd. | Thermally enhanced semiconductor package with EMI shielding |
Family Cites Families (36)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4288841A (en) * | 1979-09-20 | 1981-09-08 | Bell Telephone Laboratories, Incorporated | Double cavity semiconductor chip carrier |
CA2089435C (en) * | 1992-02-14 | 1997-12-09 | Kenzi Kobayashi | Semiconductor device |
US5648684A (en) * | 1995-07-26 | 1997-07-15 | International Business Machines Corporation | Endcap chip with conductive, monolithic L-connect for multichip stack |
US6492719B2 (en) * | 1999-07-30 | 2002-12-10 | Hitachi, Ltd. | Semiconductor device |
US5994781A (en) | 1997-05-30 | 1999-11-30 | Tessera, Inc. | Semiconductor chip package with dual layer terminal and lead structure |
US6313522B1 (en) * | 1998-08-28 | 2001-11-06 | Micron Technology, Inc. | Semiconductor structure having stacked semiconductor devices |
JP2001085361A (ja) * | 1999-09-10 | 2001-03-30 | Oki Electric Ind Co Ltd | 半導体装置およびその製造方法 |
US6376904B1 (en) * | 1999-12-23 | 2002-04-23 | Rambus Inc. | Redistributed bond pads in stacked integrated circuit die package |
US20020074637A1 (en) * | 2000-12-19 | 2002-06-20 | Intel Corporation | Stacked flip chip assemblies |
JP4780844B2 (ja) * | 2001-03-05 | 2011-09-28 | Okiセミコンダクタ株式会社 | 半導体装置 |
SG106054A1 (en) * | 2001-04-17 | 2004-09-30 | Micron Technology Inc | Method and apparatus for package reduction in stacked chip and board assemblies |
US7042073B2 (en) * | 2001-06-07 | 2006-05-09 | Renesas Technology Corp. | Semiconductor device and manufacturing method thereof |
US6787916B2 (en) * | 2001-09-13 | 2004-09-07 | Tru-Si Technologies, Inc. | Structures having a substrate with a cavity and having an integrated circuit bonded to a contact pad located in the cavity |
TW510034B (en) * | 2001-11-15 | 2002-11-11 | Siliconware Precision Industries Co Ltd | Ball grid array semiconductor package |
EP1455392A4 (en) | 2001-12-07 | 2008-05-07 | Fujitsu Ltd | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME |
TW559337U (en) | 2001-12-07 | 2003-10-21 | Siliconware Precision Industries Co Ltd | Semiconductor packaging apparatus having heat dissipation structure |
US6642081B1 (en) * | 2002-04-11 | 2003-11-04 | Robert Patti | Interlocking conductor method for bonding wafers to produce stacked integrated circuits |
US6682955B2 (en) * | 2002-05-08 | 2004-01-27 | Micron Technology, Inc. | Stacked die module and techniques for forming a stacked die module |
SG142115A1 (en) * | 2002-06-14 | 2008-05-28 | Micron Technology Inc | Wafer level packaging |
US7361533B1 (en) | 2002-11-08 | 2008-04-22 | Amkor Technology, Inc. | Stacked embedded leadframe |
US6905914B1 (en) | 2002-11-08 | 2005-06-14 | Amkor Technology, Inc. | Wafer level package and fabrication method |
US7371975B2 (en) * | 2002-12-18 | 2008-05-13 | Intel Corporation | Electronic packages and components thereof formed by substrate-imprinting |
WO2004064159A1 (ja) * | 2003-01-15 | 2004-07-29 | Fujitsu Limited | 半導体装置及び三次元実装半導体装置、並びに半導体装置の製造方法 |
JP4537702B2 (ja) * | 2003-12-26 | 2010-09-08 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
JP4361826B2 (ja) * | 2004-04-20 | 2009-11-11 | 新光電気工業株式会社 | 半導体装置 |
US7199466B2 (en) * | 2004-05-03 | 2007-04-03 | Intel Corporation | Package design using thermal linkage from die to printed circuit board |
US8552551B2 (en) * | 2004-05-24 | 2013-10-08 | Chippac, Inc. | Adhesive/spacer island structure for stacking over wire bonded die |
US20050258527A1 (en) * | 2004-05-24 | 2005-11-24 | Chippac, Inc. | Adhesive/spacer island structure for multiple die package |
JP4558413B2 (ja) * | 2004-08-25 | 2010-10-06 | 新光電気工業株式会社 | 基板、半導体装置、基板の製造方法、及び半導体装置の製造方法 |
WO2006114772A1 (en) * | 2005-04-28 | 2006-11-02 | Nxp B.V. | Integrated circuit assembly with passive integration substrate for power and ground line routing on top of an integrated circuit chip |
US7763963B2 (en) * | 2005-05-04 | 2010-07-27 | Stats Chippac Ltd. | Stacked package semiconductor module having packages stacked in a cavity in the module substrate |
TWI284976B (en) * | 2005-11-14 | 2007-08-01 | Via Tech Inc | Package, package module and manufacturing method of the package |
KR100837269B1 (ko) * | 2006-05-22 | 2008-06-11 | 삼성전자주식회사 | 웨이퍼 레벨 패키지 및 그 제조 방법 |
KR101043484B1 (ko) | 2006-06-29 | 2011-06-23 | 인텔 코포레이션 | 집적 회로 패키지를 포함하는 장치, 시스템 및 집적 회로 패키지의 제조 방법 |
KR100827667B1 (ko) * | 2007-01-16 | 2008-05-07 | 삼성전자주식회사 | 기판 내에 반도체 칩을 갖는 반도체 패키지 및 이를제조하는 방법 |
US8937382B2 (en) * | 2011-06-27 | 2015-01-20 | Intel Corporation | Secondary device integration into coreless microelectronic device packages |
-
2006
- 2006-06-29 KR KR1020087029352A patent/KR101043484B1/ko active IP Right Grant
- 2006-06-29 CN CN2006800547303A patent/CN101449375B/zh not_active Expired - Fee Related
- 2006-06-29 US US12/305,965 patent/US8084867B2/en not_active Expired - Fee Related
- 2006-06-29 WO PCT/CN2006/001507 patent/WO2008014633A1/en active Application Filing
-
2011
- 2011-12-22 US US13/335,825 patent/US8513108B2/en active Active
-
2013
- 2013-08-19 US US13/970,241 patent/US8981573B2/en active Active
- 2013-08-19 US US13/970,053 patent/US8963333B2/en active Active
-
2015
- 2015-03-16 US US14/658,743 patent/US9385094B2/en active Active
-
2016
- 2016-06-28 US US15/195,310 patent/US9837340B2/en active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6326244B1 (en) * | 1998-09-03 | 2001-12-04 | Micron Technology, Inc. | Method of making a cavity ball grid array apparatus |
US6506633B1 (en) * | 2002-02-15 | 2003-01-14 | Unimicron Technology Corp. | Method of fabricating a multi-chip module package |
CN1381889A (zh) * | 2002-05-23 | 2002-11-27 | 威盛电子股份有限公司 | 集成电路封装及其制作工艺 |
US6865084B2 (en) * | 2003-02-07 | 2005-03-08 | Siliconware Precision Industries Co., Ltd. | Thermally enhanced semiconductor package with EMI shielding |
CN2631038Y (zh) * | 2003-07-29 | 2004-08-04 | 南茂科技股份有限公司 | 裸晶形态的积体电路封装组件 |
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US9385094B2 (en) | 2016-07-05 |
US9837340B2 (en) | 2017-12-05 |
KR20090007780A (ko) | 2009-01-20 |
US8513108B2 (en) | 2013-08-20 |
US20160379920A1 (en) | 2016-12-29 |
US8963333B2 (en) | 2015-02-24 |
WO2008014633A1 (en) | 2008-02-07 |
CN101449375A (zh) | 2009-06-03 |
US20150187713A1 (en) | 2015-07-02 |
US20100244268A1 (en) | 2010-09-30 |
US8981573B2 (en) | 2015-03-17 |
US20140042639A1 (en) | 2014-02-13 |
US20130334707A1 (en) | 2013-12-19 |
US8084867B2 (en) | 2011-12-27 |
KR101043484B1 (ko) | 2011-06-23 |
US20120108053A1 (en) | 2012-05-03 |
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