CN101405871A - 用于宽禁带功率器件的结终端结构 - Google Patents
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Abstract
本发明公开了用于高电压半导体功率器件的多种结终端结构(10)。该结构(10)特别旨在提供高击穿电压,同时用最少数量的处理步骤构造。RIE蚀刻和/或使用精细地形成图案的网格的注入及退火处理的组合为最大击穿电压提供了理想的放射状梯度。该结构(10)提供了对区域内电导率和电荷密度的控制。这些结构(10)可以有利地应用于所有高电压半导体器件结构(10),但尤其对宽禁带器件有益,因为其具有很高的击穿电场和耗尽层宽度的按比例的尺寸。
Description
背景技术
本发明涉及高电压功率半导体器件中的结终端结构(junctiontermination structure),尤其,涉及用于宽禁带(wide bandgap)功率器件的结终端结构,例如碳化硅、氮化镓、氮化镓铝、氮化镓铟、金刚石器件等。
结终端结构是大多数高电压功率开关器件的一般特征,诸如p-n二极管或肖特基二极管,以及固有地包括一个或多个p-n二极管的双极晶体管、闸流晶体管、功率金属氧化物半导体场效应晶体管(MOSFET)和绝缘栅双极晶体管(IGBT)。这些结构的目的是减少器件边缘处的高电场,以产生较高阻断电压。
标准的方法是增加一个结终端结构,其通过提供场线终止于其上的附加电荷,来减少边缘处的高电场。该电荷一般通过在结面积周围的同心区域注入适当极性的掺杂物来获得,在二极管两端施加高电压时,该结面积被彻底地耗尽。一般使用多达三种这样的注入物,用不同的剂量以进一步减小处在各个区域之间转变时的场尖峰脉冲(field spike)。可选地,一种方法可以注入一组称为保护环(guard ring)的同心环来提供类似的功能。还有另一方法是将掺杂区域蚀刻到一个提供理想剂量的厚度。作为离子注入结构的可选方法,台阶式的同心区域和同心环都可以用此方式蚀刻。
终端结构用于多种器件,如p-n二极管、肖特基二极管和双极晶体管。图1A、1B和1C示出这些器件的典型的垂直结构和终端结构的位置。注意,在这些结构中,终端结构的非蚀刻部分具有极性与基片极性相反的掺杂物。
现有技术包括离子注入和蚀刻结构,具有厚度或剂量可变的同心区域和同心环。图2A和图2B示出三个区域被蚀刻的终端结构的实施例,图2C和图2D示出具有同心环的蚀刻终端的实施例。与图中示意性示出的结构不同,图2A和图2B中的多层结构可以具有可变的蚀刻深度和间距,而图2C和图2D中的同心环结构的非蚀刻部分以及间距可以有可变的宽度。
所有这些方法都得益于具有不同剂量的更多区域,或更合适地,得益于相当复杂且更难控制的控制锥度(taper)。
发明内容
本发明是一种新型的终端结构和制备方法,其提供了高阻断电压,然而却由简单的可控制的方法制备。本发明的特征包括使用精细形成(器件)图案的(或成形的)结构(finely patterned structure),其提供了理想的横向锥度以及电阻性和/或电容性区域的组合,即使存在缺陷或局部击穿时,它们也能够稳定电场。虽然半导体中典型的边缘终端结构的宽度大于耗尽层宽度,精细成形的结构具有比耗尽区的宽度小得多的特征。
本发明的实施例是用于形成在基片上的高电压半导体功率器件的结终端结构,结终端结构包括:围绕器件并与器件的***边缘横向隔开的第一导电终端环;与第一导电环横向向外隔开的第二导电终端环;以及处于器件的***边缘与第一和第二导电环中至少一个之间的电阻互连(resistive interconnection)。
每一个导电环都可以在基片之上的导电层中被成形,器件边缘和环之间的间隙确定其间的横向间距。电阻互连通过部分蚀刻导电层而形成,使得薄导电层具有高薄膜电阻(sheet resistance)。
可选地,导电环和电阻互连都能被离子注入到基片,其中,对于导电环使用较高剂量,而对于电阻互连使用较低剂量。也可以使用两种技术的组合,例如在基片之上的导电层中成形的导电环和具有高薄膜电阻的离子注入的电阻互连的组合。
这种类型的终端结构可以使用在高电压二极管中,但也可使用在包含二极管的其它高电压器件中,包括双极结型晶体管和闸流晶体管、功率MOSFET和IGBT。这种类型的终端结构特别适合于使用包括碳化硅的宽禁带半导体材料来制备半导体功率器件,如包括p-n二极管、肖特基二极管、高电压MOSFET和双极结型晶体管等的功率器件。这样的器件的应用包括功率开关、功率调节、功率转换和功率传输应用。
下面从参考附图开始本发明优选实施例的详细描述,本发明的前述及其它目标、特征和优点将变得更加显而易见。
附图说明
图1A和1B分别是具有传统的边缘终端结构的p-n二极管和肖特基二极管的剖视图。
图1C是具有传统的边缘终端结构的双极晶体管的剖视图。
图2A是传统的蚀刻三个区域的边缘终端结构的俯视图,而图2B是其剖视图。
图2C是具有还被称为保护环的同心环的传统的蚀刻边缘终端结构的俯视图,而图2D是其剖视图。
图3A和图3C是根据本发明的边缘终端结构的具有同心环和放射状电阻连接的两种变体的平面俯视图。
图3B、3D和3E是沿图3A中3B-3B线及沿图3C中3D-3D线和3E-3E线分别截取的局部剖视图。
图4A和图4B是该结构的具有螺旋式电阻连接的两种变体的平面俯视图。
图5A是具有交错(alternating)的导电环和电阻环的结构的俯视图,而图5B和5C是其剖视图。
图6A是具有交错连接的电阻环的结构的俯视图,而图6B是其剖视图。
具体实施方式
根据本发明各个实施例的用于高电压半导体功率器件的结终端结构,包括具有不同注入物剂量或不同蚀刻深度的精细形成(器件)图案的(或成形的)结构(finely patterned structure),其减小了结构中的高电场区域。当精细成形的结构的最小特征尺寸明显小于器件的耗尽层宽度时,本方法愈加有效。一个附加特征是在同心环之间使用高电阻链接(highly resistivelink),该同心环潜在地与不能充分耗尽的区域以及始终耗尽的区域结合。对应于1000V的阻断电压,碳化硅(SiC)阻挡层的一般尺寸是10微米耗尽层,而边缘终端结构则是耗尽层宽度的多倍,即30到100微米。具有较高阻断电压的结构具有较大的耗尽层,也具有较大的边缘终端。因此,理想的最小特征尺寸是大约几微米或更少。
尽管使用有限数量的处理步骤,具有精细成形的网格(mesh)的高电阻率、低电阻率、充分耗尽和部分耗尽的区域的组合,仍然提供了优化结终端结构的灵活性。
如图3A和3B所示,第一类型的结构是具有由同心环14组成的结终端结构12的功率器件10,电阻连接16横跨器件边缘11和每个环之间的间隙18。如图3B、3D和3E所示,可替换的结终端结构22包含环24之间界定短路条26的部分蚀刻区域。如果局部电场高,则这些区域耗尽,从而便于电场线的终止而不产生场尖峰脉冲。
在这些和随后的图中,仅大致地示出功率器件10,其可以为图1A、1B或1C中所示的任何类型的器件,或以上提到的其它器件。通过蚀刻而使一个或多个半导体层成形,例如掺杂外延的碳化硅,以形成器件边缘、环及环之间的间隙和短路条,从而形成器件、环和短路条。在图3A和3B的实施例中,单一掺杂层30显示在基片32上。单一蚀刻便足够使器件边缘和结终端结构成形达到单一的深度,其充分向下蚀刻到基片。
在图3C、3D和3E的实施例中,示出了三个层34、36、38。可以使用多蚀刻步骤,以形成深度不同因而电阻不同的环和短路条。短路条的电导率因而小于环的电导率,即使由电导率相同的材料形成。同样,各层的电导率也可能不同,例如,下层38的电导率比上层或层34、36低,因而提供了在成形结终端结构时的另一控制因素。
可通过改变环和间隙的宽度以及横跨间隙的短路条的宽度和长度,来提供另一控制因素。
因为同心环是连接的,如果没有电流流动,则其电势都相同。然而,由于使用高电阻层,电势将取决于电阻网格与通过基片的漏电流的比率。因为漏电流随着电势穿过耗尽区而快速增加,电流和电压会自然地增加,直到电势变化在所有位置都最小化为止。最小的电阻通路支配了电压分割,而其它区域自然地跟随此支配图案。
进一步的附加过程是将外部环连接到基片。这导致附加电流通过电阻网络,即使在不存在任何漏电流的情况下仍然如此。优点是即使没有任何漏电流,电势也将展开,以及最小化由于局部击穿而引起的任何动态特性。
通过这些不同元件的设计,可进一步期待结构的最佳化和击穿电压的最大化。
另一套结终端结构33、42包括螺旋式电阻连接。图4A所示的实施例可以在如图3B的单层中形成,以及图4B中所示的实施例可在如图3D和3E的多层中形成。本方法为相同薄膜电阻提供了较高的电阻。这些结构允许利用已是器件一部分的层,即使这些层的薄膜电阻低于期望值,仍然可以用同样的处理步骤来成形器件层和电阻螺旋。
图4A所示的结构包括螺旋式电阻连接33,其在中心处与器件连接,从而通过改变宽度和长度可以得到最佳电阻。通过穿过顶部导电层进行部分蚀刻,形成螺旋式短路,从而在螺旋之下留下具有高薄膜电阻的低掺杂薄区域13。区域13可以是在基片上形成的低掺杂外延层。图4B包括同心环42和在区域13上形成的螺旋式电阻连接的组合。选择同心环之间螺旋式短路的宽度和长度,结果形成具有不依赖于顶层10的薄膜电阻的理想电阻的电阻短路。
其它结构包括电阻环,其连接成使得任何电流都必须沿着环的一部分流动,从而提供了理想的高电阻。图5A、5B、5C及图6A和6B示出两个实施例。图5A包括有交错的电阻环52和导电环54的结构;其在蚀刻到不同深度的一层或多层中形成。短路条56连接一对环,而在相隔一个象限处另一短路条58连接下一对环。图6A示出仅具有电阻环62的结构,在环上的交错点处附着有电阻条66,结果在内环和外环之间形成最大电阻。该结构中所有的掺杂层都提供了双重功能,因为其在器件和终端结构的不同部分之间提供了导电通路,并且当高电压施加在器件上时,掺杂层可以被部分或甚至充分地耗尽。耗尽区域包括电场线终止于其上的电荷。正确设计这些电荷的位置和数量以获得电场的逐级锥度,其从器件边缘处的电场最高值到边缘终端结构的外部边缘处的电场最低值。选择使用正如所要求的精细成形的终端结构,有效提供了电阻连接和边缘终端结构的耗尽区内电荷的逐渐变化。通过逐渐改变成形特征的横向宽度和长度,以使其可通过单一蚀刻步骤形成,来获得这种逐渐变化。
可替换结构
虽然所有的附图都采用蚀刻终端结构,也可用离子注入或外延再生长来实现等效的结构。可以在终端结构的顶部沉积其他的结构,如避免表面击穿的绝缘体、过生长的非掺杂碳化硅和/或控制场分布的场板(fieldplate)。半导体可以是任何半导体,其包括GaN、GaAlN、GaInN、金刚石和其它SiC多型体,以及这些或其它材料的混合。表面还可利用诸如热氧化物或氮化物钝化层进行钝化。器件的形状也可以是除圆形以外的形状,还包括椭圆形或圆转角矩形。由于边缘处存在高局部电场,应该避免尖锐转角。
在本发明的各个实施例中描述并举例说明了本发明的原理,显然,在不偏离这样的原理的情况下,可在安排和细节上修改本发明。所有的修改和变化均落在所附权利要求的实质和范围内。
Claims (31)
1.一种用于具有器件边缘的高电压半导体功率器件的结终端结构,其包括:
第一形成(器件)图案的导电结构,其由导电材料形成,并与所述器件边缘隔开,以基本上使所述第一成形的结构与所述器件边缘电绝缘;
第二成形的导电结构,其由导电材料形成,并与所述器件边缘隔开,以基本上使所述第二成形的结构与所述器件边缘电绝缘;以及
至少一个成形的电阻结构,其由电阻材料形成,并在所述器件边缘、所述第一成形的结构和所述第二成形的结构之间延伸,以便电连接所述器件边缘、所述第一成形的结构和所述第二成形的结构。
2.如权利要求1所述的结终端结构,其中,所述至少一个成形的电阻结构被形成,以便在离所述器件边缘第一距离的第一位置处接触所述第一成形的结构,并且在离所述器件边缘第二距离的第二位置处接触所述第二成形的结构,其中,所述第二距离大于所述第一距离。
3.如权利要求1所述的结终端结构,其中,所述成形的电阻结构的电导率小于所述第一和第二成形的导电结构的电导率。
4.一种用于在基片上形成的高电压半导体功率器件的结终端结构,所述结终端结构包括:
第一导电终端环,其围绕所述器件,并与所述器件的***边缘横向隔开;
第二导电终端环,其与所述第一导电环横向向外隔开;以及
电阻互连,其位于所述器件的所述***边缘与所述第一和第二导电环中的至少一个之间。
5.如权利要求4所述的结终端结构,其中,每一个所述导电环在所述基片之上的一个导电层中被成形,其中,所述器件边缘与所述环之间的间隙确定它们之间的横向间距。
6.如权利要求5所述的结终端结构,其中,所述电阻互连成形于所述导电层中。
7.如权利要求6所述的结终端结构,其中,所述导电层具有第一厚度,以及所述电阻互连具有比所述第一厚度小的第二厚度。
8.如权利要求5所述的结终端结构,其中,所述导电环中的一个具有第一厚度,以及另一个环具有比所述第一厚度小的第二厚度。
9.如权利要求4所述的结终端结构,其中,每一个所述导电环以确定它们之间的横向间距的图案通过离子注入到所述基片而形成。
10.如权利要求9所述的结终端结构,其中,所述电阻互连是被离子注入到所述基片的。
11.如权利要求4所述的结终端结构,其中,所述电阻互连是由一系列在所述器件周围以规则间隔隔开的电阻连接条形成的。
12.如权利要求11所述的结终端结构,其中,所述连接条在所述导电环之间对角延伸,以具有一个大于它们之间的横向间距的长度。
13.如权利要求11所述的结终端结构,其中,所述连接条被定位,以使第一短路条在第一位置处使所述器件边缘连接到所述第一导电环,以及第二短路条在第二位置处使所述第一导电环连接到所述第二导电环,所述第二位置在所述器件周围从所述第一位置转移,穿过所述第一和第二连接条,经由所述第一导电环的一段而形成延伸的电阻通路。
14.如权利要求4所述的结终端结构,其中,所述电阻互连包括第三环或位于所述器件边缘、所述第一环和所述第二环中的至少一个之间的第三环的一部分。
15.如权利要求14所述的结终端结构,其中,所述第三环在所述器件边缘、所述第一环和所述第二环中的至少一个之间隔开。
16.如权利要求14所述的结终端结构,其中,第三环定位在与所述器件边缘、所述第一环和所述第二环中的至少一个相邻的邻接关系中。
17.如权利要求4所述的结终端结构,其中,所述功率器件、所述第一和第二导电终端环和所述电阻互连是由宽禁带半导体材料形成的。
18.如权利要求17所述的结终端结构,其中,所述半导体材料包括掺杂碳化硅。
19.如权利要求17所述的结终端结构,其中,所述半导体材料包括在所述掺杂碳化硅的基片上的具有(器件)图案的外延层。
20.一种用于为高电压半导体功率器件形成结终端结构的方法,包括:
提供具有器件边缘的高电压半导体功率器件;
由导电材料形成第一成形的导电结构,以使所述第一成形的导电结构与所述器件边缘隔开,以便基本上使所述第一成形的结构与所述器件边缘电绝缘;
由导电材料形成第二成形的导电结构,以使所述第二成形的导电结构与所述器件边缘隔开,以便基本上使所述第二成形的结构与所述器件边缘电绝缘;以及
由电阻材料形成至少一个成形的电阻结构,使得所述成形的电阻结构在所述器件边缘、所述第一成形的结构和所述第二成形的结构之间延伸,以便电连接所述器件边缘、所述第一成形的结构和所述第二成形的结构。
21.一种制备具有结终端结构的高电压功率半导体器件的方法,包括:
在基片的一个区域上形成高电压功率半导体器件,所述器件具有***边缘;
在所述器件周围形成至少第一和第二导电环,所述第一导电环与所述***边缘隔开,以及所述第二导电环与所述第一导电环隔开;以及
在所述器件的所述***边缘与至少所述第一导电环之间形成电阻互连。
22.如权利要求21所述的方法,其中,形成所述电阻互连,以便提供稳定每一个所述导电环处的电压的导电通路,以及提供能被部分或完全耗尽的掺杂区,使得电场线能在所述耗尽的掺杂区中的电荷上终止。
23.如权利要求22所述的方法,其包括:
在所述基片上沉积预定厚度的掺杂半导体层;
在位于所述基片的所述区域之内的掺杂半导体层之中或之上形成所述器件;以及
在所述掺杂半导体层内蚀刻出一个图案,以界定所述器件的所述***边缘,以及自其隔开的至少第一和第二环。
24.如权利要求23所述的方法,其中,所述图案包括一系列在所述器件周围以规则间隔隔开的电阻连接条。
25.如权利要求24所述的方法,其中,将所述连接条蚀刻到小于所述预定厚度的减小的厚度。
26.如权利要求23所述的方法,其中,将所述第一和第二环中的一个或多个蚀刻到小于所述预定厚度的减小的厚度。
27.如权利要求23所述的方法,其中,所述蚀刻步骤在所述器件、所述第一环和所述第二环之间的至少一个间隙中,蚀刻穿透整个所述掺杂半导体层。
28.如权利要求23所述的方法,其中,所述蚀刻步骤在所述器件、所述第一环和所述第二环之间的至少一个间隙中,蚀刻穿透部分所述掺杂半导体层。
29.一种制备具有结终端结构的高电压功率半导体器件的方法,包括:
在基片的一个区域上形成高电压功率半导体器件,所述器件具有***边缘;
在所述器件周围形成一个电阻区,所述电阻区与所述器件的所述***边缘毗连,以及从所述边缘向外延伸预定距离;以及
在所述器件周围形成连接到所述***边缘的多个导电桥臂,以及所述导电桥臂在所述电阻区上向外延伸。
30.如权利要求29所述的方法,其中,成形所述导电桥臂以形成螺旋的段。
31.如权利要求30所述的方法,包括一个或多个导电环,所述一个或多个导电环在所述器件周围与所述***边缘隔开,并由所述导电桥臂连接到所述器件。
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US8637386B2 (en) | 2009-05-12 | 2014-01-28 | Cree, Inc. | Diffused junction termination structures for silicon carbide devices and methods of fabricating silicon carbide devices incorporating same |
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US8933532B2 (en) | 2011-10-11 | 2015-01-13 | Avogy, Inc. | Schottky diode with buried layer in GaN materials |
US8749015B2 (en) | 2011-11-17 | 2014-06-10 | Avogy, Inc. | Method and system for fabricating floating guard rings in GaN materials |
CN103219898B (zh) * | 2013-04-02 | 2016-06-01 | 苏州博创集成电路设计有限公司 | 具有电流采样和启动结构的半导体装置 |
US9425265B2 (en) | 2013-08-16 | 2016-08-23 | Cree, Inc. | Edge termination technique for high voltage power devices having a negative feature for an improved edge termination structure |
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