CN101375401A - 高单元密度沟槽mosfet中的不同台面尺寸 - Google Patents

高单元密度沟槽mosfet中的不同台面尺寸 Download PDF

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CN101375401A
CN101375401A CNA200780003837XA CN200780003837A CN101375401A CN 101375401 A CN101375401 A CN 101375401A CN A200780003837X A CNA200780003837X A CN A200780003837XA CN 200780003837 A CN200780003837 A CN 200780003837A CN 101375401 A CN101375401 A CN 101375401A
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王�琦
戈登·乔治·西姆
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Fairchild Semiconductor Corp
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Abstract

提供了在保持低闩住基极电阻的同时具有用于高电流承载能力的高单元密度的功率MOSFET的电路、方法、以及设备。一个器件采用具有不同台面(沟槽栅极之间的区)尺寸的多个晶体管单元。在多个较大单元中利用重体蚀刻来减小闩住基极电阻。该蚀刻去除台面区中的硅，随后以低阻抗的铝来代替。没有接受该蚀刻的多个较小单元被用来增加器件的电流能力。通过确保这些单元具有较低BVDSS击穿电压来将雪崩电流导向尺寸较大、闩住基极电阻较低的单元。可通过调整在较宽台面任一侧上的沟槽栅极的临界尺寸或宽度，或通过调整重体蚀刻的深度来改变大单元的BVDSS。

Description

高单元密度沟槽MOSFET中的不同台面尺寸
技术领域
本发明大体涉及功率MOSFET晶体管，以及更具体地，涉及具有多种台面尺寸的功率MOSFET晶体管。
背景技术
对功率MOSFET的使用迅速地变得普遍，由于其被要求用在越来越多的应用中，其普遍性肯定能够在未来几年中广泛传播。但是对这些应用的需求为这些器件的性能增加了负担。因此，需要具有改善了性能的功率MOSFET器件。
在通常的操作期间，当导电时，功率MOSFET通过电感器拉(pull)电流。当功率MOSFET关断时，电感器保持所存储的能量。该所存储的能量产生通过电感器的电流，该电流作为电感器的品质因子或“Q”的函数而随时间减小。当该器件进入雪崩击穿模式时，电流在功率MOSFET中消散。
雪崩电流经由功率MOSFET器件的体二极管(即，其漏极和多个阱区之间的结点)而流经功率MOSFET器件。对于n沟道晶体管，雪崩电流从N型漏极流出，经过P阱，到达重体接触。由于该晶体管被设计为用来处理该电流，所以这种作用是非破坏性的。
但是，如果阱-源极二极管(well-source diode)导通时，可以开始二次寄生双极作用(secondary parasitic bipolar action)。该二次双极作用可导致对器件具有破坏性的击穿(runaway)电流。如果阱电阻很大(即，如果闩住基极电阻太高)，则阱-源极二极管可导通。
因此，期望减小闩住基极电阻以防止二次双极作用。但是，许多减小该电阻的技术导致较大的单元尺寸。较大的单元尺寸减小了能被集成的单元数量，并减小了器件的电流承载能力。
因此，需要的是提供在保持低的闩住基极电阻的同时具有大量单元的功率MOSFET晶体管的电路、方法、以及设备。
发明内容
因此，本发明的多个实施例提供了在保持低闩住基极电阻的同时还具有用于高电流承载能力的高单元密度的功率MOSFET的电路、方法、以及设备。
本发明的示意性实施例采用具有不同台面尺寸的多个晶体管单元。台面是沟槽功率MOSFET晶体管的源极区(即，台面是沟槽栅极之间的区)。尽管其他实施例可使用多于两种尺寸的台面，但一个特定的实施例对其单元使用了两种尺寸的台面。
本发明的特定实施例利用重体蚀刻(heavy body etch)来减小沟槽栅功率MOSFET的闩住基极电阻。该蚀刻去除台面区中的硅，然后以低阻抗的铝来代替。但是重体蚀刻需要的单元尺寸大于高电流承载器件的标准(ideal)。因此，该实施例还利用了未接受该蚀刻的多个较小的台面单元。
这些较小的台面单元具有较高的闩住基极电阻。因此，为防止这些器件发生二次双极击穿，大部分器件的雪崩电流被导向尺寸较大、闩住基极电阻较小的单元。这可通过确保这些单元具有较小的体二极管击穿(BVDSS)电压来实现。具体地，将较大单元的BVDSS制造得足够高以满足任何所需规格，但低于小单元的BVDSS击穿电压。可通过调整较宽台面的任一侧上的沟槽栅极的临界尺寸(CD)或宽度，或通过调整重体蚀刻的深度来改变大单元的BVDSS。
于是，功率MOSFET被设计为具有足够的大单元以处理所需的雪崩电流。于是可以增加提供所需的器件电流承载能力所需要的附加的较小单元的数量。本发明的各种实施例可使用本文中描述的这些或其它特性中的一个或多个。
参照下面的详细描述以及附图可以获得对本发明的本质和优点的更好理解。
附图说明
图1是可以由本发明实施例包括的具有重体接触蚀刻(heavybody contact etch)的晶体管单元的侧视图；
图2是根据本发明实施例的晶体管的侧视图；
图3是根据本发明实施例的相邻的窄和宽晶体管的侧视图；
图4A示出了作为沟槽栅极宽度的函数的器件沟槽深度的变化；
图4B示出了作为沟槽深度的函数的击穿电压的变化；
图5是根据本发明实施例的晶体管的俯视图；
图6是示出设计符合本发明实施例的功率MOSFET器件的方法的流程图；以及
图7是示出设计符合本发明实施例的功率MOSFET器件的方法的另一流程图。
具体实施方式
图1是可以由本发明实施例包括的具有重体接触蚀刻的晶体管单元的侧视图。该器件包括体或本体区(body or bulk region)110、漏极区120、以及源极区130。
一般地，当如图1所示的晶体管导通并导电时，其通过电感器拉电流。当晶体管关断时，存储在电感器中的能量产生流经该器件的电流(此处示为I0)。该电流在体二极管中造成雪崩击穿。在本发明实施例中，该击穿是非破坏性的，并且该晶体管被设计用于处理该电流。
然而，如果闩住基极电阻变得过大，则阱-源极二极管会变成正向偏置并开始传导大量的电流。该二极管起到双极晶体管的射极的作用。由于该二次双极效应而产生的电流不可控并会变得足够大以破坏器件。如图1所示，为防止阱-源极二极管正向偏置，使用减小闩住基极电阻的重体接触蚀刻对器件进行改进。
具体地，通过重体接触蚀刻140去除体区110中的一部分。该方法包括从台面中去除硅材料并以诸如铝的低电阻材料来进行代替。
该方法在减小器件的闩住基极电阻方面效果很好。然而，重体接触蚀刻需要较宽的台面器件，从而减少了给定器件尺寸中单元的总量。但是期望在器件中包括大量的单元以增加其电流承载能力，即，减小其导通电阻。因此，本发明实施例使用与处理电感器关断电流所需一样多的较宽的单元，同时使用附加的较窄单元以增加器件中单元的全部数量以实现低的导通电阻，即，当导通并导电时高的电流承载能力。
图2示出了利用蚀刻的重体的低基极电阻Rbb′的具有两种不同台面尺寸同时还提供了高单元密度的单元结构。该图包括宽单元210和多个较窄单元220。宽单元210中的台面的尺寸大到足以进行重体接触蚀刻，同时小单元220中的台面尺寸小到足以使沟槽密度最大。该结构有如下多个参数：
M：大台面尺寸；
M1：小台面尺寸；
n：每个管芯的大台面的数量；
n1：每个大台面的小台面的数量；
CD：大台面的沟槽开口尺寸；以及
CD1：小台面的沟槽开口尺寸。
此外，当该器件关断时，存储在负载电感器中的能量产生雪崩电流(I0)。存在使该体二极管击穿的两种情况。
在一种情况中，击穿同时发生在宽和窄台面或单元中的体二极管中。由于体二极管的面积，而使流经较大台面的电流将比流经小台面的电流大M/M1倍。为阻止阱-源极二极管导电(以超过0.6伏特的电压正向偏置)，要求小台面的“闩住基极”电阻Rbb′为：
R bb &prime; small < 0.6 ( M M 1 + n 1 ) n I o         [式1]
根据该模型，增加每个管芯的大台面的数量(n)，或增加每个大台面的小台面的数量(n1)，或增加大台面尺寸与小台面尺寸的比率(M/M1)可显著减少小台面中对重体结构的需求。这种减少使得在小台面上的非蚀刻重体结构成为可能以及进一步增加沟槽密度。
在第二种情况(其是对具有该结构的实际器件进行建模的更精确的方法)中，相邻单元屏蔽效应(screening effect)使得首先在大台面区中的体二极管发生击穿。未受钳制的感应电流(I0)主要流经大台面。闩住基极电阻的上限为：
R bb &prime; l arg e < 0.6 n I o       [式2]
主要由每个管芯的大台面的数量和感应电流来确定UIS性能(即，当器件处于雪崩击穿时的性能)，并且UIS性能还在较小的程度上取决于窄或小台面单元的闩住基板电阻。这使得能够通过减少小台面区的间距来进一步增加单元数量。大台面区中的源极230是可选的，这取决于正向电流和UIS需求二者。
为确保雪崩电流主要流经宽单元，尽管宽单元的击穿电压仍需要满足任意适用的BVDSS规格，但宽单元的体二极管的击穿电压应该小于小台面单元的击穿电压。因此，期望大台面二极管的BVDSS是可控制的。
通过改变邻近大台面的沟槽的深度或通过改变蚀刻的重体的深度可以使大台面的体二极管的击穿BVDSS小于小台面的击穿BVDSS。如图3所示，在第一种方法中，可通过改变沟槽开口尺寸(CD)310在相同的沟槽蚀刻下实现大台面沟槽的不同沟槽深度。此外，大台面中的源极320是可选的，这取决于对器件UIS性能和正向电流导电性的需求。
图4A示出了作为沟槽栅极宽度的函数的器件沟槽深度的变化。该图示出：沟槽CD越大，沟槽越浅。如下一幅图所示，由于BVDSS是沟槽深度函数，因此这点很重要。
图4b示出了作为沟槽深度的函数的击穿电压的变化。该图示出了BVDSS怎样随沟槽深度变化。沟槽越浅，击穿电压越高。利用这两种影响关系，可使用邻近大台面的沟槽CD来使大台面体二极管的BVDSS高于规格但低于小台面单元的BVDSS。
在可用于调整BVDSS的第二种方法中，可通过重体蚀刻控制台面上的重体接触的深度。可对大台面上的重体进行蚀刻至该区中的体二极管上发生穿通的深度。这两种方法均可用于确保宽单元承载大部分的雪崩电流。
重体蚀刻的一个缺点在于很难精确控制。但是，在根据本发明的实施例的器件中，具有该蚀刻的单元仅仅是器件中全部数量的单元的一部分。因此，由于重体接触蚀刻引起的Rdson(导通电阻)变化显著的减少。具体地，管芯中的沟槽仅有一小部分(大约(1+n1)-1)具有蚀刻的重体接触，因此，该重体接触引起的变化减小了(1+n1)倍。
在本发明的特定实施例中，由所需的BVDSS确定M(大台面尺寸)和CD(大台面的沟槽开口尺寸)的值。由用于制造源极和重体区的光刻能力和注入能力确定M1(小台面尺寸)的值，其在实际中可体现为所使用的设计准则。利用UIS规格确定n(大台面的数量)的值，即，根据式2需要足够的大台面器件来在不导通源极-阱二极管的情况下处理关断电流。利用导通电阻规格确定n1(每个大台面单元的小台面单元的数量)的值。
在制造该结构的过程中，在光掩模布图上将所需的各种平台和沟槽尺寸图案化，并使用平板印刷/蚀刻技术将其转移到晶片。图5示出了作为实例的具有交替源极或台面尺寸的实际沟槽图案的SEM图像。通过沟槽的蚀刻完成图样化。同样，通过限定较大台面的重体区中的蚀刻接触来使用平板印刷/蚀刻技术来限定所需的蚀刻的重体接触。
图6是示出设计符合本发明的实施例的功率MOSFET器件的方法的流程图。在本实施例中，建立了第一和第二单元类型的物理参数。确定了满足一个或多个电特性所需的每个类型的单元的数量。通过这些确定，可以布置并制造出根据本发明实施例的功率MOSFET。
具体地，在步骤610中确定第一单元类型的物理参数以使第一电特性满足所需规格。在本发明的各个实施例中，这些参数包括但不限于沟槽宽度CD、重体蚀刻深度、台面宽度、或其他物理参数。第一电特性可以是如上如述的BVDSS，或不同的电特性。
在步骤620中，确定第二单元类型的物理参数以使第一电特性不仅满足而且超过所需规格。例如，可将第二单元类型的BVDSS设置为高于第一单元类型的BVDSS，以使第一单元类型承担所有任意关断电流的冲击。
接下来，可以得到第一类型的单元的数量以满足第二要求。例如，可以在步骤630中得到不导通源极-阱二极管来处理关断电流所需的宽单元的数量。在步骤640中，可以确定满足第三要求所需的第二类型的单元的数量。例如，可以得到提供所需导通电阻而额外需要的窄单元的数量。
图7是示出设计符合本发明实施例的功率MOSFET器件的方法的另一流程图。在步骤710中，确定具有第一宽度的单元的参数以使单元的BVDSS超过规格。所得到的参数可包括但不限于沟槽宽度CD、重体蚀刻深度、台面宽度、或其他物理参数。在步骤720中得到具有第二宽度的单元的参数。这些单元具有的BVDSS高于具有第一宽度的单元的BVDSS。一般地，这些参数中的大部分是所使用的处理技术所允许的最小设计准则。
在步骤730中，确定具有无需使源极-阱二极管导通而处理所需的关断电流所需的第一宽度的单元的数量。在步骤740中确定具有满足导通电阻要求所需的第二宽度的附加单元的数量。接下来，可使用该信息来设计和制造根据本发明实施例的功率MOSFET。
为了示出和描述的目的而示出本发明的示意性实施例的上述描述。并不用于穷尽或将本发明限于所描述的形式，并且可以根据上述教导，对本发明进行多种改进和变化。选择并描述这些实施例是为了更好地解释本发明的原理及其实际应用，从而使本领域的其他技术人员能更好利用各种实施例中的发明，并使各种改进适于所预期的特定用途。例如，应该理解，在不背离本发明的情况下，所示和所述结构的掺杂剂极性可以相反和/或各种元素的掺杂浓度可以变化。作为另一个实例，在垂直MOSFET实施例的上下文中示出和描述了本发明，但是本发明的各种实施例可以类似地在其他诸如沟槽栅IGBT、水平沟槽栅MOSFET、以及垂直和水平平面栅MOSFET和IGBT的沟槽栅极结构中实现。此外，可以使用已知的开放式单元(open-cell)或封闭式单元(closed-cell)配置来布置各种晶体管实施例。

Claims (20)

1.一种沟槽栅功率MOSFET器件，包括：
多个第一单元，具有第一单元间距，使用重体蚀刻形成所述多个第一单元；
多个第二单元，具有第二单元间距，所述第二单元间距窄于所述第一单元间距，所述多个第二单元不是使用所述重体蚀刻形成的。
2.根据权利要求1所述的器件，其中，使用所述重体蚀刻来控制所述多个第一单元的体二极管击穿电压。
3.根据权利要求1所述的器件，其中，使用沟槽的宽度来控制所述多个第一单元的体二极管击穿电压。
4.根据权利要求1所述的器件，其中，使用期望的关断电流规格来确定所述多个第一单元中的单元数量。
5.根据权利要求4所述的器件，其中，使用期望的导通电阻来确定所述多个第二单元中的单元数量。
6.根据权利要求1所述的器件，其中，利用最小设计准则确定所述第二间距。
7.一种沟槽栅功率MOSFET器件，包括：
第一沟槽栅极；
第二沟槽栅极，位于距离所述第一沟槽栅极第一距离的位置处；
第三沟槽栅极，位于距离所述第二沟槽栅极第二距离的位置处；
第一体区，包括第一阱并位于所述第一沟槽栅极和所述第二沟槽栅极之间；以及
第二体区，包括第二阱并位于所述第二沟槽栅极和所述第三沟槽栅极之间；
其中，相比于所述第二体区，所述第一体区被处理为具有较低的闩住基极电阻以及漏极-本体击穿电压，以及其中，所述第一距离大于所述第二距离。
8.根据权利要求7所述的器件，其中，使用重体蚀刻处理所述第一体区。
9.一种制造沟槽栅功率MOSFET器件的方法，包括：
使用漏极-本体击穿规格确定宽单元的宽度；
使用漏极-本体击穿规格确定宽单元的沟槽栅极的第一宽度；
使用雪崩电流规格确定所述宽单元的第一数量；
使用设计准则限制确定窄单元的宽度；以及
使用导通电阻规格确定所述窄单元的第二数量。
10.根据权利要求9所述的方法，进一步包括：
布置器件，所述器件包括：
所述第一数量的所述宽单元；以及
所述第二数量的所述窄单元，
其中，所述宽单元由具有所述第一宽度的多个沟槽栅极限定。
11.一种设计沟槽栅功率MOSFET的方法，包括：
确定第一单元类型的第一物理参数以使所述第一单元类型的第一电特性满足第一要求；
确定第二单元类型的第二物理参数以使所述第二单元类型的所述第一电特性超过所述第一单元类型的所述第一电特性；
确定满足第二要求所需的所述第一单元类型的第一数量；以及
确定满足第三要求所需的所述第二单元类型的第二数量。
12.根据权利要求11所述的方法，其中，所述第一物理参数是单元宽度。
13.根据权利要求11所述的方法，其中，所述第一物理参数是重体蚀刻的深度。
14.根据权利要求11所述的方法，其中，所述第一物理参数是沟槽宽度。
15.根据权利要求11所述的方法，其中，所述第一电特性是体二极管击穿电压。
16.根据权利要求11所述的方法，其中，所述第二物理参数是单元宽度。
17.根据权利要求16所述的方法，其中，利用最小设计准则确定所述宽度。
18.根据权利要求11所述的方法，其中，所述第二要求是期望的关断电流规格。
19.根据权利要求11所述的方法，其中，所述第三要求是导通电阻规格。
20.根据权利要求11所述的方法，进一步包括：
布置具有所述第一数量的所述第一单元类型和所述第二数量的所述第二单元类型的器件。
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