CN101339948A - 非易失性存储器件及其制造方法 - Google Patents
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Abstract
本发明涉及非易失性存储器件及其制造方法,该非易失性存储器件包括:有源区,该有源区由形成在衬底中的隔离层限定并且其中在沟道宽度方向上具有凹陷,其中具有凹陷的有源区的上部突出高于隔离层的上部;沿有源区的表面和隔离层的顶表面形成的下绝缘层;在下绝缘层上形成电荷存储层;在电荷存储层上形成的上绝缘层;和在上绝缘层上形成的栅电极。
Description
相关申请
本专利要求2007年7月2日提交的韩国专利申请2007-0066169的优先权,通过引用将其全部内容并入本文。
技术领域
本发明涉及非易失性存储器件及其制造方法,更具体涉及用于存储数据的包括多沟道的非易失性存储器件中的单位单元及其制造方法。
背景技术
近来,对非易失性存储器件的需求增加,与易失性存储器件不同,非易失性存储器件可电编程和擦除而不实施用于周期性重新写入数据的刷新操作,由此实现低功率消耗。为了开发大容量存储器件,用于制造高度集成的非易失性存储器件的研究正在进行中。
对属于非易失性存储器件的快闪存储器件的需求已经增加。在快闪存储器件中的每一个存储单元包括具有水平沟道的栅极,即,在平面水平方向上形成的沟道。当栅极具有水平沟道时,确保了制造的方便。但它事实上不能解决器件设计规则的减小。
例如,在快闪存储器件中,NAND快闪存储器件具有多个存储单元,该存储单元串联连接形成单元串(unit string)。因此,NAND存储器件高度集成到一定程度。然而,通过40nm或更小的工艺技术制造的存储器件具有诸如干涉和干扰的问题,即在单元编程操作过程中邻近单元阈值电压变化的现象,和因此难以通过40nm以下的工艺技术来制造存储器件。
为了最小化在高度集成的存储器件中的干涉和干扰,应尽可能减小存储单元栅极的最终检查临界尺寸(final inspection critical dimension,FICD)。然而,当减小栅极的CD时,产生短沟道效应(SCE)和漏致势垒降低(drain induced barrier lowering,DIBL)效应。而且,随着CD的减小,操作电流降低使得在编程和擦除操作中的操作速度降低,和使得作为在单位存储单元中的介电层电容对单位存储单元的总电容之比的耦合率降低。
发明内容
为了克服上述的问题,本发明提供非易失性存储器件及其制造方法,该方法通过增加有效沟道宽度以解决由于存储器件的高度集成所导致的栅极区域的减小,由此确保操作电流。
根据本发明的第一方面,提供一种非易失性存储器件。该器件包括:有源区,该有源区由形成在衬底中的隔离层限定并且在沟道宽度方向上具有凹陷,其中具有凹陷的有源区的上部突出高于隔离层的上部;沿有源区的表面和隔离层的顶表面形成的下绝缘层;在下绝缘层上形成电荷存储层;在电荷存储层上形成的上绝缘层;和在上绝缘层上形成的栅电极。
根据本发明的第二方面,提供一种非易失性存储器件。该器件包括:有源区,该有源区由形成在衬底中的隔离层限定并且在沟道宽度方向上具有凹陷,其中具有凹陷的有源区的上部突出高于隔离层的上部;沿有源区的表面和隔离层的顶表面形成的隧穿绝缘层(tunneling insulationlayer);在隧穿绝缘层上形成的浮置栅极;在浮置栅极上形成的介电层;和在介电层上形成的控制栅极。
根据本发明的第三方面,提供一种制造非易失性存储器件的方法。该方法包括:形成隔离层以在衬底中限定有源区;在有源区内形成凹陷;通过除去隔离层的一部分以暴露出有源区的内壁和外壁;沿有源区的表面和隔离层的顶表面形成下绝缘层;在下绝缘层上形成电荷存储层;在电荷存储层上形成上绝缘层,和在上绝缘层上形成栅电极。
根据本发明的第四方面,提供一种制造非易失性存储器件的方法。该方法包括:形成隔离层以限定在衬底中的有源区,在有源区内形成凹陷,通过除去隔离层的一部分以暴露出有源区的内壁和外壁,沿有源区的表面和绝缘层的上表面形成隧穿绝缘层,在隧穿绝缘层上形成浮置栅极,在浮置栅极上形成介电层,和在介电层上形成控制栅极。
附图说明
图1为根据本发明的非易失性存储器件的透视图。
图2A为沿图1中的第一虚线I-I′描绘的截面图。
图2B为沿图1中的第二虚线II-II′描绘的截面图。
图3A至3N为制造图1中的非易失性存储器件的方法的透视图。
具体实施方式
本发明的实施方案涉及非易失性存储器件及其制造方法。
参照附图,层和区域的图示厚度被放大以便于说明。当第一层称为在第二层“上”或在衬底“上”时,可表示第一层在第二层或衬底上直接形成,或者也可表示在第一层与第二层或衬底之间可存在第三层。另外,在本发明的全部的不同实施方案中相同或相似的附图标记表示在不同附图中相同或相似的元件。
图1为透视图,说明根据本发明一个实施方案的非易失性存储器件的浮动陷阱(floating trap)型存储器件,即用于在形成于栅电极和衬底之间的绝缘电荷存储层中存储电荷的存储器件。图2A为沿图1中的第一虚线I-I′描绘的截面图。图2B为沿图1中的第二虚线II-II′描绘的截面图。为了解释,随后的描述将集中在确定沟道宽度的存储单元的栅电极上。
参照图1至2B,本发明的非易失性存储器件包括在沟道宽度方向(即X轴)具有凹陷的有源区100B。虽然为了便于描述,在本实施方案中描绘了具有一个凹陷的‘U’型,但是也可形成具有两个凹陷的‘W’型。即,凹陷的数目是不受限制的,可考虑制造过程(即包括曝光过程的掩模过程)来根据有源区100B的线宽合适地进行选择。
通过在衬底100中的隔离层102C将有源区100B限定为在沟道长度方向即Z轴方向上延伸的线型或岛型。当有源区100B限定为线型时,其对应于具有串联连接的存储单元的NAND快闪存储器件。当有源区100B限定为岛型时,其对应于NOR快闪存储器件。隔离层102C的顶表面降低至凹陷底部的水平。隔离层102C的顶表面可高于或低于凹陷的底部并根据目标沟道尺寸而变化。因此,凹陷相对于隔离层102C的上部突出,使得凹陷的侧壁(即在沟道宽度方向上形成的侧壁)也突出被暴露出来。简言之,凹陷的底部以及内和外侧壁用作沟道区,由此形成多沟道。
有源区100B在半导体衬底100中作为单体(Single body)形成或者在单独的半导体层中(未显示)作为形成在衬底100上的单体而形成。半导体衬底100或单独的半导体层可以是硅(Si)或硅锗(SiGe)合金。半导体衬底100或单独的半导体层可以是块状(bulk)衬底或绝缘体上硅(SOI)衬底。
在本实施方案中,非易失性存储器件包括沿有源区100B在沟道宽度的垂直方向上顺序堆叠的下绝缘层108A、电荷储存层109A和上绝缘层110A。上述三层沿着由在有源区100B中的凹陷形成的具有高度差的表面形成。
下绝缘层108A和上绝缘层110A可以是氧化物层,例如氧化硅(SiO2)层或具有比SiO2层更高的介电常数例如高于约3.9的高k膜,其由基于金属氧化物的材料例如氧化铪(HfO2)、氧化锆(ZrO2)和氧化铝(Al2O3)或其堆叠结构中的一种所制成。
电荷存储层109A可以是氮化物层(例如Si3N4层)或能够存储电荷的介电层中的一种,其中所述介电层由例如金属氧化物如氧化铪(HfO2)、氧化锆(ZrO2)、氧化铝(Al2O3)、氧化钽(Ta2O3)和氧化镧(La2O3)制成或由硅酸盐如铪硅氧化物(HfSiOx)、锆硅氧化物(ZrSix)和镧硅氧化物(LaSiOx)制成。其中‘x’是正整数。
而且,在本实施方案中,非易失性存储器件包括在上绝缘层110A上形成的栅电极111B。栅电极111B可包括杂质掺杂的多晶硅层、或由过渡金属、稀土金属及其合金中的一种所制成的层。而且,可在栅电极111B上形成金属氮化物层、金属硅化物层及其堆叠结构中的一种以降低电阻率。金属氮化物层可由氮化钛(TiN)、氮化钽(TaN)和氮化钨(WN)层中的一种所形成。金属硅化物层可以是硅化钛(TiSi2)和硅化钨(WSix)层中的一种。其中‘x’为正整数。
图3A至3N为根据本发明制造图1中的非易失性存储器件的方法的透视图。
参照图3A,在衬底100上沉积硬掩模层101。通过利用低压化学气相沉积(LPCVD)方法来沉积硬掩模层101以最小化在沉积过程中施加于衬底100上的应力。而且,硬掩模层101可以是相对衬底100具有高蚀刻选择性的氮化物层,例如氮化硅(Si3N4)层。
而且,在形成硬掩模层101之前,可在衬底100上形成缓冲层(未显示)以保护衬底100。缓冲层可包括对硬掩模层101具有高蚀刻选择性的材料。例如,当硬掩模层101由Si3N4层形成时,缓冲层可由SiO2层形成。而且,通过使用干氧化、湿氧化或自由基离子的氧化工艺来形成缓冲层。
通过蚀刻硬掩模层101和衬底100的一部分来形成沟槽(未显示)。因此,第一有源区100A在衬底100中限定为线型。
在衬底100上沉积用于绝缘的绝缘层102以填充沟槽。考虑到深宽比,绝缘层102可以由单层或堆叠结构形成。例如,当绝缘层102由单层形成时,可使用对高深宽比的情形具有良好填充特性的高密度等离子体(HDP)层。也可以使用具有绝缘性能的其他基于氧化物的层,例如硼磷硅酸盐玻璃(BPSG)、磷硅酸盐玻璃(PSG)、未掺杂的硅酸盐玻璃(USG)、原硅酸四乙酯(TEOS)、硼硅酸盐玻璃(BSG)层及其堆叠结构中的一种。当绝缘层102具有堆叠结构时,优选顺序堆叠HDP层、旋涂玻璃(SOG)层和HDP层。可使用聚硅氮烷(PSZ)层作为SOG层。
参照图3B,平坦化隔离层102以形成具有与硬掩模层101上表面齐平的上表面的隔离图案102A。此时,利用化学机械抛光(CMP)或毯覆式蚀刻方法例如回蚀刻过程来实施平坦化过程。
参照图3C,除去硬掩模层101以暴露出第一有源区100A。磷酸(H3PO4)溶液可用于该去除过程。
参照图3D,在衬底100上沿着具有高度差的表面形成用于间隔物的绝缘层103。用于间隔物的绝缘层103可以是对隔离图案102A具有高蚀刻选择性的氮化物层,例如Si3N4层。用于间隔物的绝缘层103可以由SiO2层形成。在这种情况下,通过控制在干蚀刻过程中的蚀刻时间在隔离图案102A的内壁上形成间隔物。
参照图3E,实施毯覆式蚀刻过程例如采用等离子体蚀刻***的回蚀刻过程,以蚀刻用于间隔物的绝缘层103。因此,在第一有源区100A的上部上沿着隔离图案102A的内壁形成间隔物103A。
参照图3F,实施利用间隔物103A作为蚀刻阻挡层的蚀刻过程(例如干蚀刻过程)以蚀刻第一有源区100A至一定的深度,形成具有一定深度的‘U’型或‘W’型凹陷104的第二有源区100B。
参照图3G,除去间隔物103A。当间隔物103A为氮化物层时,可利用H3PO4溶液除去间隔物103A。当间隔物103A为氧化物层时,可使用稀HF(DHF)、缓冲HF(BHF)和缓冲氧化物蚀刻剂(BOE)溶液中的一种。当使用H3PO4溶液时,可严重损伤Si层的第二有源区100B。因此,为了最小化第二有源区100B的损伤,优选使用清洗溶液例如DHF、BHF和BOE溶液,因此,优选氧化物层作为间隔物103A。
参照图3H,在衬底100上沉积绝缘层105以完全填充在图3G中显示的凹陷104。绝缘层105可以是HDP、SOG、BPSG、PSG、USG、BSG、TEOS层及其堆叠结构中的一种。
参照图3I,平坦化绝缘层105。可以利用化学机械抛光(CMP)或毯覆式蚀刻方法例如回蚀刻过程来实施平坦化过程。此外,实施平坦化过程,使得绝缘层105的一部分保留在有源区100B上并具有一定的厚度,如图3I中所示,或使得剩余绝缘层105的顶表面与第二有源区100B的突出的壁部分的顶表面对齐。下文中,平坦化过程后的剩余绝缘层105将称为绝缘图案105A。
参照图3J,实施包括光刻胶涂敷、曝光和显影过程的掩模过程以形成光刻胶图案106,暴露出其中将形成栅电极的栅电极形成区域107。
然后,利用光刻胶图案106作为蚀刻掩模实施蚀刻过程以蚀刻隔离图案102A的一部分和埋在栅电极形成区域107中的凹陷104(参照图3G)中的绝缘图案105A的一部分。因此,在第二有源区100B中的凹陷104暴露于栅电极形成区域107中。结果,形成了部分蚀刻的绝缘图案105B和部分蚀刻的绝缘图案102B。
参照图3K,除去光刻胶图案106。可以在等离子体蚀刻***中使用O2等离子体除去光刻胶图案106。
参照图3L,沿衬底100上具有高度差的表面顺序沉积下绝缘层108、电荷存储层109和上绝缘层110。
下绝缘层108A和上绝缘层110A可以是氧化物层,例如氧化硅(SiO2)层或具有比SiO2层更高的介电常数例如高于约3.9的高k膜,其由基于金属氧化物的材料例如氧化铪(HfO2)、氧化锆(ZrO2)和氧化铝(Al2O3)或其堆叠结构中的一种所制成。另外,下绝缘层108和上绝缘层110的每一个均可具有约至约的厚度。
电荷存储层109可以是氮化物层(例如Si3N4层)或能够存储电荷的介电层中的一种,所述能够存储电荷的介电层例如由金属氧化物如HfO2、ZrO2、Al2O3、Ta2O3和La2O3或由硅酸盐层如铪硅氧化物(HfSiOx)、锆硅氧化物(ZrSix)和镧硅氧化物(LaSiOx)制成。其中‘x’是正整数。另外,可通过化学气相沉积(CVD)或原子层沉积(ALD)方法沉积约至约的厚度的电荷存储层109。
随后在上绝缘层110上沉积用于栅电极的导电层111。导电层111可包括掺杂的多晶Si层。或者,导电层111可包括过渡金属和稀土金属及其合金中的一种。例如,利用LPCVD方法沉积掺杂的多晶Si层,其中硅烷(SiH4)气体被用作源气体,磷化氢(PH3)、三氯化硼(BCl3)或乙硼烷(B2H6)气体用作掺杂气体。过渡金属可包括铁(Fe)、钴(Co)、钨(W)、镍(Ni)、钯(Pd)、铂(Pt)、钼(Mo)或钛(Ti)。稀土金属可包括铒(Er)、镱(Yb)、钐(Sm)、钇(Y)、镧(La)、铈(Ce)、铽(Tb)、镝(Dy)、钬(Ho)、铥(Tm)或镥(Lu)。
可在导电层111上形成金属氮化物层、金属硅化物层及其堆叠结构中的一种以降低电阻率。金属氮化物层可由氮化钛(TiN)、氮化钽(TaN)或氮化钨(WN)层中的一种所形成。金属硅化物层可以是硅化钛(TiSi2)或硅化钨(WSix)层中的一种。其中‘x’为正整数。
参照图3M,平坦化导电层111。利用CMP或回蚀刻过程平坦化导电层111。下文中,平坦化的导电层将称为平坦化图案111A。
参照图3N,通过实施包括光刻胶涂敷、曝光和显影过程的掩模过程形成覆盖用于形成栅电极111B(参照图1)的区域的光刻胶图案112。
利用光刻胶图案112作为蚀刻掩模实施蚀刻过程以形成栅电极111B。在蚀刻过程中,位于下方的层也被蚀刻以形成图案化的绝缘层108A、图案化的电荷存储层109A和图案化的上绝缘层110A。然后,除去光刻胶图案112。
利用硅-氧化物-氮化物-氧化物-硅(SONOS)器件作为浮动陷阱型存储器件的例子来描述本发明的实施方案。然而,本发明也可应用于金属-氮化物-氧化物-半导体(MNOS)、金属-氧化铝-氧化物-半导体(MAOS)和金属-氧化铝-半导体(MAS)器件。另外,本发明也可应用于包括快闪存储器件的电荷俘获器件,例如作为在隔离的导电材料(即浮置栅极)中存储电荷的场效应晶体管(FET)的浮置栅极型存储器件。
再次参照图3I,在浮置栅极型存储器件中,沿着具有高度差的衬底100的表面顺序形成隧穿绝缘层、浮置栅极和介电层,而不是下绝缘层108、电荷存储层109和上绝缘层110。栅电极111B用作控制栅极。
根据本发明,在有源区中形成凹陷和暴露凹陷的侧壁以增加沟道长度和沟道宽度。由此,即使由于存储器件的高集成度导致栅极尺寸的减小,但增加了有效沟道宽度,由此可以确保操作电流。
虽然根据具体实施方案描述了本发明,但是对本领域技术人员而言显而易见的是,可以做出各种变化和改变而不脱离如在所附权利要求书中所限定的本发明的精神和范围。
Claims (21)
1.一种非易失性存储器件,包括:
有源区,所述有源区由形成在衬底中的隔离层限定并且在沟道宽度方向具有凹陷,其中具有所述凹陷的所述有源区的上部突出高于所述隔离层的上部;
沿所述有源区的表面和所述隔离层的顶表面形成的下绝缘层;
在所述的下绝缘层上形成的电荷存储层;
在所述电荷存储层上形成的上绝缘层;和
在所述上绝缘层上形成的栅电极。
2.一种非易失性存储器件,包括:
有源区,所述有源区由形成在衬底中的隔离层限定并且在沟道宽度方向具有凹陷,其中具有所述凹陷的所述有源区的上部突出高于所述隔离层的上部;
沿所述有源区的表面和所述隔离层的顶表面形成的隧穿绝缘层;
在所述隧穿绝缘层上形成的浮置栅极;
在所述浮置栅极上形成的介电层;和
在所述介电层上形成的控制栅极。
3.根据权利要求1所述的非易失性存储器件,其中所述凹陷形成为‘U’型或‘W’型。
4.根据权利要求1所述的非易失性存储器件,其中所述有源区在沟道长度方向上限定为线型或岛型。
5.根据权利要求1所述的非易失性存储器件,其中形成所述下绝缘层以接触所述凹陷的内壁、底部和所述有源区的外壁的一部分。
6.根据权利要求1所述的非易失性存储器件,其中所述下绝缘层和所述上绝缘层包括氧化硅(SiO2)层、具有比所述SiO2层更高的介电常数的层、及其堆叠结构中的一种。
7.根据权利要求1所述的非易失性存储器件,其中所述电荷存储层包括氮化物层或基于金属氧化物的层。
8.根据权利要求1所述的非易失性存储器件,其中所述电荷存储层包括硅酸盐层。
9.一种制造非易失性存储器件的方法,所述方法包括:
形成隔离层以在衬底中限定有源区;
在所述有源区中形成凹陷;
通过除去所述隔离层的一部分暴露出所述有源区的内壁和外壁;
沿所述有源区的表面和所述隔离层的顶表面形成下绝缘层;
在所述的下绝缘层上形成电荷存储层;
在所述电荷存储层上形成上绝缘层;和
在所述上绝缘层上形成栅电极。
10.一种制造非易失性存储器件的方法,所述方法包括:
形成隔离层以在衬底中限定有源区;
在所述有源区中形成凹陷;
通过除去所述隔离层的一部分暴露出所述有源区的内壁和外壁;
沿所述有源区的表面和所述隔离层的顶表面形成隧穿绝缘层;
在所述的隧穿绝缘层上形成浮置栅极;
在浮置栅极上形成介电层;和
在所述介电层上形成控制栅极。
11.根据权利要求9所述的方法,其中形成所述隔离层包括:
在所述衬底上形成硬掩模层;
通过蚀刻所述硬掩模层和所述衬底的一部分形成沟槽;和
形成所述隔离层以填充所述沟槽。
12.根据权利要求11所述的方法,其中形成所述凹陷包括:
除去在所述有源区上的所述硬掩模层;
在所述有源区上的所述隔离层的内壁上形成间隔物;
利用所述间隔物作为蚀刻阻挡层来蚀刻所述有源区以形成所述凹陷;和
除去所述间隔物。
13.根据权利要求12所述的方法,其中所述间隔物包括氮化物层或氧化物层。
14.根据权利要求9所述的方法,还包括在暴露出所述有源区的所述内壁和外壁之前沉积绝缘层以填充所述凹陷。
15.根据权利要求14所述的方法,其中暴露出所述有源区的所述内壁和外壁通过下列过程来实施:除去所述隔离层的一部分来暴露出所述有源区的外壁,同时除去所述绝缘层来暴露出所述有源区的内壁。
16.根据权利要求15所述的方法,其中所述绝缘层由与所述隔离层相同的材料制成。
17.根据权利要求9所述的方法,其中所述有源区形成为线型或岛型。
18.根据权利要求9所述的方法,其中所述隔离层包括高密度等离子体(HDP)层或所述HDP层和旋涂玻璃(SOG)层的堆叠结构。
19.根据权利要求9所述的方法,其中所述下绝缘层和所述上绝缘层包括SiO2层、具有比所述SiO2层更高的介电常数的层及其堆叠结构中的一种。
20.根据权利要求9所述的方法,其中所述电荷存储层包括氮化物层或基于金属氧化物的层。
21.根据权利要求9所述的方法,其中所述电荷存储层包括硅酸盐层。
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CN102683350A (zh) * | 2012-04-19 | 2012-09-19 | 北京大学 | 一种电荷俘获存储器 |
CN107293492A (zh) * | 2016-04-11 | 2017-10-24 | 三星电子株式会社 | 半导体器件及其制造方法 |
CN110211963A (zh) * | 2019-06-11 | 2019-09-06 | 南京邮电大学 | 一种mos存储器及制备方法 |
CN111092063A (zh) * | 2018-10-24 | 2020-05-01 | 台湾积体电路制造股份有限公司 | 离子衬底穿孔 |
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- 2007-07-02 KR KR1020070066169A patent/KR100886643B1/ko not_active IP Right Cessation
- 2007-12-27 US US11/965,454 patent/US20090008698A1/en not_active Abandoned
- 2007-12-28 JP JP2007338688A patent/JP2009016784A/ja active Pending
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CN102683350A (zh) * | 2012-04-19 | 2012-09-19 | 北京大学 | 一种电荷俘获存储器 |
CN107293492A (zh) * | 2016-04-11 | 2017-10-24 | 三星电子株式会社 | 半导体器件及其制造方法 |
CN107293492B (zh) * | 2016-04-11 | 2021-10-29 | 三星电子株式会社 | 半导体器件的制造方法 |
CN111092063A (zh) * | 2018-10-24 | 2020-05-01 | 台湾积体电路制造股份有限公司 | 离子衬底穿孔 |
CN111092063B (zh) * | 2018-10-24 | 2023-04-18 | 台湾积体电路制造股份有限公司 | 集成电路及其制造方法 |
CN110211963A (zh) * | 2019-06-11 | 2019-09-06 | 南京邮电大学 | 一种mos存储器及制备方法 |
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JP2009016784A (ja) | 2009-01-22 |
US20090008698A1 (en) | 2009-01-08 |
KR20090002645A (ko) | 2009-01-09 |
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