CN101312132A - 具导脚的多芯片半导体装置及其制法 - Google Patents
具导脚的多芯片半导体装置及其制法 Download PDFInfo
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Abstract
本发明公开了一种具导脚的多芯片半导体装置及其制法,是提供一表面设有多个连接垫(connection pad)的基板,以于该基板表面接置并电性连接多个半导体芯片,并于该基板上形成包覆该半导体芯片且外露出该连接垫的封装胶体,以形成封装单元,另提供一具有多个导脚(leads)的导线架,以将该封装单元外露的连接垫与该导线架的导脚电性连接,从而构成本发明的具导脚的多芯片半导体装置,藉以避免现有技术将基板或导脚整合于封装件中而导致信赖性不良或基板吸湿导致封装件裂损问题。
Description
技术领域
本发明涉及一种半导体装置,特别是涉及一种具导脚的多芯片半导体装置及其制法。
背景技术
传统的导线架型式半导体封装件,例如四方扁平式半导体封装件(Quad Flat Package,QFP),其制作方式是在一具有芯片座(Die Pad)及多个导脚(Lead)的导线架上黏置一芯片,复通过多条焊线(Wire)电性连接该芯片上表面的焊垫(Pad)与其对应的多个导脚,并以一封装胶体包覆该芯片及焊线而形成一导线架型式半导体封装件。相关技术可参见美国专利第5,874,773、6,696,750、6,902,102、及7,057,293号。
另由于电子产品的微小化以及高运行速度需求的增加,而为提高单一半导体封装件的性能与容量以符合电子产品小型化的需求,半导体封装件予以多芯片模块化(Multi-Chip Module,MCM)乃成一趋势,由此将两个或两个以上的半导体芯片组合在单一封装构造中,以缩减整体电路体积,并提升电性功能。
然而受限于传统导线架式半导体封装件为一单层结构,当多芯片接置于单层导线架时,无法充分提供多个芯片间的电性连接。
请参阅图1,为此,中国台湾专利I229427公开一种多芯片的半导封装件,是将一布线基板12接置于导线架11的芯片座111上,以形成多层结构(Multi-layer),再将多个的半导体芯片13以并排方式黏结至该布线基板12上,并通过第一焊线组14a与第二焊线组14b分别将该半导体芯片13电性连接至该布线基板12上与该导线架11的导脚112上,其中该些半导体芯片13可通过预设于该布线基板12上的线路而相互电性导接。相关的技术还可参阅美国专利第5,502,289、5,661,337号。
但是前述的半导体封装件中,因布线基板与导线架芯片座间的接口,常易因材料不同所造成的应力导致许多信赖性问题,甚者,因封装件内含有易吸湿的基板材料,易导致封装件裂损等问题。再者,于有限的芯片座上布设基板无法整合太多的芯片于一封装件内,从而限制此种具多层结构的导线架(Multi-layer lead frame)应用。
请参阅图2,为解决前述问题,业界遂发展出一种具导脚(leads)的球栅阵列(BGA)基板,如美国专利5,563,446及5,789,811号所公开,是于基板22中整合多个导脚21,以供接置于该基板22上的半导体芯片23得以同时利用焊线24电性连接至该基板22及该导脚21上,并于该基板22上形成包覆该半导体芯片23及导脚21内端的封装胶体26,最后通过该基板22底面的焊球25及导脚21而电性连接至外界。
然而前述的半导体封装件中,因将导线架整合至基板内部,除制造困难外,又因该金属材料的导脚是设于树脂材料基板内,将因多种接口的应力问题而导致此种封装件仍存有信赖性不佳的问题。
因此,如何提供一种多芯片半导体装置及其制法,以在其中整合多个半导体芯片,且可避免形成多种材料接口应力、基板内埋所导致吸湿缺陷及包覆导脚所造成信赖性不佳等问题,实为目前相关业界所亟待解决的问题。
发明内容
鉴于以上现有技术的缺点,本发明的一目的在于提供一种可整合多个半导体芯片以构成多芯片模块(MCM)的具导脚的多芯片半导体装置及其制法。
本发明的复一目的是提供一种具导脚的多芯片半导体装置及其制法,以避免现有封装件中多种材料接口应力所产生信赖性不佳问题。
本发明的又一目的是提供一种具导脚的多芯片半导体装置及其制法,以避免现有封装件中包覆导脚所发生信赖性不良问题。
本发明的再一目的是提供一种具导脚的多芯片半导体装置及其制法,以避免现有封装件中包覆基板所发生基板吸湿导致封装件裂损问题。
本发明的另一目的是提供一种制程简便且成本低的具导脚的多芯片半导体装置及其制法。
为达到上述目的及其它相关的目的,本发明提供一种具导脚的多芯片半导体装置的制法,包括:提供一表面设有多个连接垫(connection pad)的基板,以于该基板表面接置并电性连接多个半导体芯片;于该基板上形成包覆该半导体芯片的封装胶体,并使该连接垫外露出该封装胶体,以形成封装单元;提供一具有多个导脚(leads)的导线架,以将该封装单元外露的连接垫与该导线架的导脚电性连接,以构成具导脚的多芯片半导体装置。
本发明还提供一种具导脚的多芯片半导体装置,包括:基板,该基板表面设有多个连接垫;多个半导体芯片,接置并电性连接至该基板;封装胶体,形成于该基板上以包覆该半导体芯片且外露出该连接垫;以及多个导脚,与该连接垫相互接合及电性连接。
另外本发明的具导脚的多芯片半导体装置及其制法中还可于该导脚上接置一环状加强件,藉以强化该导脚与封装单元的基板结合强度;亦或可将一设有凹穴的散热件接置于该封装单元的封装胶顶面及该导脚上,藉以同时强化多芯片半导体装置的散热性及导脚与基板的结合性;再者,亦可于该封装单元相对形成有封装胶体的另一表面上接置多个焊球,该焊球可额外提供信号传递及导热路径;此外,为考虑电性需求,于该封装单元相对形成有封装胶体的另一表面上形成不同电性的外露焊垫,以供多芯片半导体装置接置于如印刷电路板等外部装置时,得作为多重电压(Multi-voltage)或接地的设计。
因此,本发明的具导脚的多芯片半导体装置及其制法主要即是提供表面设有多个连接垫的基板,以将多个半导体芯片接置并电性连接至该基板,及于该基板上形成包覆该半导体芯片且外露出该连接垫的封装胶体,以形成封装单元,接着再令该封装单元外露的连接垫与导线架的导脚相互结合及电性连接,以通过简便且低成本的方式即形成具导脚的多芯片模块(MCM)的半导体装置,如此即可避免现有技术将基板或导脚整合于封装件中所产生多种接口应力造成信赖性不佳,或基板吸湿导致封装件裂损的问题。
附图说明
图1为中国台湾专利I229427所公开的多芯片半导封装件剖面示意图;
图2为美国专利5,563,446及5,789,811号所公开的半导体封装件示意图;
图3A至图3E为本发明的具导脚的多芯片半导体装置及其制法第一实施例的示意图;
图4A及图4B为本发明的具导脚的多芯片半导体装置及其制法第二实施例的示意图;
图5为本发明的具导脚的多芯片半导体装置及其制法第三实施例的示意图;
图6为本发明的具导脚的多芯片半导体装置及其制法第四实施例的示意图;以及
图7为本发明的具导脚的多芯片半导体装置及其制法第五实施例的示意图。
元件符号说明
11导线架 111芯片座
112导脚 12布线基板
13半导体芯片 14a,14b焊线
21导脚 22基板
23半导体芯片 24焊线
25焊球 26封装胶体
30封装单元 31基板
310基板模块片 311连接垫
32半导体芯片 33焊线
34封装胶体 35导线架
350导线架模块片 351导脚
36导电材料 41环状强化件
410环状开口 42不导电胶
51散热件 510匹穴
52不导电胶 53导热胶
61焊球 71焊垫
72外部装置 73导电材料
具体实施方式
以下通过特定的具体实施例说明本发明的实施方式,本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其它优点与功效。
第一实施例
请参阅图3A至图3E,为本发明的具导脚的多芯片半导体装置的制法示意图,且以下将以批次量产方式进行说明,当然亦可以单颗制程方式进行。
如图3A所示,提供一具有多个基板31的基板模块片310,各该基板31表面设有多个连接垫(connection pad)311,以于各该基板31表面接置多个半导体芯片32。该些半导体芯片32可通过如本图示的焊线33电性连接至该基板31,亦可以覆晶方式电性连接至该基板31;该连接垫311设于该基板31边缘。
如图3B及图3C所示,于各该基板31上形成包覆该半导体芯片32及焊线33的封装胶体34,并使各该基板31表面的连接垫311外露出该封装胶体34。
接着,再沿各该基板31间进行切割该基板模块片310,以形成多个封装单元30。
如图3D及图3E所示,提供一具有多个导线架35的导线架模块片350,其中各该导线架35具有多个导脚(leads)351,接着将先前完成芯片封装的封装单元30,以其外露出封装胶体34的连接垫311利用回焊或热压合等方式,间隔一导电材料36而与该导脚351电性连接,接着成型(forming)该些导脚351,并沿各该导线架35分离(singulating)该导线架模块片350,以构成具导脚的多芯片半导体装置。
该导脚351亦可预先弯折成型,以供该封装单元30连接至该导脚351后,直接分离该导线架35,以构成具导脚的多芯片半导体装置。
通过前述制法,本发明还提供一种具导脚的多芯片半导体装置,包括:基板31,该基板31表面设有多个连接垫311;多个半导体芯片32,接置并电性连接至该基板31;封装胶体34,形成于该基板31上以包覆该半导体芯片32且外露出该连接垫311;以及多个导脚351,与该连接垫311相互接合及电性连接。
因此,本发明的具导脚的多芯片半导体装置及其制法主要即是提供表面设有多个连接垫的基板,以将多个半导体芯片接置并电性连接至该基板,及于该基板上形成包覆该半导体芯片且外露出该连接垫的封装胶体,以形成封装单元,接着再令该封装单元外露的连接垫与导线架的导脚相互结合及电性连接,以通过简便且低成本的方式即形成具导脚的多芯片模块(MCM)的半导体装置,如此即可避免现有技术将基板或导脚整合于封装件中所产生多种接口应力造成信赖性不佳,或基板吸湿导致封装件裂损问题。
第二实施例
请参阅图4A及图4B,为本发明的具导脚的多芯片半导体装置及其制法第二实施例的示意图,其中为便于说明及了解,对应先前相同或相似的元件是以相同编号表示的。
本实施例的具导脚的多芯片半导体装置及其制法与前述实施例大致相同,主要相异是在完成芯片封装的封装单元以其外露出封装胶体的连接垫与导脚电性连接后,还可提供一环状强化件41(如图4A所示),以将该强化件41通过一不导电胶42而接置于该导脚351上,并使该封装单元的封装胶体34容设于该强化件41的环状开口410中,藉以强化该导脚351与封装单元的基板31接合强度。
第三实施例
请参阅图5,为本发明的具导脚的多芯片半导体装置及其制法第三实施例的示意图,其中为便于说明及了解,对应先前相同或相似的元件是以相同编号表示的。
本实施例的具导脚的多芯片半导体装置及其制法与前述实施例大致相同,主要相异是在完成芯片封装的封装单元以其外露出封装胶体的连接垫与导线架的导脚电性连接后,还可提供一设有凹穴510的散热件51,以将该散热件51通过一不导电胶52而接置于该导脚351上,并使该凹穴510顶面间隔一导热胶53而接置于该封装胶体34顶面,藉以同时强化半导体装置的散热性及导脚351与基板31的结合性。
第四实施例
请参阅图6,为本发明的具导脚的多芯片半导体装置及其制法第四实施例的示意图,其中为便于说明及了解,对应先前相同或相似的元件是以相同编号表示的。
本实施例的具导脚的多芯片半导体装置及其制法与前述实施例大致相同,主要相异是在基板31相对形成有封装胶体34的另一表面上接置多个焊球61,该焊球61可额外提供信号传递及导热路径,藉以强化半导体装置的电性功能及散热性。
第五实施例
请参阅图7,为本发明的具导脚的多芯片半导体装置及其制法第五实施例的示意图,其中为便于说明及了解,对应先前相同或相似的元件是以相同编号表示的。
本实施例的具导脚的多芯片半导体装置及其制法与前述实施例大致相同,主要相异是于基板31相对形成有封装胶体34的另一表面上形成不同电性的外露焊垫71,以供该半导体装置接置于如印刷电路板等外部装置72时,得以利用该些外露焊垫71间隔导电材料73而电性连接至该外部装置72,作为多重电压(Multi-voltage)或接地的设计。
上述的具体实施例,仅用以例释本发明的特点及功效,而非用以限定本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下,对于上述的实施例进行修饰与改变。因此,本发明的权利保护范围,应以本发明权利要求书的范围为依据。
Claims (17)
1.一种具导脚的多芯片半导体装置的制法,包括:
提供一表面设有多个连接垫的基板,以于该基板表面接置并电性连接多个半导体芯片;
于该基板上形成包覆该半导体芯片的封装胶体,并使该连接垫外露出该封装胶体,以形成封装单元;以及
提供一具有多个导脚的导线架,以将该封装单元外露的连接垫与该导线架的导脚电性连接,以构成具导脚的多芯片半导体装置。
2.根据权利要求1所述的具导脚的多芯片半导体装置的制法,其中,该具导脚的多芯片半导体装置选择以批次量产及单颗制程的其中一方式进行。
3.根据权利要求1所述的具导脚的多芯片半导体装置的制法,其中,该些半导体芯片是选择以焊线及覆晶的其中一方式而电性连接至该基板。
4.根据权利要求1所述的具导脚的多芯片半导体装置的制法,其中,该连接垫是设于该基板边缘。
5.根据权利要求1所述的具导脚的多芯片半导体装置的制法,其中,该封装单元是以其外露出封装胶体的连接垫利用回焊及热压合的其中一方式,间隔导电材料而与该导脚电性连接。
6.根据权利要求1所述的具导脚的多芯片半导体装置的制法,还包括提供一环状强化件,以将该强化件通过一不导电胶而接置于该导脚上,并使该封装单元的封装胶体容设于该强化件的环状开口中。
7.根据权利要求1所述的具导脚的多芯片半导体装置的制法,还包括提供一设有凹穴的散热件,以将该散热件通过一不导电胶而接置于该导脚上,并使该凹穴顶面间隔一导热胶而接置于该封装胶体顶面。
8.根据权利要求1所述的具导脚的多芯片半导体装置的制法,其中,该基板在相对形成封装胶体的另一表面上接置有多个焊球,以额外提供信号传递及导热路径。
9.根据权利要求1所述的具导脚的多芯片半导体装置的制法,其中,该基板在相对形成封装胶体的另一表面上设有不同电性的外露焊垫,以利用该些外露焊垫间隔导电材料而电性连接至外部装置,作为多重电压(Multi-voltage)或接地的设计。
10.一种具导脚的多芯片半导体装置,包括:
基板,该基板表面设有多个连接垫;
多个半导体芯片,接置并电性连接至该基板;
封装胶体,形成于该基板上以包覆该半导体芯片且外露出该连接垫;以及
多个导脚,与该连接垫相互接合及电性连接。
11.根据权利要求10所述的具导脚的多芯片半导体装置,其中,该些半导体芯片选择以焊线及覆晶的其中一方式而电性连接至该基板。
12.根据权利要求10所述的具导脚的多芯片半导体装置,其中,该连接垫设于该基板边缘。
13.根据权利要求10所述的具导脚的多芯片半导体装置,其中,该封装单元是以其外露出封装胶体的连接垫利用回焊及热压合的其中一方式,间隔导电材料而与该导脚电性连接。
14.根据权利要求10所述的具导脚的多芯片半导体装置,还包括有一环状强化件,通过一不导电胶而接置于该导脚上,并使该封装单元的封装胶体容设于该强化件的环状开口中。
15.根据权利要求10所述的具导脚的多芯片半导体装置,还包括有一设有凹穴的散热件,通过一不导电胶而接置于该导脚上,并使该凹穴顶面间隔一导热胶而接置于该封装胶体顶面。
16.根据权利要求10所述的具导脚的多芯片半导体装置,其中,该基板在相对形成封装胶体的另一表面上接置有多个焊球,以额外提供信号传递及导热路径。
17.根据权利要求10所述的具导脚的多芯片半导体装置,其中,该基板在相对形成封装胶体的另一表面上设有不同电性的外露焊垫,以利用该些外露焊垫间隔导电材料而电性连接至外部装置,作为多重电压或接地的设计。
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CN102403281A (zh) * | 2011-10-11 | 2012-04-04 | 常熟市广大电器有限公司 | 一种高性能芯片封装结构 |
CN105374789A (zh) * | 2015-11-13 | 2016-03-02 | 华为技术有限公司 | 一种电路模块结构及其制造方法 |
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CN102403281A (zh) * | 2011-10-11 | 2012-04-04 | 常熟市广大电器有限公司 | 一种高性能芯片封装结构 |
CN105374789A (zh) * | 2015-11-13 | 2016-03-02 | 华为技术有限公司 | 一种电路模块结构及其制造方法 |
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