Summary of the invention
(1) technical matters that will solve
In view of this, fundamental purpose of the present invention is to provide a kind of method for preparing microelectron mechanical system optical multiplexer chip, to reduce preparation cost, makes microelectron mechanical system optical multiplexer chip be able to extensive promotion and application.
(2) technical scheme
For achieving the above object, technical scheme of the present invention is achieved in that
A kind of method for preparing microelectron mechanical system optical multiplexer chip, this method comprises:
Step 101: at the front and back grown silicon nitride film of first silicon substrate;
Step 102: photoetching first published top electrode figure on described silicon nitride film;
Step 103: on the top electrode figure of described silicon nitride film and formation, evaporate chromium/gold thin film, obtain the top electrode figure after ultrasonic the peeling off;
Step 104: photoetching second edition top electrode figure on described top electrode figure;
Step 105: under thick photoresist is sheltered, silicon nitride film is carved thoroughly, obtained the upper reflector figure;
Step 106: the corrosion window graphics that makes the back side in the back side of the described first silicon substrate third edition by lithography;
Step 107: on described corrosion window graphics, be coated with the optics photoresist, under the sheltering of optics etching glue, the silicon nitride film at the back side carved thoroughly, obtain corrosion window graphics;
Step 108: place potassium hydroxide KOH solution to corrode described first silicon substrate, remove the silicon substrate of the redundance under the upper reflector, obtain the upper reflector structure;
Step 109: the 4th edition bottom electrode figure of photoetching on second silicon substrate;
Step 110: on described the 4th edition bottom electrode figure, evaporate chromium/gold thin film, obtain the bottom electrode figure after ultrasonic the peeling off;
Step 111: with described first and second silicon substrate carry out alignment keys and, scribing and welding lead then.
Described step 101 comprises: selecting thickness for use is that the common double of 480 to 520 μ m is thrown silicon chip as first silicon substrate, and the method that adopts low-pressure chemical vapor deposition is 1.2 to 1.5 microns silicon nitride film at the front and back growth thickness of described first silicon substrate.
Described step 102 comprises: be coated with the S9912 optics etching glue on described silicon nitride film, glue thick 1000 carries out exposure imaging to 1500nm to optics etching glue, forms the top electrode figure.
Further comprise between step 102 and the step 103: the silicon chip after will developing adopts oxygen to remove primer in reactive ion etching, and oxygen flow is 55 to 65 milliliters of per seconds, and plasma bias power is 10 to 15 watts, goes behind the primer silicon chip to be sent into evaporator.
Evaporate chromium/gold thin film described in the step 103 and adopt electron beam evaporation process to carry out, evaporation thickness is 10 to 12nm chromium thin film earlier, evaporates thickness again and be 55 to 65nm gold thin film;
Peel off described in the step 103 and obtain the top electrode figure and comprise: the silicon chip that evaporated chromium/gold thin film is placed the acetone vessel, and ultrasound wave removes photoresist on the silicon chip and the chromium/gold thin film on the glue, obtain the top electrode figure of chromium/gold.
Described step 104 comprises: be coated with the BP218 optics etching glue on described top electrode figure, thick 3 to 4 microns of glue obtains the top electrode figure through behind the exposure imaging.
Described step 105 comprises: it is saturating to adopt dry process reaction ion etching technology that the silicon nitride film in front is carved under the sheltering of BP218 optics etching glue, obtains the upper reflector figure.
Described step 106 comprises: be coated with the BP218 optics etching glue at the back side of described first silicon substrate, thick 3 to 4 microns of glue obtains back surface corrosion window graphics through behind the exposure imaging.
Described step 107 comprises: it is saturating to adopt dry process reaction ion etching technology that back side silicon nitride film is carved under the sheltering of BP218 optics etching glue, obtains corrosion window graphics.
Described step 108 comprises: described first silicon substrate put into the KOH corrosive liquid corrode, remove the silicon substrate of the redundance under the upper reflector, obtain the upper reflector structure.
Described step 109 comprises: be coated with the S9912 optics etching glue on second silicon substrate, glue thick 1000 obtains the bottom electrode figure to 1500nm through behind the exposure imaging.
Described step 110 comprises: on described the 4th edition bottom electrode figure, adopt electron beam evaporation process earlier evaporation thickness be 10 to 12nm chromium thin film, evaporate thickness again and be 55 to 65nm gold thin film, obtain chromium/gold thin film;
Second silicon substrate that evaporated chromium/gold thin film placed the acetone vessel, and the chromium/gold thin film on ultrasound wave removal photoresist and the glue, the top electrode figure obtained.
Described step 111 comprises: in temperature is that 220 to 250 ℃, voltage are under 400 to 600V the condition described first and second silicon substrate to be carried out anode linkage, and two silicon chips are bonded together fully; According to the distribution of component graphics on the silicon chip, be diced into line array device then; And welding electrode lead-in wire on the golden film of last lower silicon slice respectively.
The film of etch silicon nitride described in step 105 and the step 107 adopts dry process reaction ion etching technology to carry out, and process conditions are: gas adopts SF
6, 55 to 65 milliliters of per seconds of flow, plasma bias power is 60 to 80 watts, adds magnetic field, water-cooled.
(3) beneficial effect
From technique scheme as can be seen, the present invention has following beneficial effect:
1, this method for preparing microelectron mechanical system optical multiplexer chip provided by the invention, because the processing and fabricating of chip can carry out in batches, processing cost is low, so greatly reduce preparation cost, makes microelectron mechanical system optical multiplexer chip be able to extensive promotion and application.
2, this method for preparing microelectron mechanical system optical multiplexer chip provided by the invention owing to adopted unique biplate bonding technology, so whole difficulty of processing has reduced, has improved the yield rate of device effectively.
3, this method for preparing microelectron mechanical system optical multiplexer chip provided by the invention is because optical multiplexer is a necessary important devices in the optical fiber telecommunications system, so have actual application value very widely.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail.
As shown in Figure 1, Fig. 1 is the method flow diagram of preparation microelectron mechanical system optical multiplexer chip provided by the invention, and this method may further comprise the steps:
Step 101: at the front and back grown silicon nitride film of first silicon substrate;
Step 102: photoetching first published top electrode figure on described silicon nitride film;
Step 103: on the top electrode figure of described silicon nitride film and formation, evaporate chromium/gold thin film, obtain the top electrode figure after ultrasonic the peeling off;
Step 104: photoetching second edition top electrode figure on described top electrode figure;
Step 105: under thick photoresist is sheltered, silicon nitride film is carved thoroughly, obtained the upper reflector figure;
Step 106: the corrosion window graphics that makes the back side in the back side of the described first silicon substrate third edition by lithography;
Step 107: on described corrosion window graphics, be coated with the optics photoresist, under the sheltering of optics etching glue, the silicon nitride film at the back side carved thoroughly, obtain corrosion window graphics;
Step 108: place potassium hydroxide KOH solution to corrode described first silicon substrate, remove the silicon substrate of the redundance under the upper reflector, obtain the upper reflector structure;
Step 109: the 4th edition bottom electrode figure of photoetching on second silicon substrate;
Step 110: on described the 4th edition bottom electrode figure, evaporate chromium/gold thin film, obtain the bottom electrode figure after ultrasonic the peeling off;
Step 111: with described first and second silicon substrate carry out alignment keys and, scribing and welding lead then.
Above-mentioned steps 101 comprises: selecting thickness for use is that the common double of 480 to 520 μ m is thrown silicon chip as first silicon substrate, and the method that adopts low-pressure chemical vapor deposition is 1.2 to 1.5 microns silicon nitride film at the front and back growth thickness of described first silicon substrate.
Above-mentioned steps 102 comprises: be coated with the S9912 optics etching glue on described silicon nitride film, glue thick 1000 carries out exposure imaging to 1500nm to optics etching glue, forms the top electrode figure.
Further comprise between above-mentioned steps 102 and the step 103: the silicon chip after will developing adopts oxygen to remove primer in reactive ion etching, oxygen flow is 55 to 65 milliliters of per seconds, plasma bias power is 10 to 15 watts, goes behind the primer silicon chip to be sent into evaporator.
Evaporate chromium/gold thin film described in the above-mentioned steps 103 and adopt electron beam evaporation process to carry out, evaporation thickness is 10 to 12nm chromium thin film earlier, evaporates thickness again and be 55 to 65nm gold thin film.
Peel off described in the above-mentioned steps 103 and obtain the top electrode figure and comprise: the silicon chip that evaporated chromium/gold thin film is placed the acetone vessel, and ultrasound wave removes photoresist on the silicon chip and the chromium/gold thin film on the glue, obtain the top electrode figure of chromium/gold.
Above-mentioned steps 104 comprises: be coated with the BP218 optics etching glue on described top electrode figure, thick 3 to 4 microns of glue obtains the top electrode figure through behind the exposure imaging.
Above-mentioned steps 105 comprises: it is saturating to adopt dry process reaction ion etching technology that the silicon nitride film in front is carved under the sheltering of BP218 optics etching glue, obtains the upper reflector figure.
Above-mentioned steps 106 comprises: be coated with the BP218 optics etching glue at the back side of described first silicon substrate, thick 3 to 4 microns of glue obtains back surface corrosion window graphics through behind the exposure imaging.
Above-mentioned steps 107 comprises: it is saturating to adopt dry process reaction ion etching technology that back side silicon nitride film is carved under the sheltering of BP218 optics etching glue, obtains corrosion window graphics.
Above-mentioned steps 108 comprises: described first silicon substrate put into the KOH corrosive liquid corrode, remove the silicon substrate of the redundance under the upper reflector, obtain the upper reflector structure.
Above-mentioned steps 109 comprises: be coated with the S9912 optics etching glue on second silicon substrate, glue thick 1000 obtains the bottom electrode figure to 1500nm through behind the exposure imaging.
Above-mentioned steps 110 comprises: on described the 4th edition bottom electrode figure, adopt electron beam evaporation process earlier evaporation thickness be 10 to 12nm chromium thin film, evaporate thickness again and be 55 to 65nm gold thin film, obtain chromium/gold thin film; Second silicon substrate that evaporated chromium/gold thin film placed the acetone vessel, and the chromium/gold thin film on ultrasound wave removal photoresist and the glue, the top electrode figure obtained.
Above-mentioned steps 111 comprises: in temperature is that 220 to 250 ℃, voltage are under 400 to 600V the condition described first and second silicon substrate to be carried out anode linkage, and two silicon chips are bonded together fully; According to the distribution of component graphics on the silicon chip, be diced into line array device then; And welding electrode lead-in wire on the golden film of last lower silicon slice respectively.
Etch silicon nitride film described in above-mentioned steps 105 and the step 107 adopts dry process reaction ion etching technology to carry out, and process conditions are: gas adopts SF
6, 55 to 65 milliliters of per seconds of flow, plasma bias power is 60 to 80 watts, adds magnetic field, water-cooled.
Based on the method flow diagram of the described preparation microelectron mechanical system optical multiplexer chip of Fig. 1, the method that the present invention prepares microelectron mechanical system optical multiplexer chip is further described below in conjunction with specific embodiment.
Embodiment
Now be described with reference to the accompanying drawings technical scheme of the present invention, according to the preparation method of above-described microelectron mechanical system optical multiplexer chip, its operation steps is:
The first step is in silicon chip 101 surperficial two-sided grown silicon nitride films 102 and 103.
As shown in Figure 2, Fig. 2 is according to the process chart of the embodiment of the invention at the front and back grown silicon nitride film of first silicon substrate; Select for use common double to throw silicon chip and do substrate 101, the thickness of substrate is 500 microns, and the method that adopts low-pressure chemical vapor deposition is in the two-sided grown silicon nitride film 102 of silicon substrate and 103, and thickness is 1.2 to 1.5 microns.
The second step photoetching first published top electrode figure 104;
As shown in Figure 3, Fig. 3 is the process chart according to embodiment of the invention photoetching first published top electrode figure on silicon nitride film; Be coated with the S9912 optics etching glue on silicon nitride 102, the thick 1000-1500nm of glue obtains top electrode figure 104 through behind the exposure imaging.
The 3rd step evaporation chromium/gold thin film 105;
As shown in Figure 4, Fig. 4 is the process chart according to embodiment of the invention evaporation chromium/gold thin film; Adopting electron beam evaporation process evaporation chromium thickness 10nm earlier on the silicon nitride 102 and on the photoresist 104, evaporated gold thickness 60nm obtains chromium/gold thin film 105 then.
Ultrasonic peeling off of the 4th step;
As shown in Figure 5, the process chart of Fig. 5 for the chromium/gold thin film of evaporation being peeled off according to the embodiment of the invention; The substrate that evaporated metal film is placed the acetone vessel, and the chromium/gold thin film 105 on ultrasound wave removal photoresist 104 and the glue, top electrode figure 106 obtained.
The 5th step photoetching second edition top electrode figure 107;
As shown in Figure 6, Fig. 6 is the process chart according to embodiment of the invention photoetching second edition top electrode figure; Be coated with the BP218 optics etching glue on top electrode 106, the thick 3-4 micron of glue obtains top electrode figure 107 through behind the exposure imaging.
The 6th step photoresist masking dry method shelter etching;
As shown in Figure 7, Fig. 7 is the process chart according to embodiment of the invention dry method shelter etching front silicon nitride film; It is saturating to adopt dry process reaction ion etching (RIE) technology that silicon nitride is carved under thick photoresist is sheltered, and obtains upper reflector figure 108.
The 7th step silicon chip back side third edition photoetching corrosion graph window 109
As shown in Figure 8, Fig. 8 is according to the process chart of the embodiment of the invention at silicon chip back side third edition photoetching corrosion graph window; In silicon chip back BP218 optics etching glue, the thick 3-4 micron of glue obtains back surface corrosion window graphics 109 through behind the exposure imaging.
The 8th step photoresist masking dry method shelter etching;
As shown in Figure 9, Fig. 9 is the process chart according to embodiment of the invention dry method shelter etching back side silicon nitride film; It is saturating to adopt dry process reaction ion etching (RIE) technology that back side silicon nitride is carved under thick photoresist is sheltered, and obtains corrosion window graphics 110.
The 9th step wet etching;
As shown in figure 10, Figure 10 is the process chart according to first silicon substrate of embodiment of the invention wet etching; Whole silicon wafer is put into the KOH corrosive liquid corrode, remove the silicon substrate of the redundance under the upper reflector, and obtain upper reflector structure 111.
The tenth step is at the 4th edition bottom electrode figure 112 of second silicon chip photoetching;
As shown in figure 11, Figure 11 is according to the process chart of the embodiment of the invention at the 4th edition bottom electrode figure of second silicon chip photoetching; Be coated with the S9912 optics etching glue on second silicon chip, the thick 1000-1500nm of glue obtains bottom electrode figure 112 through behind the exposure imaging.
The tenth step evaporation chromium/gold thin film 113;
As shown in figure 12, Figure 12 is for to evaporate the process chart of chromium/gold thin film according to the embodiment of the invention on the bottom electrode figure; Adopt electron beam evaporation process evaporation chromium thickness 10nm earlier on bottom electrode figure 112, evaporated gold thickness 50nm obtains chromium/gold thin film 113 then.
Ultrasonic peeling off of the 12 step;
As shown in figure 13, Figure 13 is for to carry out the ultrasonic process chart of peeling off according to the embodiment of the invention; The substrate that evaporated metal film is placed the acetone vessel, and the chromium/gold thin film 113 on ultrasound wave removal photoresist 112 and the glue, top electrode figure 114 obtained.
The 13 step bonding;
As shown in figure 14, Figure 14 for according to the embodiment of the invention with first and second silicon substrate carry out alignment keys and process chart; Under the condition of 220~250 ℃ of temperature, voltage 400~600V, carry out anode linkage, two silicon chips are bonded together fully.
The 14 step scribing; Distribution according to component graphics on the silicon chip is diced into line array device;
The 15 step welding lead; Welding electrode goes between on the golden film of last lower silicon slice respectively, and so far, the microelectron mechanical system optical multiplexer chip preparation finishes.
Above-described specific embodiment; purpose of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the above only is specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any modification of being made, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.