CN112563124A - Preparation method of large-area ultrathin hollowed-out hard mask - Google Patents
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- CN112563124A CN112563124A CN202011452269.5A CN202011452269A CN112563124A CN 112563124 A CN112563124 A CN 112563124A CN 202011452269 A CN202011452269 A CN 202011452269A CN 112563124 A CN112563124 A CN 112563124A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 49
- 238000000034 method Methods 0.000 claims abstract description 44
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 36
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 36
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 36
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 22
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 22
- 239000010703 silicon Substances 0.000 claims abstract description 22
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- 238000005530 etching Methods 0.000 claims description 27
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 claims description 10
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 claims description 10
- 239000008367 deionised water Substances 0.000 claims description 7
- 229910021641 deionized water Inorganic materials 0.000 claims description 7
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 7
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
Abstract
The invention discloses a preparation method of a large-area ultrathin hollow hard mask, which mainly solves the problems of large thickness and small area of the hollow hard mask prepared by the prior art. The implementation scheme is as follows: 1) selecting a double-polished silicon substrate, and cleaning; 2) growing a layer of compact silicon nitride film on the front and back surfaces of the double-polished silicon substrate; 3) respectively photoetching the front surface and the back surface of the substrate on which the compact silicon nitride film is grown, forming a photoresist pattern complementary with the electrode pattern on the photoresist on the front surface, and forming a corresponding window pattern on the back surface; 4) transferring the electrode pattern and the window pattern manufactured in the step 3) to a silicon nitride film on the front side and the back side of the substrate with the patterned surface by using a dry etching process; 5) and (4) carrying out wet etching on the substrate processed in the step (4), cleaning and drying, and removing glue and residues to obtain the hollow hard mask. The invention has the advantages of large area, no deformation and reusability, and has low production cost and high efficiency, and can be used for preparing semiconductor devices.
Description
Technical Field
The invention belongs to the technical field of microelectronics, and particularly relates to a preparation method of an ultrathin hollow hard mask, which can be used for preparing a semiconductor device.
Background
The preparation of electrode patterns related to the traditional micro-nano semiconductor device generally adopts an ultraviolet lithography or electron beam etching method, which comprises complex steps of photoresist throwing, exposure, development, electrode evaporation, photoresist removal and the like, and meanwhile, the ultraviolet lithography has extremely high requirements on light beams, and the electron beam lithography has the defects of low production efficiency and proximity effect. And for organic semiconductor devices, the introduction of organic photoresists can affect or dissolve semiconductor materials, thereby affecting device performance. Therefore, the concept of the electrode hollow hard mask technology is developed, the electrode hollow hard mask technology has important application in the preparation and integration of large-area low-cost micro-nano semiconductor devices, the hollow hard mask can directly cover and align the surface of a device substrate, electrode patterns can be prepared on semiconductor materials by adopting a conventional metal film evaporation method, the electrode hollow hard mask technology has the advantages of no pollution, simple process, short period and the like, and has very important application prospects in the fields of integrated semiconductor devices, particularly flexible electronic devices and the like.
Chinese patent publication No. CN105185707A proposes a method for preparing a hard mask film with high hardness and low stress grown on a semiconductor substrate, and can be used for patterning a variety of dielectric materials. Chinese patent No. CN1901141A discloses a method for preparing a silicon nitride hollow mask-based nano-electrode, which adopts the techniques of silicon nitride film growth and focused ion beam etching patterning to form a hollow mask. At present, the methods cannot form an ultrathin patterned hollow mask with a large area and can be repeatedly used. Moreover, the thickness of the traditional hollow mask is usually more than hundreds of microns, which is not beneficial to forming high fidelity integrated device electrodes, thereby affecting the performance of the device.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provides a method for preparing a large-area ultrathin hollowed-out hard mask to prepare a large-area reusable ultrathin patterned hollowed-out mask.
In order to achieve the purpose, the technical scheme of the invention comprises the following steps:
(1) selecting a double-polished silicon substrate, and cleaning;
(2) growing a layer of compact silicon nitride film on the front and back surfaces of the cleaned double-polished silicon substrate by adopting a film growth process;
(3) photoetching the front side and the back side of the substrate with the dense silicon nitride film, so as to form a photoresist pattern complementary to the electrode pattern on the photoresist on the front side and form a window pattern corresponding to the front side pattern on the photoresist on the back side;
(4) transferring the electrode pattern and the window pattern manufactured in the step (3) from the photoresist to a silicon nitride film on the front side and the back side of the substrate with the patterned surface by using a dry etching process;
(5) and (4) carrying out wet etching on the substrate processed in the step (4), cleaning and drying, and removing glue and residues to obtain the hollow hard mask.
Further, the double-polished silicon substrate in the step (1) is cleaned by adopting double-polished intrinsic silicon with the thickness of 200 +/-20 microns, and is sequentially cleaned by acetone, alcohol and deionized water for 5 min.
Further, the thickness of the compact silicon nitride film deposited in (2) is 0.8-1.2 μm, and the film growth process comprises chemical vapor deposition or atomic layer deposition.
Further, in (3), the front side and the back side of the substrate on which the dense silicon nitride film is grown are respectively subjected to photoetching, namely, photoresist with the thickness of 1-3 mu m is firstly spin-coated on the silicon nitride film, then prebaking, exposure, development and postbaking are sequentially carried out, finally, a photoresist pattern complementary with the electrode pattern is formed on the photoresist on the front side, and a window pattern corresponding to the front side pattern is formed on the photoresist on the back side. Wherein the electrode patterns comprise interdigital electrode patterns and parallel electrode patterns.
Further, (4) the etching depth of the middle dry method is the same as the thickness of the silicon nitride film.
Further, in the step (5), the substrate processed in the step (4) is subjected to wet etching, and the wet etching is carried out according to the following steps:
(5a) soaking the substrate for 1-2s by using a buffer oxide etching solution BOE to remove a natural oxide layer on the surface of the silicon;
(5b) etching the substrate by adopting 25 wt% of TMAH weak base solution, namely, keeping the solution temperature at 80-100 ℃ by adopting an oil bath system, etching for 5-8 hours at the etching rate of 1 mu m/min, and finishing etching after the substrate stops bubbling.
Compared with the prior art, the invention has the following advantages:
firstly, the preparation process adopts the processes of ultraviolet lithography, dry etching, wet etching and the like, the process is simple and reliable, the preparation and the commercial batch production of large-area hollow masks can be realized, and different practical application requirements can be met by changing electrode patterns;
secondly, the grid silicon frame between the electrode arrays formed by anisotropic wet etching can effectively support the ultrathin silicon nitride film, so that the method has the characteristic of reutilization;
thirdly, the ultrathin hard mask prepared by the invention can obtain the following application effects:
the invention can be combined with the conventional coating processes such as thermal evaporation, electron beam evaporation and the like to cover and align the surface of a device to obtain a large-area, high-fidelity and pollution-free electrode array;
secondly, the invention can realize the top contact electrode, which is beneficial to reducing the contact resistance of the metal-semiconductor;
the invention can be used for preparing organic semiconductor integrated device electrodes, in particular to flexible organic semiconductor material electronic devices, and can effectively overcome the influence of organic photoresist and solvent on organic semiconductor materials in the device electrode photoetching process.
Drawings
FIG. 1 is a schematic diagram of a process flow for carrying out an embodiment of the present invention;
FIG. 2 is an optical microscope image of an ultra-thin hollow hard mask prepared based on an interdigital electrode array pattern according to an embodiment of the present invention;
FIG. 3 is a scanning electron microscope image of an ultra-thin hollow hard mask prepared based on an interdigital electrode array pattern according to an embodiment of the present invention;
FIG. 4 is an optical microscope image and a scanning electron microscope image of an ultra-thin hollow hard mask prepared based on a parallel electrode array pattern according to a second embodiment of the present invention;
fig. 5 is a scanning electron microscope image of an organic semiconductor submicroscale device, in which an ultra-thin hollow hard mask is prepared based on a parallel electrode array pattern according to a second embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention are described in detail below with reference to the accompanying drawings.
Referring to fig. 1, the present invention is given by the following two examples:
example 1, an ultra-thin hollowed-out hard mask was prepared based on the interdigital electrode array pattern using a chemical vapor deposition process.
Step 1: the substrate is picked up and washed and dried, as shown in fig. 1 (a).
According to the characteristic that intrinsic silicon is beneficial to anisotropic wet etching, excessive transverse etching is avoided, and the silicon surface has the characteristic of being beneficial to preparation of a compact and flat film after double polishing, an undoped double-polishing intrinsic silicon substrate is preferred in the embodiment, namely, the double-polishing intrinsic silicon substrate 1 with the thickness of 200 +/-20 mu m is selected, is sequentially subjected to ultrasonic cleaning for 5min by acetone, alcohol and deionized water, is dried by a nitrogen gun, and is baked on a hot plate at 180 ℃ for 5min to obtain a clean double-polishing silicon wafer substrate.
Step 2: and depositing a silicon nitride film, as shown in FIG. 1 (b).
Introducing nitrogen gas by using low-pressure chemical vapor deposition equipment under the process conditions of the pressure of 10-100Pa and the temperature of 700-2Cl2、SiCl4Or SiH4These silicon source gases and ammonia gas are subjected to a gas phase reaction to grow a 1 μm dense silicon nitride film 2 on the front and back surfaces of the clean substrate 1.
And step 3: a photoresist pattern and a window pattern are formed as shown in fig. 1 (c).
Uniformly spin-coating photoresist 3 on two sides of a substrate on which a silicon nitride film 2 is grown by a spin coater, regulating the thickness of the photoresist to be 1 mu m by the spin coating speed, baking the substrate before an annealing process, and preparing an interdigital electrode pattern by utilizing a photomask of the interdigital electrode through photoresist throwing, exposing and developing processes, wherein the array period parameter of the front electrode pattern is consistent with and aligned with the period of a back window.
In the present example, but not limited to, the photoresist is used in S1813, the prebaking temperature is 115 ℃, the prebaking time is 1min, the exposure time is 2-10S, the developing time is 30S, the deionized water is used for rinsing for 30S, the postbaking temperature is 125 ℃, and the postbaking time is 2 min.
And 4, step 4: the pattern is transferred to the silicon nitride film as shown in fig. 1 (d).
And (3) selecting a reactive ion beam dry etching process, carrying out chemical reaction by utilizing Ar ions and bombarding the silicon nitride film which is not masked by the photoresist, and controlling the etching rate and time to ensure that the etching depth is the same as the thickness of the deposited silicon nitride so as to transfer the pattern on the photoresist manufactured in the step (3) to the silicon nitride film.
And 5: and (4) carrying out wet etching on the substrate processed in the step (4), as shown in figure 1 (e).
A hollow hard mask is formed by a wet etching process, a weak base tetramethyl ammonium hydroxide solution is preferably selected, the slow release effect of weak base hydroxide ions is utilized to keep the etching rate, and the problem that the etching rate is rapidly reduced due to the fact that strong base reduces along with the reduction of ion concentration in the silicon etching process is solved.
The method comprises the following implementation steps:
5.1) quickly immersing the substrate into a buffer oxide etching solution BOE1-2s to remove silicon nitride possibly remained in the ion beam etching and a silicon surface compact oxide layer;
5.2) immersing the substrate treated by the step 5.1) into a 25 wt% weak base tetramethyl ammonium hydroxide (TMAH) solution, and keeping the temperature environment at 80-100 ℃ through a glycerol oil bath, a spiral condensation reflux and temperature control device, wherein the etching rate is 1 mu m/min, the etching time is 5-8 hours, and the etching is finished until bubbles on the surface of the substrate disappear;
and 5.3) removing the photoresist of the substrate after the etching is finished by utilizing acetone, then sequentially ultrasonically cleaning the substrate by utilizing alcohol and deionized water, and finally drying to obtain the hollow hard mask 4.
The optical microscope image of the obtained stencil hard mask of this example is shown in fig. 2, and the scanning electron microscope image is shown in fig. 3. Wherein, fig. 3(a) is a scanning electron microscope image at a magnification of 150; FIG. 3(b) is a scanning electron microscope image at a magnification of 500; FIG. 3(c) is a scanning electron microscope image at a magnification of 15 k; FIG. 3(d) is a scanning electron microscope image at a magnification of 50 k.
As can be seen from fig. 2 and fig. 3(a), the interdigital electrode pattern and the square electrodes are periodically arranged to form an array, and as can be seen from fig. 3(b), the black strip in the middle and the square on the diagonal of the element in each element in the array are all hollow parts, and fig. 3(d) shows that the width of the black strip, i.e., the interdigital electrode, is 5 μm, and the distance between every two interdigital electrodes is 3 μm. FIG. 3(d) demonstrates that the non-hollowed-out portion, i.e., the suspended silicon nitride pattern, has the characteristics of no deformation, smoothness and high precision. In the example, each interdigital electrode unit is connected with two electrode squares, and can be connected with an external circuit through a wire-bonding wire pressing process.
Step 1: the substrate is picked up and washed and dried, as shown in fig. 1 (a).
This step is embodied in the same manner as step 1 of example 1.
Step 2: and depositing a silicon nitride film, as shown in FIG. 1 (b).
Introducing SiCl precursor into the reaction kettle by adopting plasma enhanced atomic layer deposition equipment at the temperature of 50-550 DEG C4Or SiH4Reacting with ammonia gas to grow 1.2 μm dense silicon nitride films on the front and back of the clean substrate 12。
And step 3: a photoresist pattern and a window pattern are formed as shown in fig. 1 (c).
Uniformly spin-coating photoresist 3 on two sides of a substrate on which a silicon nitride film 2 is grown by a spin coater, regulating the thickness of the photoresist to be 1 mu m by the spin coating speed, baking the substrate before an annealing process, and preparing parallel electrode patterns by using a photomask of parallel electrodes by photoetching processes of spin coating, exposure and development, wherein the array period parameter of the front electrode patterns is consistent with and aligned with the period of a back window.
In the present example, but not limited to, the photoresist is used in S1813, the prebaking temperature is 115 ℃, the prebaking time is 1min, the exposure time is 2-10S, the developing time is 30S, the deionized water is used for rinsing for 30S, the postbaking temperature is 125 ℃, and the postbaking time is 2 min.
And 4, step 4: the pattern is transferred to the silicon nitride film as shown in fig. 1 (d).
And (3) selecting a reactive ion beam dry etching process, bombarding the silicon nitride film which is not masked by the photoresist by using Ar ions, and controlling the etching rate and time to ensure that the etching depth is the same as the thickness of the deposited silicon nitride so as to transfer the parallel electrode pattern and the window pattern manufactured in the step (3) to the silicon nitride film.
And 5: and (4) carrying out wet etching on the substrate processed in the step (4), as shown in figure 1 (e).
This step is embodied in the same manner as step 5 of example 1.
The optical microscope image of the obtained stencil hard mask of this example is shown in fig. 4(a), the scanning electron microscope image is shown in fig. 4(b), and as can be seen from fig. 4(a), the parallel electrode patterns are periodically arranged to form an array, the black stripe in the middle and the square on the diagonal of the cell in each cell in the array are both the stencil portions, and fig. 4(b) shows that the width of the black stripe, i.e., the parallel electrode, is 3 μm.
The hollow electrode hard mask obtained in the example is covered on the organic semiconductor submicron line array, the organic semiconductor device electrode is prepared by thermal evaporation, a local scanning electron microscope image of the organic semiconductor device electrode is shown in fig. 5, and as can be seen from fig. 5, the parallel electrode on the device has the characteristic of fidelity and no deformation.
The above are only two specific embodiments of the present invention, but do not constitute any limitation to the present invention. The present invention may not meet the requirements of specific dimensions and electrode pattern parameters, but may also include various changes and modifications of dimensions and electrode patterns without departing from the scope of the present invention, but such modifications and changes based on the inventive idea are still within the scope of the present invention as defined in the appended claims.
Claims (10)
1. A preparation method of a large-area ultrathin hollow hard mask is characterized by comprising the following steps:
(1) selecting a double-polished silicon substrate, and cleaning;
(2) growing a layer of compact silicon nitride film on the front and back surfaces of the cleaned double-polished silicon substrate by adopting a film growth process;
(3) photoetching the front side and the back side of the substrate with the dense silicon nitride film, so as to form a photoresist pattern complementary to the electrode pattern on the photoresist on the front side and form a window pattern corresponding to the front side pattern on the photoresist on the back side;
(4) transferring the electrode pattern and the window pattern manufactured in the step (3) from the photoresist to a silicon nitride film on the front side and the back side of the substrate with the patterned surface by using a dry etching process;
(5) and (4) carrying out wet etching on the substrate processed in the step (4), cleaning and drying, and removing glue and residues to obtain the hollow hard mask.
2. The method of claim 1, wherein the double-polished silicon substrate in (1) is made of double-polished intrinsic silicon with a thickness of 200 ± 20 μm.
3. The method according to claim 1, wherein the double-polished silicon substrate is cleaned in (1) by ultrasonic cleaning with acetone, alcohol and deionized water for 5 min.
4. The method of claim 1, wherein the thin film growth process of (2) comprises a chemical vapor deposition process and an atomic layer deposition process.
5. The method of claim 1, wherein the dense silicon nitride film grown in (2) has a thickness of 0.8 to 1.2 μm.
6. The method of claim 1, wherein in (3), the front and back surfaces of the substrate on which the dense silicon nitride film is grown are respectively subjected to photolithography, and the photolithography is performed by spin-coating a photoresist with a thickness of 1-3 μm on the silicon nitride film, and then sequentially performing pre-baking, exposure, development, and post-baking, thereby finally forming a photoresist pattern complementary to the electrode pattern on the photoresist on the front surface, and forming a window pattern corresponding to the front pattern on the photoresist on the back surface.
7. The method of claim 1, wherein the electrode pattern of (3) comprises an interdigitated electrode pattern and a parallel electrode pattern.
8. The method of claim 1, wherein the dry etching depth in (4) is the same as the thickness of the silicon nitride film.
9. The method of claim 1, wherein the wet etching of the substrate treated in (4) in (5) is performed by:
(5a) soaking the substrate for 1-2s by using a buffer oxide etching solution BOE to remove a natural oxide layer on the surface of the silicon;
(5b) etching the substrate by adopting 25 wt% of TMAH weak base solution, namely, keeping the solution temperature at 80-100 ℃ by adopting an oil bath system, etching for 5-8 hours at the etching rate of 1 mu m/min, and finishing etching after the substrate stops bubbling.
10. The method according to claim 1, wherein the step (5) of cleaning the substrate after wet etching comprises removing photoresist with acetone, sequentially ultrasonically cleaning with alcohol and deionized water, and drying to obtain the hollow hard mask.
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