CN101246375A - Low voltage drop stabilizer for regulating polar point, zero point, polar point and zero point cancellation control - Google Patents

Abstract

The invention discloses a low-voltage voltage stabilizer whose zero point and pole can cancellation control through regulating the zero point and pole properly. The voltage stabilizer comprises a regulation unit, an error magnifying apparatus, a Miller effect pole control unit, a pole and zero point cancellation delay unit and a feedback network. The pole and the zero point can be regulated adaptability according to the load changed mechanism, can maintain the stability of low-voltage voltage stabilizer in relative ideal phase margin in all load conditions.

Description

The low dropout voltage regulator that adjustment limit, zero point, pole and zero disappear mutually and control

Technical field

The present invention relates to a kind of low dropout voltage regulator (LDO), particularly relate to a kind of suitable adjustment limit (pole), zero point (zero), limit (pole) and the low dropout voltage regulator (LDO) of (cancellation) control that disappears mutually zero point (zero).

Background technology

Known control technology about low dropout voltage regulator (LDO) is US6 as being disclosed in the United States Patent (USP) number, 603,292, patent name is " LDO regulator having an adaptive zero frequencycircuit ", generally speaking, feedback signal can produce phase shift when transmitting in backfeed loop, phase shift can be defined as the phase change total amount that caused when this feedback signal is transmitted in backfeed loop, the phase differential of desirable negative feedback and source signal is 180 degree, therefore, the stability that actual phase differential and the difference between this desired phase difference will influence low dropout voltage regulator, decide on this phase place extent, if the difference between this actual phase difference and the desired phase difference has reached 180 degree (plus or minus), this feedback signal is identical with source signal so, thereby cause the low dropout voltage regulator instability, stability in order to ensure low dropout voltage regulator, phase margin (phase margin) should be higher than a minimum bit standard, and phase margin (phase margin) is defined as the total phase shift of feedback signal and poor from the number of degrees between ideal 180 degree of source signal under the same gain frequency.The known practice is shown in Figure 1A, and producing one can improve degree of stability with the zero point (zero) of load change.And its principle is that gm3 is operated in three polar body districts (triode region), utilize gm1 to detect the electric current of power MOS, when load current was big, the electric current of power MOS was just big, and the come electric current of gm2path of mapping (mirror) is also just big, this moment, the gm2 value also became big, make the voltage of gm2 gate end rise, make the gm3 value also and then become big, shown in Figure 1B, therefore equiva lent impedance R1 (being inversely proportional to gm3) also and then descends, and causes Zero (Z1) can drop on the place of high frequency.Otherwise, when load current is little, the electric current of power MOS is just little, the come electric current of gm2 path of mapping (mirror) is also just little, and this moment, gm2 value also diminished, and makes the voltage decline of gm2 gate end, make the gm3 value also and then diminish, therefore equiva lent impedance R1 (being inversely proportional to gm3) also and then rises, and causes Zero (Z1) can drop on the place of low frequency, please refer to shown in Figure 2.

In the middle of above-mentioned patent case, though zero point, (zero) can move along with load current, but but do not do some controls, therefore can cause limit (pole) and the phenomenon that has mutually disappear (cancellation) zero point (zero), factor beta=the R2/R1 that disappears mutually at limit (pole) and zero point (zero), therefore when load current is little, limit this moment (pole) has almost disappeared with zero point (zero) mutually, therefore, zero point this moment (zero) is just very little to the help of loop degree of stability, cause the reduction of phase margin (phase margin), make low dropout voltage regulator at load current hour, the performance of dynamic response, can be than load current large time difference, Fig. 3 is the phase margin (phase margin) and load current synoptic diagram of known low dropout voltage regulator (LDO), because the effect at zero point (zero), make low current phase margin (phase margin) by 60 several years fall to 40 the degree about, Fig. 4 is the jitter test synoptic diagram of the load current 0 to 150mA of known low dropout voltage regulator (LDO), by learning among the figure a little jitter phenomenon is arranged still.

Therefore how to do improvement at above-mentioned these shortcomings, make low dropout voltage regulator at load current hour, the performance of dynamic response can not be subjected to disappear mutually to influence yet, and becomes the subject under discussion that a quilt is paid close attention to.

Summary of the invention

The low dropout voltage regulator that the object of the present invention is to provide a kind of suitable adjustment limit, zero point, pole and zero to disappear mutually and control, solve general in the compensation low dropout voltage stabilizer, can do compensation at non-dominant pole (non-dominant pole), and be example at output terminal with dominant pole (dominant pole), when load current is big, because the output impedance of equivalence diminishes, therefore the loop gain of low dropout voltage regulator also just diminishes, and the dominant pole of this moment also can move toward high frequency, causes the frequency range in loop to become big.Opposite, when load current is little, because the output impedance of equivalence becomes big, therefore the loop gain of low dropout voltage regulator also just becomes big, the dominant pole of this moment also can move toward low frequency, causes problems such as the frequency range in loop diminishes, and other variety of issues that exist in the above-mentioned known technology.

To achieve these goals, the invention provides disappear the mutually low dropout voltage regulator of control of a kind of suitable adjustment limit, zero point, pole and zero, comprising:

One regulon comprises an input end, an output terminal and a control end, receives an input signal at this input end, and responds the control signal that this control end receives and provide an output signal at this output terminal;

One error amplifier, wherein an inverting input is connected to a reference voltage, and an output terminal is connected to one first end points;

One the Miller effect limit control module, comprise a P-type mos transistor AND gate one N type metal oxide semiconductor transistor series connection, the transistorized one source pole of this P-type mos is connected to this input end, one grid is connected to this first end points and this control end, one drain electrode is connected in series the transistorized source ground of this N type metal oxide semiconductor by one second end points with grid with this N type metal oxide semiconductor transistor drain;

The one pole and zero delay cell that disappears mutually connects this first end points, this second end points and this control end; And

One feedback network connects a non-inverting input of this output terminal and this error amplifier.

Design of the present invention is to be different from general fixing zero compensation, but design the circuit that a zero point and limit can change along with load current, when load current big, the frequency range of this moment is also big, the position at zero point is just in the place of high frequency, dominant pole (dominant pole) is pushed more low frequency to, do not wish that the limit of seeing shifts onto outside the frequency range in loop, when load current little, the frequency range of this moment is also little, will move zero point toward the direction of low frequency, and non-dominant pole (non-dominant pole) drops on high frequency.Such design, the low dropout voltage regulator that can make no matter at load current big or load current hour, can access sufficient compensation, produce goodish phase margin (phase margin).And when phase margin (phase margin) is good more, low dropout voltage regulator (be load current change from small to big suddenly or from large to small the time) when making Load Transient, dynamically the shake of wave mode is also just more little, even when phase margin (phase margin) good to a certain degree the time, dynamically just almost not shake of wave mode, this to some circuit to the voltage dithering sensitivity be of great use (as RF Circuit, ADC or the like), such low dropout voltage regulator not only can provide stable output voltage, the ability of good opposing power supply supply noise (power supply noise) more can be to the function do improvement to a certain degree of integrated circuit.

Describe the present invention below in conjunction with the drawings and specific embodiments, but not as a limitation of the invention.

Description of drawings

Figure 1A is the circuit diagram of known low dropout voltage regulator (LDO);

Figure 1B is the equivalent circuit diagram of known Fig. 1;

Fig. 2 is limit (pole) and the phase shifts synoptic diagram at zero point (zero) of known low dropout voltage regulator (LDO) under the unequally loaded situation;

Fig. 3 is the phase margin (phase margin) and load current synoptic diagram of known low dropout voltage regulator (LDO);

Fig. 4 is the jitter test synoptic diagram of the load current 0 to 150mA of known low dropout voltage regulator (LDO);

Fig. 5 A is the calcspar of low dropout voltage regulator of the present invention (LDO);

Fig. 5 B is the circuit diagram of low dropout voltage regulator of the present invention (LDO);

Fig. 5 C is the signal flow graph (SignalFlow Graph) of low dropout voltage regulator of the present invention (LDO) framework;

Fig. 5 D is limit (pole) and the phase shifts synoptic diagram at zero point (zero) of low dropout voltage regulator of the present invention (LDO) under the unequally loaded situation;

Fig. 6 is the phase margin (phase margin) and load current synoptic diagram of low dropout voltage regulator of the present invention (LDO); And

Fig. 7 is the jitter test synoptic diagram of the load current 0 to 150mA of low dropout voltage regulator of the present invention (LDO).

Wherein, Reference numeral:

500 regulons

510 error amplifiers

520 the Miller effect limit control modules

The 530 pole and zeros delay cell that disappears mutually

540 feedback networks

Embodiment

Fig. 5 A is the calcspar of low dropout voltage regulator of the present invention (LDO), this low dropout voltage regulator is a kind of suitable adjustment limit, zero point, the low dropout voltage regulator that pole and zero disappears mutually and controls, this low dropout voltage regulator comprises: a regulon 500, one error amplifier 510, one the Miller effect limit control module 520, one pole and zero disappear mutually a delay cell 530 and a feedback network 540, the pole and zero of the low dropout voltage regulator that the present invention carried can be with the machine-processed accommodation of load change, under all loading conditions, the degree of stability of low dropout voltage regulator can be maintained quite desirable phase margin (phase margin).

Fig. 5 B is the circuit diagram of low dropout voltage regulator of the present invention (LDO), this low dropout voltage regulator comprises a regulon 500, described regulon 500 is a P-type mos transistor or a N type metal oxide semiconductor transistor, be preferably the P-type mos transistor, comprise an input end Vin, an output end vo ut and a control end, receive an input signal at this input end, and respond the control signal that this control end receives and provide an output signal at this output terminal; One error amplifier 510, wherein an inverting input is connected to a reference voltage Vref, and an output terminal is connected to one first end points V1; One the Miller effect limit control module 520, comprise a P-type mos transistor AND gate one N type metal oxide semiconductor transistor series connection, the transistorized one source pole of this P-type mos is connected to this input end, one grid is connected to this first end points V1 and this control end, one drain electrode is connected in series the transistorized source ground of this N type metal oxide semiconductor by one second end points V2 with grid with this N type metal oxide semiconductor transistor drain; The one pole and zero delay cell 530 that disappears mutually, connect this first end points V1, this second end points V2 and this control end, the pole and zero delay cell 530 that disappears mutually also comprises an impact damper, wherein an inverting input of this impact damper connects this control end, one resistance (R1)-electric capacity (C1) series circuit connects this first end points and this second end points, and with the non-inverting input of this first end points as this impact damper; Wherein this first end points also and connect a resistance (R2)-electric capacity (C2) parallel circuit; Reach a feedback network 540, connect a non-inverting input of this output end vo ut and this error amplifier.

Fig. 5 C is the signal flow graph (SignalFlow graph) of low dropout voltage regulator of the present invention (LDO) framework, and its operation mainly is divided into three zones:

A.Strong?Inversion $(\mathrm{\&alpha;}=\frac{\mathrm{<figure-callout\; id="1"\; label="gm"\; filenames="A20071007980200131.png,A20071007980200141.png"\; state="\{\{state\}\}">gm</figure-callout>}1}{\mathrm{<figure-callout\; id="2"\; label="gm"\; filenames="A20071007980200141.png,A20071007980200171.png"\; state="\{\{state\}\}">gm</figure-callout>}2}=\mathrm{Cons}\tan t)$

$\mathrm{<figure-callout\; id="1"\; label="Z"\; filenames="A20071007980200131.png,A20071007980200141.png"\; state="\{\{state\}\}">Z</figure-callout>}1=\frac{1}{2\mathrm{\&pi;C}1(R1+\frac{1}{\mathrm{gm}2})}$ $\mathrm{<figure-callout\; id="1"\; label="P"\; filenames="A20071007980200131.png,A20071007980200141.png"\; state="\{\{state\}\}">P</figure-callout>}1=\frac{1}{2\mathrm{\&pi;C}1(1+\mathrm{<figure-callout\; id="1"\; label="gm"\; filenames="A20071007980200131.png,A20071007980200141.png"\; state="\{\{state\}\}">gm</figure-callout>}1/\mathrm{gm}2)R2}$ $\mathrm{<figure-callout\; id="2"\; label="P"\; filenames="A20071007980200141.png,A20071007980200171.png"\; state="\{\{state\}\}">P</figure-callout>}2=\frac{1}{2\mathrm{\&pi;C}2\frac{R1}{(1+\mathrm{<figure-callout\; id="1"\; label="gm"\; filenames="A20071007980200131.png,A20071007980200141.png"\; state="\{\{state\}\}">gm</figure-callout>}1/\mathrm{gm}2)}}$

Wherein above-mentioned, R1 is the resistance value of this resistance of this resistance-capacitance series circuit, C1 is the capacitance of this electric capacity of this resistance-capacitance series circuit, gm1 is transistorized first mutual conductance of this P-type mos, gm2 is transistorized second mutual conductance of this N type metal oxide semiconductor, R2 is the equivalent resistance of error amplifier output, and C2 is the equivalent capacitance value of error amplifier output.

This zone is to occur in electric current bigger the time, almost be that tens of mA are to hundreds of mA, because the output current in this time is very big, so the equiva lent impedance of output is also just very little, therefore shown in Fig. 5 D, for stablizing of loop, PLoad is generally non-dominant pole (non-dominant pole), this moment, V1 was dominant pole (dominant pole) just, and the automatic adjustment limit (adaptive pole) of this circuit is because C1 has the relation of the Miller effect (miller effect), wherein, Miller factor alpha=gm1/gm2 can be with dominant pole (dominant pole; P1) push away (1+gm1/gm2) more inward doubly, can make again P2 (our undesired non-dominant pole) can be more to extrapolation (1+gm1/gm2) doubly, make that the phase margin (phasemargin) in whole loop can be better, more can keep the stability in loop, and automatic adjustment zero point (adaptive zero) of this moment is by C1, R1 determines (proportion of R1 is much larger than 1/gm2), and it is used for compensating PLoad, the stability in whole loop can be done the optimization compensation.

B.Weak?Inversion $(\mathrm{\&alpha;}=\frac{\mathrm{<figure-callout\; id="1"\; label="gm"\; filenames="A20071007980200131.png,A20071007980200141.png"\; state="\{\{state\}\}">gm</figure-callout>}1}{\mathrm{<figure-callout\; id="2"\; label="gm"\; filenames="A20071007980200141.png,A20071007980200171.png"\; state="\{\{state\}\}">gm</figure-callout>}2}\&cong;1)$

$\mathrm{<figure-callout\; id="1"\; label="Z"\; filenames="A20071007980200131.png,A20071007980200141.png"\; state="\{\{state\}\}">Z</figure-callout>}1=\frac{1}{2\mathrm{\&pi;C}1(\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="A20071007980200131.png,A20071007980200141.png"\; state="\{\{state\}\}">R</figure-callout>}1+\frac{1}{\mathrm{gm}2})}$ $\mathrm{<figure-callout\; id="1"\; label="P"\; filenames="A20071007980200131.png,A20071007980200141.png"\; state="\{\{state\}\}">P</figure-callout>}1=\frac{1}{2\mathrm{\&pi;C}1\left(2\right)R2}$ $\mathrm{<figure-callout\; id="2"\; label="P"\; filenames="A20071007980200141.png,A20071007980200171.png"\; state="\{\{state\}\}">P</figure-callout>}2=\frac{1}{2\mathrm{\&pi;C}2\frac{R1}{\left(2\right)}}$

Wherein above-mentioned, R1 is the resistance value of this resistance of this resistance-capacitance series circuit, C1 is the capacitance of this electric capacity of this resistance-capacitance series circuit, gm2 is transistorized second mutual conductance of this N type metal oxide semiconductor, R2 is the equivalent resistance of error amplifier output, and C2 is the equivalent capacitance value of error amplifier output.

When load current slowly reduces, almost be that number mA are during to tens of mA, the resistance of output is just slowly increase also, therefore also moving gradually of PLoad to low frequency, so, at this moment dominant pole (dominantpole) is PLoad, when electric current is little during to a degree, gm1 and gm2 can enter the state of weak inversion gradually, and the gm of this moment is just almost only with current related (α is decreased to 1), therefore the Miller effect (miller effect) effect of P1 dies down at this moment, level off to one times, make P1 (non-dominant pole) can drop on the place of higher-frequency, improve degree of stability, and the Z1 of this moment, because the electric current of gm2 also and then diminishes,,, the proportion of 1/gm2 increases so also just following so gm2 also just and then diminishes, therefore, Z1 can move toward the direction of low frequency along with output current must diminish.Therefore from whole loop, load current reduces, and the frequency range in loop also diminishes, and this moment, the zero point can move to the place than low frequency, can be to non-dominant pole (non-dominant pole; P1) do effective compensation, can keep the good phase margin in loop (phase margin) with degree of stability.

C.Light?Load

$\mathrm{<figure-callout\; id="1"\; label="Z"\; filenames="A20071007980200131.png,A20071007980200141.png"\; state="\{\{state\}\}">Z</figure-callout>}1=\frac{1}{2\mathrm{\&pi;C}1\left(\frac{1}{\mathrm{gm}2}\right)}$ $\mathrm{<figure-callout\; id="1"\; label="P"\; filenames="A20071007980200131.png,A20071007980200141.png"\; state="\{\{state\}\}">P</figure-callout>}1=\frac{1}{2\mathrm{\&pi;C}1\left(\frac{1}{\mathrm{gm}2}\right)}$ $\mathrm{<figure-callout\; id="2"\; label="P"\; filenames="A20071007980200141.png,A20071007980200171.png"\; state="\{\{state\}\}">P</figure-callout>}2=\frac{1}{2\mathrm{\&pi;C}2\mathrm{<figure-callout\; id="2"\; label="R"\; filenames="A20071007980200141.png,A20071007980200171.png"\; state="\{\{state\}\}">R</figure-callout>}2}$

Wherein above-mentioned, C1 is the capacitance of this electric capacity of this resistance-capacitance series circuit, and gm2 is transistorized second mutual conductance of this N type metal oxide semiconductor, and R2 is the equivalent resistance of error amplifier output, and C2 is the equivalent capacitance value of error amplifier output.

Littler when electrorheological it's time to count mA even littler for a short time, and the direction of the more past low frequency of PLoad this moment is walked, and P1 can be more close with Z1, has the effect of cancellation at last, the limit (pole) and the coefficient that disappears mutually at zero point (zero)

$\mathrm{\&beta;}=R2/\left(\frac{1}{\mathrm{gm}2}\right),$

But because we have the control of being pole and Zero cancallation, be exactly to utilize the zone of creating a Weak Inversion, slow down the generation of pole and zero cancellation, therefore in the time of pole and zero cancellation generation, the PLoad of this moment is in the unusual place of low frequency, and the frequency range in loop is also than dominant pole (non-dominant pole; P2) also will be in the position of low frequency more, the influence that therefore is subjected to P2 will be very little, so good phase margin (phase margin) still can be kept with degree of stability in the loop.

According to above analysis, in order to keep the degree of stability in loop, we produce the degree of stability that three operating areas are controlled low dropout voltage regulator (LDO), (1) at heavy load (high capacity) (strong inversion, oppositely strong) time, we utilize the slow down speed of limit (pole) and disappear mutually zero point (zero) (cancellation) of R1, and utilize the effect of the Miller effect, dominant pole (dominant pole) is pushed away toward low frequency, the more past high frequency of undesirable limit (pole) pushes away, shift onto away from outside the frequency range of loop, improve phase margin (phase margin) with degree of stability.(2) at heavy load (weak inversion, oppositely weak) time, electric current according to load changes (zero) value at zero point, it is moved toward low frequency do more efficient compensation, have the effect of automatic adjustment (adaptive) zero point (zero) of this moment, and the Miller effect is also no longer so obvious, the non-dominant pole that makes (non-dominant pole) can be in the position of higher-frequency, the limit (pole) of this moment also is the effect with automatic adjustment (adaptive), again because dominant pole (dominant pole) is PLoad, non-dominant pole (non-dominant pole) is v1, therefore the phase margin (phase margin) in loop can not be affected with degree of stability, still can keep good situation.(3) in light load (low load), very low current the time, though the effect of limit (pole) and disappear mutually zero point (zero) (cancellation) produces, zero point, the effect of (zero) did not almost have, but we utilize R1 to do limit (pole) and control that zero point, (zero) disappeared mutually because have, therefore can control when dominant pole (dominant pole) and move to enough low frequencies, the frequency range of this moment is than non-dominant pole (non-dominant pole) also more low frequency the time, limit (pole) just can take place with disappear mutually zero point (zero) (cancellation), therefore can keep the goodish phase margin of low dropout voltage regulator (phase margin) with degree of stability.Therefore, automatic adjustment limit of the present invention (adaptivepole), automatically adjust zero point (adaptive zero), limit (pole) with disappear mutually zero point (zero) (cancellation) control low dropout voltage regulator (LDO), can be under the situation of all load currents, can both adjust limit automatically or keep the good stable degree zero point, this to some concerning the circuit application of circuit jitter sensitivity, be considerable, and can overcome the problem that the LDO compensation is difficult for, with under the opereating specification of voltage, can keep goodish phase margin (phase margin) at very big load current with degree of stability.

Fig. 6 is the phase margin (phase margin) and load current synoptic diagram of low dropout voltage regulator of the present invention (LDO), owing to the effect of limit (pole) with (cancellation) control that disappears mutually zero point (zero), make the phase margin (phase margin) of low current can keep about 64 degree, can be because of the variation of load current variation, Fig. 7 is the jitter test synoptic diagram of the load current 0 to 150mA of low dropout voltage regulator of the present invention (LDO), by learning among the figure that jitter phenomenon significantly improves.

Certainly; the present invention also can have other various embodiments; under the situation that does not deviate from spirit of the present invention and essence thereof; those of ordinary skill in the art can make various corresponding changes and distortion according to the present invention, but these corresponding changes and distortion all should belong to the protection domain of the appended claim of the present invention.

Claims (8)

1. adjust the low dropout voltage regulator that limit, zero point, pole and zero disappear mutually and control for one kind, it is characterized in that this low dropout voltage regulator comprises:

One regulon comprises an input end, an output terminal and a control end, receives an input signal at this input end, and responds the control signal that this control end receives and provide an output signal at this output terminal;

One error amplifier, wherein an inverting input is connected to a reference voltage, and an output terminal is connected to one first end points;

One the Miller effect limit control module, comprise a P-type mos transistor AND gate one N type metal oxide semiconductor transistor series connection, the transistorized one source pole of this P-type mos is connected to this input end, one grid is connected to this first end points and this control end, one drain electrode is connected in series the transistorized source ground of this N type metal oxide semiconductor by one second end points with grid with this N type metal oxide semiconductor transistor drain;

The one pole and zero delay cell that disappears mutually connects this first end points, this second end points and this control end; And

One feedback network connects a non-inverting input of this output terminal and this error amplifier.

2. low dropout voltage regulator according to claim 1 is characterized in that, this regulon is a P-type mos transistor or a N type metal oxide semiconductor transistor.

3. low dropout voltage regulator according to claim 1, it is characterized in that, this pole and zero delay cell that disappears mutually also comprises an impact damper, wherein an inverting input of this impact damper connects this control end, one resistance-capacitance series circuit connects this first end points and this second end points, and with the non-inverting input of this first end points as this impact damper.

4. low dropout voltage regulator according to claim 3 is characterized in that, this first end points also and connect a resistance-capacitance parallel circuit.

5. low dropout voltage regulator according to claim 4 is characterized in that, limit (P1) is defined as follows:

$P1=\frac{1}{2\mathrm{\&pi;C}1(1+\mathrm{gm}1/\mathrm{gm}2)R2}.$

Wherein, C1 is the capacitance of this electric capacity of this resistance-capacitance series circuit, gm1 is transistorized first mutual conductance of this P-type mos, and gm2 is transistorized second mutual conductance of this N type metal oxide semiconductor, and R2 is the equivalent resistance of this error amplifier output.

6. low dropout voltage regulator according to claim 4 is characterized in that, limit (P2) is defined as follows:

$P2=\frac{1}{2\mathrm{\&pi;C}2\frac{R1}{(1+\mathrm{gm}1/\mathrm{gm}2)}}$

Wherein, C2 is the equivalent capacitance value of this error amplifier output, gm1 is transistorized first mutual conductance of this P-type mos, and gm2 is transistorized second mutual conductance of this N type metal oxide semiconductor, and R1 is the resistance value of this resistance of this resistance-capacitance series circuit.

7. low dropout voltage regulator according to claim 4 is characterized in that, this zero point, (Z1) was defined as follows:

$Z1=\frac{1}{2\mathrm{\&pi;C}1(R1+\frac{1}{\mathrm{gm}2})}$

Wherein, C1 is the capacitance of this electric capacity of this resistance-capacitance series circuit, and gm2 is transistorized second mutual conductance of this N type metal oxide semiconductor, and R1 is the resistance value of this resistance of this resistance-capacitance series circuit.

8. low dropout voltage regulator according to claim 1 is characterized in that, this feedback network is a voltage divider, and a dividing point of this voltage divider is connected to this non-inverting input of this error amplifier.

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