CN101192541A - 半导体器件及其制造方法 - Google Patents
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Abstract
本发明提供一种半导体器件及其制造方法。其中该半导体器件包括：半导体衬底，其包括源极/漏极区域和在该源极/漏极区域之间的沟道；在该沟道上的栅极氧化层图案；在该栅极氧化层图案上的金属氮化层图案；在该金属氮化层图案上的硅化物；以及在该栅极氧化层图案、该金属氮化层图案和该硅化物的侧面上的间隔物。在一个实施例中，该金属氮化层图案的厚度是该硅化物的1/4至1/2。
Description
技术领域
本发明涉及半导体器件及其制造方法。
背景技术
大部分互补金属氧化物半导体(CMOS)器件包括由多晶硅形成的栅极。如果栅极由多晶硅形成，则不管它们大小如何，都不可避免地形成耗尽层。当半导体器件的集成度不高时，可以形成相对较大的多晶硅栅极。因此，即使形成耗尽层，也可以忽略电特性的降低。
然而，随着半导体器件的高度集成，栅极大小也进一步缩小，从而使得在栅极中形成的耗尽层的影响相对较大。耗尽层是使半导体器件的性能降低的一个因素。也就是说，耗尽层被认为是在使用多晶硅的半导体器件中的重要问题。已提出将金属栅极作为用于防止由耗尽层造成的半导体器件性能降低的一种途径。
然而，当形成金属栅极时，一般难以执行金属蚀刻。因此，并非执行先加工栅极工艺(即通过光刻首先直接形成栅电极)，可以执行代替的栅极工艺，即在牺牲层中的沟槽和具有金属的沟槽中定义栅极区域。然而，这种代替的栅极工艺可能具有未对准的问题。
发明内容
本发明的实施例提供一种半导体器件及其制造方法，该半导体器件可以防止或减少通过使用多晶硅电极产生的耗尽层所可能引起的故障。
在一个实施例中，一种半导体器件包括：半导体衬底，其包括源极/漏极区域和在所述源极/漏极区域之间的沟道；在该沟道上的栅极氧化层图案；在该栅极氧化层图案上的金属氮化层图案；在该金属氮化层图案上的硅化物；以及在该栅极氧化层图案、该金属氮化层图案和该硅化物侧面上的间隔物。该金属氮化层图案是该硅化物厚度的1/4至1/2(例如1/3至1/2)。
在附图和以下描述中将阐述一个或多个实施例的细节。通过描述和附图以及权利要求书，其它特征将是明显的。
附图说明
图1至4是说明根据本发明实施例的半导体器件的制造方法的横截面图。
图5是根据本发明实施例的半导体器件的横截面图。
具体实施方式
现在详细参考本发明公开的实施例，在附图中说明本发明的实例。
图1至4是说明根据本发明实施例的半导体器件的制造方法的横截面图，图5是根据本发明实施例的半导体器件的横截面图。
参考图1，通过已知方法在半导体衬底10上生长或沉积栅极氧化层20。栅极氧化层20可以包括热生长的二氧化硅或高介电常数(高k)氧化物(例如氮氧化硅、氮化硅、二氧化铪等)，其可以被热生长(例如，通过几乎同时对硅进行氧化/氮化，或通过对被溅射的铪进行氧化)或沉积(例如，通过化学气相沉积)。可以在沉积处理之后对所沉积的栅极氧化层20进行热退火。在另一实施例中，栅极氧化层20可以包括双层结构，例如在上面覆盖有高k氧化物以及在下面有二氧化硅缓冲层。
在该栅极氧化层20上依次形成金属氮化层30和多晶硅层40。该金属氮化层30可以包括金属氮化物，所述金属氮化物在典型的处理条件下粘附到该栅极氧化层20下面，并提供足以最小化或减小该下层沟道中的任一耗尽层的栅电极运行功能。例如，该金属氮化层30的分子式为MNx，其中x至少为1且一般约是2，M是可以形成导电氮化物的难熔金属和/或过渡金属。在各种实施例中，M可以是钴、镍、钨、钼、钛、铪或钽，但优选地是提供高导电性氮化物的金属(诸如钴)。通常，该金属氮化层30的厚度为可以通过反应离子蚀刻(RIE)工艺等容易地进行干蚀刻。为此，该金属氮化层30的厚度可以是该多晶硅层40的厚度的1/3至1/2。可选择地或另外地，该金属氮化层30的厚度范围可以从约20nm到约30nm，和/或该多晶硅层40的厚度范围可以从50nm到约100nm。
参考图2，将光致抗蚀剂(未示出)涂覆在该多晶硅层40上，并且利用曝露装置例如分档器(stepper)将光致抗蚀剂图案投射到该光致抗蚀剂上。对于所投射的光致抗蚀剂图案(未示出)进行显影以形成光致抗蚀剂图案(未示出)。接着，对于该多晶硅层40、该金属氮化层30和该栅极氧化层20依次进行干蚀刻以分别形成多晶硅层图案41、金属氮化层图案31和栅极氧化层图案21。根据蚀刻条件，该干蚀刻操作可以同时蚀刻该多晶硅层40和该金属氮化层30，或可以依次蚀刻该多晶硅层40和该金属氮化层30。
参考图3，通过利用已知方法将低浓度的杂质离子注入到该半导体衬底10的暴露表面中，在该半导体衬底10中形成轻掺杂的漏极(LDD)11。接着，在该多晶硅图案41、该金属氮化层图案31和该栅极氧化层图案21的侧面上形成间隔物S。间隔物S一般包括一层或多层介电材料，例如二氧化硅、氮化硅、氧氮化硅等。在某些实施例中，间隔物S包括双层(例如在二氧化硅上有氮化硅)结构或三层(例如二氧化硅/氮化硅/二氧化硅堆)结构。通过利用该多晶硅层图案41和所述间隔物S作为离子注入掩模来注入高浓度杂质离子(一般是与用于LDD区域11相同的导电类型)，形成源极/漏极区域12。
参考图4，在该半导体衬底10上沉积金属(例如，钴、镍、钨、钼、钛、铪或钽，但优选地是钴(Co)或镍(Ni))层50，并且执行第一快速热处理(RTP)以在该源极/漏极区域12和该多晶硅层图案41上形成第一硅和金属的化合物(例如CoSi)。因此，金属50一般是在用于形成金属硅化物的传统退火条件下可以形成金属硅化物的化合物的金属。在一个实施例中，该金属50与该金属氮化层30的金属相同。将剩余的金属层50除去，并且执行第二RTP，以在该源极/漏极区域12和该多晶硅层图案41上形成略有不同的金属硅化物，即，第二硅和金属的化合物(CoSi2)(如图5所示)。因此，所沉积的金属50的厚度应该为足以提供用以形成第二金属硅化物的化合物所需的金属原子的量。此外，金属层50对于多晶硅层40的相对厚度应足以将多晶硅层图案41和其上的金属层50都转变成第二金属硅化物的化合物。
参考图5，沟道留在该源极/漏极区域12之间的该半导体衬底10中，并且在该沟道上有栅极氧化层图案21。金属氮化层图案31在该栅极氧化层图案21上，并且完全硅化的多晶硅(FUSI)60在该金属氮化层图案31上。将该完全硅化的多晶硅60称作硅化物。该金属氮化层图案31的厚度可以是该硅化物60的厚度的1/4至1/2(例如1/3至1/2)。该金属氮化层图案31的厚度范围可以从约20nm至约30nm，而该硅化物60的厚度范围可以从50nm到约100nm。
间隔物S在该栅极氧化层图案21、该金属氮化层图案31和该硅化物60的侧面(相对面)上。
包括金属氮化层图案和硅化物的栅电极在该栅极氧化层图案21上。因此，相比由多晶硅形成的相关的栅电极，在该栅电极中形成耗尽层的可能性降低，从而减少或防止该半导体器件的故障。
此外，优选地，该金属氮化层具有可对其进行干蚀刻的厚度，并且可以在该金属层上形成该多晶硅层。可以同时蚀刻该多晶硅层和该金属氮化层(例如，依次在原位蚀刻和/或不破坏蚀刻室中的真空蚀刻)。因此，相比现有技术，可容易执行金属蚀刻，并且可以避免或防止在代替的栅极工艺中潜在的未对准问题。换句话说，在保持先加工栅极工艺的同时(例如通过光刻首先直接形成栅电极)，可以降低形成耗尽层的可能性，并且可以避免或防止潜在的未对准问题。
在本说明书中的引用的“一个实施例”、“实施例”、“示例性实施例”等意思是根据该实施例所描述的特定特征、结构或特性包括在本发明的至少一个实施例中。在该说明书中的各处出现的此种短语不必所有都指示相同的实施例。此外，当根据任一实施例描述特定特征、结构或特性时，可以理解的是，本领域技术人员可以在本领域的范围内根据其它实施例实现此特征、结构或特性。
虽然已参考本发明多个说明性实施例来描述这些实施例，但需要明白的是，在本发明所公开的原理的精神和范围内，本领域的技术人员可以设计出多种其它修改和实施例。特别地，对于在本发明所公开的说明书、附图和附加的权利要求书的范围内的组合部分和/或主要组合结构的排列可以进行各种变更和修改。除了在组合部分和/或排列中的各种变更和修改之外，对于本领域的技术人员而言，可选择的用途也是明显的。
Claims (21)
1.一种半导体器件的制造方法，包括：
在半导体衬底上形成栅极氧化层、金属氮化层和多晶硅层；
对所述多晶硅层、所述金属氮化层和所述栅极氧化层进行图案化；
将离子注入到所述半导体衬底的暴露区域中；
在所述半导体衬底和所述图案化的多晶硅层上沉积金属层，并且执行第一快速热处理；以及
除去剩余的金属，并执行第二快速热处理以形成金属硅化物。
2.如权利要求1所述的方法，其中所述金属氮化层的厚度是所述多晶硅层的厚度的1/3至1/2。
3.如权利要求1所述的方法，其中所述金属层的厚度范围从约20nm到约30nm。
4.如权利要求1所述的方法，其中所述多晶硅层的厚度范围从约50nm到约100nm。
5.如权利要求1所述的方法，其中在所述多晶硅层上形成光致抗蚀剂图案，并且利用所述光致抗蚀剂图案作为蚀刻掩模来依次蚀刻所述多晶硅层、所述金属氮化层和所述栅极氧化层。
6.如权利要求1所述的方法，其中所述第一快速热处理形成第一金属硅化物的化合物，而所述第二快速热处理形成与所述第一金属硅化物的化合物不同的第二金属硅化物的化合物。
7.如权利要求6所述的方法，其中所述金属层的厚度足以提供用以形成所述第二金属硅化物的化合物所需的金属原子的量。
8.如权利要求7所述的方法，其中所述金属层和所述多晶硅层图案的厚度足以将所述多晶硅层图案和所述金属层基本全都转变成所述第二金属硅化物的化合物。
9.如权利要求1所述的方法，其中所述栅极氧化层包括高介电常数氧化物，即高k氧化物。
10.如权利要求1所述的方法，其中所述金属氮化层包括从钴、镍、钨、钼、钛、铪和钽中选择的第一金属的氮化物。
11.如权利要求1所述的方法，其中所述金属硅化物包括从钴、镍、钨、钼、钛、铪和钽中选择的第二金属的硅化物。
12.如权利要求9所述的方法，其中所述第一金属和所述第二金属包括同样的金属。
13.如权利要求1所述的方法，其中所述将离子注入到所述半导体衬底的暴露区域中的步骤形成轻掺杂漏极。
14.如权利要求13所述的方法，还包括在所述图案化的多晶硅层、图案化的金属氮化层和图案化的栅极氧化层的侧面上形成间隔物，然后将离子注入到所述半导体衬底的新暴露区域中，以形成源极/漏极端。
15.一种半导体器件，包括：
半导体衬底，其包括源极/漏极区域和所述源极/漏极区域之间的沟道；
在所述沟道上的栅极氧化层图案；
在所述栅极氧化层图案上的金属氮化层图案；
在所述金属氮化层图案上的硅化物；以及
在所述栅极氧化层图案、所述金属氮化层图案和所述硅化物的侧面上的间隔物，
其中所述金属氮化层图案的厚度是所述硅化物厚度的1/4至1/2。
16.如权利要求15所述的半导体器件，其中所述金属氮化层图案的厚度范围从约20nm至约30nm。
17.如权利要求15所述的半导体器件，其中所述硅化物的厚度范围从约50nm至约100nm。
18.如权利要求16所述的半导体器件，其中所述栅极氧化层包括高介电常数氧化物，即高k氧化物。
19.如权利要求15所述的半导体器件，其中所述金属氮化层包括从钴、镍、钨、钼、钛、铪和钽中选择的第一金属的氮化物。
20.如权利要求15所述的半导体器件，其中所述金属硅化物包括从钴、镍、钨、钼、钛、铪和钽中选择的第二金属的硅化物。
21.如权利要求20所述的半导体器件，其中所述第一金属和所述第二金属包括同样的金属。
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| US20120038048A1 (en) * | 2010-08-11 | 2012-02-16 | International Business Machines Corporation | Stabilized nickel silicide interconnects |
| CN103928329B (zh) * | 2013-01-10 | 2016-08-03 | 中芯国际集成电路制造(上海)有限公司 | Mos晶体管及其形成方法 |
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| US6503833B1 (en) * | 2000-11-15 | 2003-01-07 | International Business Machines Corporation | Self-aligned silicide (salicide) process for strained silicon MOSFET ON SiGe and structure formed thereby |
| DE10234931A1 (de) * | 2002-07-31 | 2004-02-26 | Advanced Micro Devices, Inc., Sunnyvale | Verfahren zur Herstellung eines Metallsilizidgates in einer standardmässigen MOS-Prozesssequenz |
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