CN101164149B - 具有沉积氧化物的沟槽金属氧化物半导体场效应晶体管 - Google Patents
具有沉积氧化物的沟槽金属氧化物半导体场效应晶体管 Download PDFInfo
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Abstract
一种沟槽型的功率半导体设备,包括所述沟槽内沉积的而非生成的氧化物,从而将设置在所述沟槽内的电极电隔离于所述半导体主体。
Description
相关申请
本申请基于2004年10月29日提交的名称为“Trench MOSFET StructuresUsing Deposited Oxide With Spacers”的美国临时申请No.60/623,679并且要求其优先权,其公开内容作为参考而结合于此。
技术领域
本发明涉及一种半导体设备并且尤其涉及沟槽型功率半导体设备。
背景技术
通常的沟槽型功率半导体设备包括在沟槽内部支持的栅极结构。所述栅极结构包括导电栅电极,通过绝缘体而绝缘于设备的半导体主体,这种绝缘体通常为二氧化硅。
如同所公知的,沟槽底部的高电场可能损害设备的整体性。为了克服该问题,在栅极下方沟槽底部处形成厚氧化物。
传统的制造该厚氧化物的方法是通过对硅进行氧化而进行的。然而,氧化非常耗时,并且成本很高。并且,氧化消耗硅。因此,设备的单元属性受到不利影响,从而对设备每单位面积的电流承载能力造成不利影响。
发明内容
本发明的一个目标是改进现有的设备和制造技术。
根据本发明一个实施方式的功率半导体设备包括半导体主体,该半导体主体包括具有一种导电性的漂移区以及在所述漂移区上具有另一种导电性的通道区;至少通过所述通道区在所述半导体主体中形成的栅极沟槽;设置在所述栅极沟槽底部的氧化体;形成在所述氧化体上的栅电极;以及介于所述栅极沟槽的侧壁和所述栅电极之间的栅极氧化物。
根据本发明一个方面,所述氧化体为可沉积的二氧化硅(例如TEOS);而所述栅极氧化物是使用氧化技术生成的。因此,在根据本发明的设备中,所述氧化体不如所述栅极氧化物紧致。
根据本发明另一个方面,根据本发明的设备包括场释放沟槽,具有凹部的场氧化体,以及至少部分容纳在所述凹部中的T形电极。所述T形电极延伸至栅电极的深度下方,并且电连接到所述设备的功率电极以提高设备的击穿电压。
应当注意,所述氧化体、场氧化体优选的均通过相同的可沉积氧化物(例如TEOS)而形成,并且均比所述栅极氧化物更厚。
为了制造根据本发明的设备,在半导体主体中形成沟槽,在沟槽底部沉积氧化体,并且在氧化体上形成电极。
根据本发明另一个方面,使用沟槽内的隔片以形成凹部,支持所述场释放电极在所述栅电极深度以下的延伸。
本发明的其他特征和优点通过下面的参考附图的详细描述可以更加明白。
附图说明
图1显示了根据本发明一个实施方式的设备的有源单元的截面图;以及
图2A-2Q图形化显示了制造根据本发明的设备的方法。
具体实施方式
参考图1,根据本发明的功率半导体设备包括半导体主体10。半导体主体10优选的包括半导体基底12,可以为漂浮区型、单晶体、硅,以及附生的半导体主体14,例如在基底12上形成的附生硅。附生的半导体主体14包括漂移区16、通道区(有时称为主体区)18以及通道区18上的导电区20。如同本领域公知的,漂移区16以及导电区20具有一种导电性,而通道区18具有另一种相反的导电性。因此,当漂移区16和导电区20为N型导电性时,通道区18为P型导电性,并且当漂移区16和导电区20为P型导电性时,通道区18为N型导电性。
根据优选实施方式的功率半导体设备为垂直导电型功率MOSFET(金属氧化物半导体场效应晶体管)。因此,基底12具有与漂移区16相同的导电性,尽管在通常情况下它与漂移区16相比更加高度掺杂。作为一个示例,图1显示了垂直导电型功率MOSFET,其中漂移区16为N型并且通道区18为P型,即N通道设备。通过逆转N通道设备中各个区的极性可以获得P通通设备。
根据本发明的设备包括栅极沟槽22,延伸通过至少通道区18。根据本发明,氧化物(例如二氧化硅)主体24设置在栅极沟槽22的底部。栅电极25(例如通过导电多晶硅形成)通过介于栅极沟槽22的侧壁和通道区18之间的栅极氧化物28而间隔于通道区16。根据本发明一个方面,氧化体24被沉积,而栅极氧化物28被生成。例如,在优选实施方式中,氧化体24为沉积的TEOS,而栅极氧化物28通过栅极氧化工艺而生成。因此,根据本发明一个方面的氧化体24不如栅极氧化物28紧致。
根据本发明的设备进一步包括第一功率电极30(例如用Al或者AlSi形成),第一功率电极30优选的通过置于导电区20上的硅化体32而电连接到导电区20。第二功率电极34(例如用Al或者AlSi形成)电连接到基底12。在优选实施方式中,第一功率电极30为源电极,而第二功率电极34为漏电极。
根据本发明另一个方面,根据本发明的设备进一步包括场释放沟槽36,延伸到漂移区16中。场释放沟槽36在其底部支撑场氧化体38。场氧化体38优选地用与氧化体24相同的氧化物而形成(例如TEOS),并且包括凹部40。优选的T形场电极42(例如用导电多晶硅形成)驻留在凹部40内并且填充凹部40,并且延伸至凹部40以外,在场氧化体38上横向延伸。第一功率电极30通过硅化体32电连接到场电极42。优选的,具有与通道区18相同导电性的高导电区44形成在场释放沟槽36的侧壁上,以降低硅化体32与通道区18之间的接触电阻,从而降低由于漏电流等等激活寄生设备的可能性。场释放电极42能够改进设备的击穿功能,从而允许降低漂移区16的电阻,这是通过降低其厚度(这样还可以降低设备成本)或者其掺杂浓度而实现的。还应当注意,在优选实施方式中,第功率电极的一部分容纳在场释放沟槽36内。进一步应当注意,氧化体24和场氧化体38比栅极氧化物28更厚。
参考图2A-2Q,根据本发明的设备如下制造。开始,如图2A所示,在设置在半导体基底12(例如N型Si)上方的附生半导体14(例如N型Si)上生成衬垫氧化物48。优选的,基底12掺杂了红磷。
接着,通道掺杂物被注入附生形成的硅14中,以形成通道注入区46(图2B)。接着,优选的通过氮化物形成的硬掩模50形成在衬垫氧化物48上(图2C),并且图案形成为指定将被蚀刻以形成沟槽的附生半导体14的区域。此后,附生半导体14被蚀刻以产生如图2D所示的栅极沟槽22和场释放沟槽36。
接着,在沟槽22、36的侧壁和底部上生成牺牲氧化物52(图2E),并且沉积例如TEOS 54等氧化物以如图2F所示填充沟槽22、36。此后,TEOS54被去除,只留下氧化体24和场氧化体38。然后如图2G所示沉积另一个氮化物层56。氮化物层56然后被蚀刻,留下如图2H所示的氮化物隔片58。
接着,在栅极沟槽22上形成栅极保护掩模60,并且蚀刻场氧化体38以在其中形成如图2I所示的凹部40。此后,掩模60和氮化物隔片56被去除以获得如图2J所示的结构。然后,从沟槽22、36的侧壁去除衬垫氧化物52,暴露的侧壁在栅极氧化工艺中被氧化以形成栅极氧化物28,并且沉积导电多晶硅62以填充沟槽22、36,如图2K所示。然后多晶硅62被去除,仅留下栅电极25,以及场释放电极42,如图2C所示。此后,沉积另一个TEOS层64(图2M)以填充栅电极25上方的空间以及场释放电极42上方的空间。然后TEOS 64被蚀刻,仅留下栅电极25以及场释放电极42上方的绝缘盖29,如图2N所示。
接着参考图2O,氮化物掩模50以及衬垫氧化物48被去除,并且然后注入掺杂物以形成导电区20。此后,通道注入区46中的掺杂物以及形成导电区20的注入物在扩散驱动中被驱动以获得漂移区16、通道区18以及导电区20。
接着,在栅极沟槽22上形成栅极保护掩模66,并且场释放沟槽36中的氧化物盖29被去除。并且,场释放电极42的顶部局部以及与被去除部分相邻的氧化物被蚀刻去除,从而通道区18通过场释放电极42上方的场释放沟槽36的侧壁而暴露。使用斜角注入技术,与通道区18具有相同导电性的掺杂物被注入场释放沟槽36的暴露侧壁内,并且在扩散驱动中被驱动为高导电区44,如图2P所示。
此后,栅极保护掩模66被去除,并且在传统的硅化物工艺中形成硅化体32以获得如图2Q所示的结构。此后,第一功率电极30和第二功率电极34通过任何公知方法例如喷射等等被形成以获得根据本发明的设备。
尽管参考特定实施例描述了本发明,各种其他变化和修改以及其他使用对于本领域技术人员来说是显见的。因此,优选的本发明并不限于在此公开的特定内容,而是仅由所附权利要求限制。
Claims (10)
1.一种功率半导体设备,包括:
半导体主体,包括具有一种导电性的漂移区以及在所述漂移区上具有另一种导电性的通道区;
至少通过所述通道区在所述半导体主体中形成的栅极沟槽,所述栅极沟槽包括侧壁和底部壁;
设置在所述沟槽底部的氧化体;
形成在所述氧化体上的栅电极;
介于所述沟槽的侧壁和所述栅电极之间的栅极氧化物,其中所述氧化体不如所述栅极氧化物紧致;以及
场释放沟槽,具有场氧化体、和置于所述场氧化体内的场电极、以及电连接到所述场电极的功率电极,所述功率电极的一部分容纳在所述场释放沟槽内。
2.根据权利要求1所述的功率半导体设备,其中所述氧化体包括TEOS。
3.根据权利要求1所述的功率半导体设备,其中所述场释放沟槽的所述场氧化体包括凹部,并且所述场电极包括至少部分容纳于所述凹部内的T形电极。
4.根据权利要求1所述的功率半导体设备,其进一步包括介于所述半导体主体和所述功率电极之间的硅化体。
5.根据权利要求3所述的功率半导体设备,其进一步包括介于所述T形电极和所述功率电极之间的硅化体。
6.根据权利要求1所述的功率半导体设备,其进一步包括:
至少一个高导电区,形成在所述场释放沟槽的至少一个侧壁中,具有与所述通道区相同的导电性,所述功率电极电连接到所述至少一个高导电区。
7.根据权利要求1所述的功率半导体设备,其进一步包括置于所述栅电极上的氧化物盖。
8.一种制造功率半导体设备的方法,包括:
在半导体主体中形成栅极沟槽,所述栅极沟槽具有多个侧壁以及一个底部;
在所述栅极沟槽的底部沉积氧化体;
在所述氧化体上形成栅电极;
形成场释放沟槽,所述场释放沟槽具有场氧化体,所述场释放沟槽形成于所述半导体主体内;
形成所述场氧化体之后在所述场氧化体内形成凹部;以及
将置于所述凹部内的场电极电连接到功率电极。
9.根据权利要求8所述的方法,其进一步包括在形成所述栅电极之前在所述侧壁上生成栅极氧化物。
10.根据权利要求8所述的方法,其进一步包括在所述场氧化体上的所述场释放沟槽的各个侧壁上形成隔片,所述隔片互相间隔,并且去除所述场氧化体的局部以在其中形成所述凹部。
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US60/623,679 | 2004-10-29 | ||
US11/261,896 US7371641B2 (en) | 2004-10-29 | 2005-10-28 | Method of making a trench MOSFET with deposited oxide |
US11/261,896 | 2005-10-28 | ||
PCT/US2005/039132 WO2006050192A2 (en) | 2004-10-29 | 2005-10-31 | Trench mosfet with deposited oxide |
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US20060091456A1 (en) | 2006-05-04 |
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US8106446B2 (en) | 2012-01-31 |
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