CN101150105A - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
CN101150105A
CN101150105A CNA2007101529120A CN200710152912A CN101150105A CN 101150105 A CN101150105 A CN 101150105A CN A2007101529120 A CNA2007101529120 A CN A2007101529120A CN 200710152912 A CN200710152912 A CN 200710152912A CN 101150105 A CN101150105 A CN 101150105A
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China
Prior art keywords
filament
semiconductor chip
electrode
conductor portion
semiconductor device
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CNA2007101529120A
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田边学
藤本博昭
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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Publication of CN101150105A publication Critical patent/CN101150105A/zh
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Abstract

在本发明的半导体器件中，将在半导体芯片2的一个主面上形成的多个电极3与配置在前述半导体芯片2的周围的导体部的内部端子4连接、并互相上下配置的丝5a、5b、5c内，对于最下面位置的丝5a采用刚性最小的丝，对于上面位置的丝5b、5c采用刚性更大的丝。通过这样，能够消除金属细丝彼此之间的接触，提高合格率。

Description

半导体器件及其制造方法
技术领域
本发明涉及使用多引脚的半导体芯片的封装型的半导体器件及其制造方法。
背景技术
近年来，移动通信设备等电子设备正向着小型化、高性能、多功能化发展，为了与之相对应，半导体器件存在小型化、高密度化、多引脚化的倾向。例如，正多采用将外部端子配置在底面呈平面阵列状的封装型的半导体器件。被封装的半导体芯片的电极，不仅配置在芯片外周部(外周边缘部)呈一排，而且还交错配置等那样配置成多排。
图7(a)(b)所示为作为这样的半导体器件的一个例子的BGA(Ball GridArray，球栅阵列)封装。在BGA用基板1(以下简称为基板1)上粘结了多引脚的半导体芯片2，半导体芯片2的电极3与基板1上形成的内部电极4利用焊丝5(以下简称为丝5)进行电连接，利用封装树脂6通过传递模铸法等，覆盖半导体芯片2及丝5。图7(b)中仅图示了丝5的一部分，省略了封装树脂6的图示。
在半导体芯片2中，在其一个主面的外周边缘部，配置多排电极3。在基板1上，在半导体芯片2的周围那样形成多排内部电极4，与各内部电极4通过通孔等导通的外部电极7形成为格子状等，在各外部电极7上形成焊锡球8。
在这样的BGA封装中，为了与多引脚的半导体芯片2相对应，将丝5呈三维配置。如图所示，与半导体芯片2上的最外周一排的电极3a连接的丝5a与基板1上的最内周一排的内部电极4a连接，与位于电极3a的内周侧的电极3b、3c连接的丝5b、5c与位于内部电极4a的外周侧的内部电极4b、4c连接。控制各丝5a、5b、5c，使得丝5a的最上部的位置处于比丝5b要低的位置，另外使得丝5b的最上部的位置处于比丝5c要低的位置(例如特表2005-532672号公报)。
但是，在这样三维配置丝5(5a、5b、5c)的情况下，由于丝5使用金(Au)，因此难以控制环形，有时丝5彼此之间接触，成为合格率降低的原因。金也是非常高价的材料。
发明内容
本发明鉴于上述问题，其目的在于不使采用多引脚的半导体芯片的半导体器件的焊丝彼此之间接触，提高合格率。
为了达到上述目的，本发明的半导体器件，利用金属细丝电连接形成在半导体芯片的一个主面上的多个电极与配置在前述半导体芯片的周围的多个导体部的内部端子，前述半导体芯片及金属细丝被树脂封装，在前述半导体器件中，在将前述半导体芯片的电极与前述导体部的内部端子连接，并且互相上下配置的多个金属细丝中，最下面的金属细丝的刚性最小。
根据上述结构，由于最下面位置的金属细丝的刚性最小，因此能够降低丝的高度。由于比它上面位置的金属细丝的刚性更大，因此不仅焊接时容易控制环形形状，而且能够抑制焊接后的环形的变形，还能够抑制树脂封装时由于树脂流动而产生的压力所导致的变形，因此能够维持所希望的高度及形状。因而，能够避免金属细丝彼此之间接触，合格率提高。
例如，可以是半导体芯片具有：配置在一个主面的外周部呈排列状的第1电极、以及配置在比前述第1电极靠近前述一个主面的中心呈排列状的至少一排的第2电极，前述半导体芯片的第1电极与导体部的内部端子，利用第1金属细丝连接，前述半导体芯片的第2电极与前述导体部的内部端子，利用刚性大于前述第1金属细丝的第2金属细丝连接。
另外，可以是将多个半导体芯片层叠，最下层的半导体芯片的电极与导体部的内部端子，利用第1金属细丝连接，第2层以上的上层的半导体芯片的电极与前述导体部的内部端子，利用刚性大于前述第1金属细丝的第2金属细丝连接。
再有，可以是将多个半导体芯片层叠，最下层的半导体芯片的电极与导体部的内部端子，利用第1金属细丝连接，第2层以上的上层的半导体芯片的电极与前述导体部的内部端子、以及多个半导体芯片的电极的一部分彼此之间，利用刚性大于前述第1金属细丝的第2金属细丝连接。
最下面位置的金属细丝的最上部的位置，低于其它的金属细丝的最上部的位置。可以是在用最下面位置的金属细丝连接的半导体芯片的电极的下方，形成电路元件。
本发明的半导体器件的制造方法，具有以下工序：将在一个主面上形成多个电极的半导体芯片安装在支持体上的第1工序；将安装在前述支持体上的半导体芯片的多个电极与配置在该半导体芯片的周围的多个导体部的内部端子，利用金属细丝连接的第2工序；以及将前述半导体芯片与前述金属细丝进行树脂封装的第3工序，在前述半导体器件的制造方法中，在前述第2工序中，在互相上下配置的多个金属细丝内，配置在最下面位置的金属细丝使用刚性最小的金属细丝进行连接，然后使用刚性更大的金属细丝进行连接。
例如，可以进行以下工序：将具有配置在一个主面的外周部呈排列状的第1电极、以及配置在比前述第1电极靠近前述一个主面的中心呈排列状的至少一排的第2电极的半导体芯片安装在支持体上的第1工序；将前述半导体芯片的第1电极与该半导体芯片的周围的多个导体部的内部端子利用第1金属细丝连接，然后将前述半导体芯片的第2电极与多个导体部的内部端子利用刚性大于前述第1金属细丝的第2金属细丝连接的第2工序；以及将前述半导体芯片与前述第1及第2金属细丝进行树脂封装的第3工序。
另外，可以进行以下工序：将多个在一个主面的外周部具有多个电极的半导体芯片层叠安装在支持体上的第1工序；将最下层的半导体芯片的电极与该半导体芯片的周围的多个导体部的内部端子利用第1金属细丝连接，然后将第2层以上的上层的半导体芯片的电极与多个导体部的内部端子利用刚性大于前述第1金属细丝的第2金属细丝连接的第2工序；以及将前述多个半导体芯片与前述第1及第2金属细丝进行树脂封装的第3工序。
再有，可以进行以下工序：将多个在一个主面的外周部具有多个电极的半导体芯片层叠安装在支持体上的第1工序；将最下层的半导体芯片的电极与该半导体芯片的周围的多个导体部的内部端子利用第1金属细丝连接，然后将第2层以上的上层的半导体芯片的电极与多个导体部的内部端子及多个半导体芯片的电极的一部分彼此之间利用刚性大于前述第1金属细丝的第2金属细丝连接的第2工序；以及将前述多个半导体芯片与前述第1及第2金属细丝进行树脂封装的第3工序。
最下面位置的金属细丝与其它的金属细丝的刚性的不同，可以是基于各金属材料的组成来实现的。可以是最下面位置的金属细丝以金为主要成分，其它的金属细丝以铜为主要成分。另外，可以是最下面位置的金属细丝及其它金属细丝以金为主要成分，而前述最下面位置的金属细丝的含金率大于其它金属细丝的含金率。
可以是多个导体部形成在装载有半导体芯片的支持体上。具有这样的多个导体部的支持体例如是布线基板。可以是多个导体部排列在装载有半导体芯片的支持体的周围。具有这样的多个导体部及支持体的构成例如是引线框。
附图说明
图1为说明本发明的一个实施形态的半导体器件的制造方法的工序剖视图。
图2为说明本发明的其它实施形态的半导体器件的制造方法的工序剖视图。
图3为本发明的另外其它的实施形态的半导体器件的剖视图。
图4为本发明的另外其它的实施形态的半导体器件的剖视图。
图5为本发明的另外其它的实施形态的半导体器件的剖视图。
图6为本发明的另外其它的实施形态的半导体器件的剖视图。
图7为以往的半导体器件的剖视图。
具体实施方式
以下，参照附图说明本发明的实施形态。
图1所示为制造本发明的一个实施形态的半导体器件即BGA封装的工序。对于与前面用图7说明的以往的半导体器件相同的构件，附加与图7相同的标号进行说明。
首先，准备图1(a)所示的BGA用基板1(以下简称为基板1)。基板1是将玻璃环氧(或BT树脂或聚酰亚胺等)作为基材的厚度为0.05mm～1mm左右的基板，形成布线图形及通孔等导体部(用虚拟线表示举例)，在芯片安装面及其背面形成通过该导体部电连接的内部电极4、以及与外部的安装基板等连接用的外部电极7。内部电极4及外部电极7的周围的基板面，用阻焊剂等绝缘层(未图示)覆盖。
内部电极4在芯片安装面的中间，设定的芯片安装区域的周围，沿该区域的外周的方向隔开间隔排列，同时沿着从芯片安装面的中心向外周的方向，隔开间隔排列多排(也参照图7)。将各排的内部电极4从最内周一排开始依次用4a、4b、4c表示。
内部电极4之所以这样形成多排，是因为即使用尽可能的最小间距配置，用单排也不能应对半导体芯片的全部引脚数。这样的内部电极4，通常以50μm～500μm左右的间距，使用Cu等为主要材料，形成5～35μm，在表面施加厚度为0。01～5μm的镀Au等。外部电极7采用与内部电极4相同的材料，以能够与内部电极4相对应的数量及配置形成。
接着，如图1(b)所示，在基板1上粘结半导体芯片2。为了进行粘结，使环氧、聚酰亚胺等热固化性树脂(未图示)介于基板1与半导体芯片2之间。
半导体芯片2的电极3在一个主面的外周边缘部、沿该一个主面的外周的方向隔开间隔排列，同时沿着从该一个主面的中心向外周的方向隔开间隔排列多排。将各排的电极3从最外周一排开始依次用3a、3b、3c表示。
这样，电极3之所以这样形成多排，是因为在增多半导体芯片2的电极数(根据电路规模等，为10～2000引脚左右)的情况下，即使用尽可能的最小间距配置，用单排也不能配置必需数量的电极。这样的电极3通常用Al、Au、Cu等形成，在以Al为主要材料的情况下，添加微量的Si、Cu等。电极3采用交错配置、并排配置等。在半导体芯片2上，在最外周一排的电极3a的下方也形成晶体管等半导体元件及布线等电路元件9。
接着，如图1(c)所示，采用丝焊法通过丝5a，电连接半导体芯片1的最外周一排的电极3a与基板1的最内周一排的内部电极4a。接着，如图1(d)所示，通过丝5b，电连接半导体芯片1的中间一排的电极3b与基板1的中间一排的内部电极4b。然后，通过丝5c，电连接半导体芯片1的最内周一排的电极3c与基板1的最外周一排的内部电极4c。图1(c)(d)所示的这些丝焊工序，通常是加热或施加超声波、并加压进行的。加热温度是50～300℃左右，超声波的输出是10～300mW左右，加压是10～100g重左右。
这时重要的是，对于与半导体芯片2的最外周一排的电极3a连接的丝5a(称为第1丝5a)、以及与其内侧一排的电极3b、3c连接的丝5b、5c(称为第2丝5b、5c)，是采用刚性不同的丝。这样进行选定，使得第2丝5b、5c的刚性比第1丝5a的刚性更大。
在丝焊结束后，如图1(e)所示，在基板1的单侧，利用传递模铸法等形成封装树脂6，使得覆盖半导体芯片2及第1丝5a和第2丝5b、5c，然后对基板1的外部电极7形成焊锡球8。通过这样，完成BGA封装。
在以上的BGA封装中，之所以如上所述对于第2丝5b、5c使用比第1丝5a的刚性要大的丝，是因为在将配置成多排的电极3a、3b、3c与内部电极4a、4b、4c连接时，在俯视图中来看，丝5a、5b、5c彼此之间至少一部分容易重叠配置，即丝5a、5b、5c彼此之间至少一部分容易互相位于上下位置那样配置，难以避免这种情况。
另外，是由于与半导体芯片2的靠近中心的电极3b、3c连接的第2丝5b、5c，在与电极3b、3c的接合部对半导体芯片2沿垂直方向引出，需要形成环形，丝高度增高，丝长度也伸长。
由于对于这样的第2丝5b、5c通过使用刚性较大的丝，不仅容易控制焊接时形成的环形形状，而且焊接后难以引起环形的变形挠曲(歪斜)等，另外也能够抑制树脂封装时由于树脂流动而产生的压力所导致的变形，所以能够维持所希望的高度及形状。另一方面，由于对于与半导体芯片2的最外周一排的电极3a连接、配置在最下面位置的第1丝5a通过使用刚性最小的丝，能够降低丝高度，因此能够加大与配置在上面位置的第2丝5b、5c的距离。
通过这些措施，难以引起产生第1丝5a、第2丝5b、5c接触等不良的情况，合格率高。通过抑制第2丝5b、5c的丝高度，达到与第1丝5a不接触的程度，从而还能够使整个器件实现薄型化。
再有，由于利用刚性小的第1丝5a在焊接时对电极3a所加的负载小，因此即使如上所述在电极3a的下方配置电路元件9，也不会导致损坏。换句话说，由于第1丝5a使用刚性小的丝，因此在半导体芯片2的外周部也能够形成电路元件9。通过这样，通过减小半导体芯片2的尺寸，能够降低成本。
为此，设配置在最下面位置的第1丝5a为Au线，设配置在比第1丝5a要高的位置的第2丝5b、5c为Cu线，采用这样材料不同的丝。或者，第1丝5a采用含金率高(99.99质量％以上)的Au线，第2丝5b、5c采用含金率低(99.90～99.00质量％左右)的Au线，采用这样含有量不同的材料。通过采用Cu或纯度低的Au，则也降低高价材料的Au的使用量，也有助于降低成本。
即使第1丝5a与第2丝5b、5c的组成相同，但通过使直径不同，也可以使刚性不同。由于丝径通常为12～30μm左右，因此可以选择适当的直径。另外，配置在最下面位置的第1丝5a也可以包含在俯视图来看与第2丝5b、5c不重叠的丝。
焊接的顺序如上所述，在利用半导体芯片2的最外周一排的电极3a的第1丝5a进行连接结束后，利用内侧的电极3b、3c的第2丝5b、5c进行连接。为此，例如将第1丝5a用的丝焊器与第2丝5b、5c用的丝焊器形成为分别独立的装置，则效率高。
以上，是将第1丝5a与第2丝5b、5c的两组作为使刚性不同的情况进行说明的，但也可以这样选定，使得越配置在上面位置的丝的刚性越大，即成为丝5a的刚性＜丝5b的刚性＜丝5c的刚性。
图2所示为制造本发明的其它实施形态的半导体器件即BGA封装的工序。
如图2(a)所示，准备与上述相同的基板1。然后，在基板1上粘结在外周边缘部形成电极3A的第1半导体芯片20，在其上，如图2(b)所示，层叠粘结在外周边缘部形成电极3B的第2半导体芯片21、以及在外周边缘部形成电极3C的第3半导体芯片22。为了进行粘结，使用热固化性树脂。电极3A、3B、3C的结构及数量与上述的电极3a、3b、3c相同。在第1半导体芯片20的电极3A的下方，形成晶体管等半导体元件及布线层等电路元件9。
接着，如图2(c)所示，将第1半导体芯片20的电极3A与基板1的最内周一排的内部电极4a采用丝焊法通过丝5a进行电连接。接着，如图2(d)所示，将第2半导体芯片21的电极3B与基板1的中间一排的内部电极4b通过丝5b进行电连接。然后，将第3半导体芯片22的电极3C与基板1的最外周一排的内部电极4c通过丝5c进行电连接。图2(c)(d)所示的这些丝焊工序，与上述相同，加热或施加超声波、并加压进行的。
这时重要的是，对于与第1半导体芯片20的电极3A连接的丝5a(以下称为第1丝5a)、以及与第2、第3半导体芯片21、22的电极3B、3C连接的丝5b、5c(以下称为第2丝5b、5c)，是采用刚性不同的丝。这样进行选定，使得第2丝5b、5c的刚性比第1丝5a的刚性更大。
在丝焊结束后，如图2(e)所示，在基板1的单侧，利用传递模铸法等形成封装树脂6，使得覆盖半导体芯片20、21、22及丝5a、5b、5c，然后对基板1的外部电极7形成焊锡球8。通过这样，完成BGA封装。
在以上的BGA封装中也同样，在将层叠成多层的半导体芯片20、21、22的电极3A、3B、3C、与内部电极4a、4b、4c进行连接时，在俯视图中来看，丝5a、5b、5c彼此之间至少一部分容易互相位于上下位置那样配置，难以避免这种情况。为此，对于与上层的半导体芯片21、22上存在的、位于靠近器件中心的电极3B、3C连接的第2丝5b、5c，使用硬度大于第1丝5a的丝，通过这样，能够得到与关于图1所示的BGA封装说明的情况同样的效果。
即，对于第2丝5b、5c，不仅容易控制焊接时形成的环形形状，而且焊接后难以引起环形的变形挠曲(歪斜)等，另外也能够抑制树脂封装时由于树脂流动而产生的压力所导致的变形，所以能够维持所希望的高度及形状。对于配置在最下面位置的第1丝5a，由于能够降低丝高度，因此能够加大与配置在上面位置的第2丝5b、5c的距离。通过这些措施，难以引起产生第1丝5a、第2丝5b、5c接触等不良的情况，合格率高。通过抑制第2丝5b、5c的丝高度，达到与第1丝5a不接触的程度，从而还能够使整个器件实现薄型化。
另外，由于利用刚性小的第1丝5a在焊接时对电极3A所加的负载小，因此即使在电极3A的下方配置电路元件9，也不会导致损坏，能够确保可靠性。换句话说，由于第1丝5a使用刚性小的丝，因此在半导体芯片2的外周部也能够形成电路元件9。通过这样，通过减小半导体芯片2的尺寸，能够降低成本。
第1丝5a及第2丝5b、5c可以使用与关于图1所示的BGA封装说明的相同的材料。若使用Cu或纯度低的Au，则能够减少高价材料的Au的使用量，也能够力图实现低成本化。也可以这样选定，即成为丝5a的刚性＜丝5b的刚性＜丝5c的刚性。焊接的顺序及装置也可以与关于图1所示的BGA封装说明的相同。
另外，图中所示为是将最下层的半导体芯片20作为最大的尺寸，但对于半导体芯片的层叠位置及尺寸没有限制。例如，最下层的半导体芯片20在不进行丝焊时，也可以小于其它的半导体芯片21、22的尺寸。
说明的层叠的半导体芯片数是假设3个，但若是2个以上，则能够采用上述的结构，能够得到同样的效果。图3所示为层叠了2个半导体芯片20、21的BGA封装。
图4所示为本发明的另外其它实施形态的半导体器件即BGA封装的结构。在该BGA封装中，在基板1上层叠粘结了第1半导体芯片23、第2半导体芯片24。关于与图2的BGA封装的相同点，则省略说明。
第1半导体芯片23的多个电极3在一个主面的外周边缘部、沿该一个主面的外周的方向隔开间隔排列，同时沿着从该一个主面的中心向外周的方向隔开间隔排列多排。从外周一侧开始依次用3A1、3A2表示。第2半导体芯片24的多个电极3如同样，在一个主面的外周边缘部排列多排。从外周一侧开始依次用3B1、3B2表示。
将第1半导体芯片23的外周一排的电极3A1与基板1的内周一排的内部电极4a采用丝焊法通过丝5a进行电连接。将第1半导体芯片23的内周一排的电极3A2与第2半导体芯片24的外周一排的电极3B1，通过丝5b进行连接。由于将第1半导体芯片23与第2半导体芯片24进行电连接，因此其目的是不通过基板1，以节省空间进行连接。第2半导体芯片24的内周一排的电极3B2与基板1的外周一排的内部电极4b，采用与丝5b同一种类的丝5c进行连接。
对于丝5b、5c(以下称为第2丝5b、5c)，选定刚性比丝5a(以下称为第1丝5a)更大的丝。用第1丝5a进行第1半导体芯片23的电极3A1与内部电极4a的连接，然后用第2丝5b进行电极3A2与3B1的连接，然后用第2丝5c进行电极3B2与内部电极4b的连接。
在该BGA封装中，也由于对于与上层的半导体芯片24上存在的、位于靠近器件中心的电极3B2、3B1连接的第2丝5b、5c，使用硬度大于与下层的半导体芯片23的电极3A1连接的第1丝5a的丝，即由于对于配置在上面位置的第2丝5b、5c，采用刚性比配置在最下面位置的第1丝5a更大的丝，因此能够得到与关于图1、图2所示的BGA封装说明的情况同样的效果。
能够使用的第1丝5a及第2丝5b、5c与关于图1所示的BGA封装说明的相同。但是，由于第2丝5b没有与第1丝5a重叠的可能，因此刚性也可以不一定大于第1丝5a，也可以采用与第1丝5a相同的材料。当然，也可以这样选定，即成为丝5a的刚性＜丝5b的刚性＜丝5c的刚性。
另外，图中所示为是将下层的半导体芯片23作为较大的尺寸，但对于半导体芯片的层叠位置及尺寸没有限制。例如，下层的半导体芯片23在不进行丝焊时，也可以小于半导体芯片24的尺寸。
说明的层叠的半导体芯片数是假设2个，但若是2个以上，则能够采用上述的结构，能够得到同样的效果。
图5所示为本发明的另外其它实施形态的半导体器件即BGA封装的结构。在该BGA封装中，在基板1上层叠安装了第1半导体芯片25、第2半导体芯片26。
第1半导体芯片25在一个主面上呈格子状形成电极3D，在各电极3D上形成焊锡球10，焊锡球10与基板1的芯片安装区域上形成的内部电极4d进行接合。
第2半导体芯片26粘结在第1半导体芯片25上。第2半导体芯片26的多个电极3在一个主面的外周边缘部、沿该一个主面的外周的方向隔开间隔排列，同时沿着从该一个主面的中心向外周的方向隔开间隔排列多排。从外周一侧开始依次用3a、3b表示。
将第2半导体芯片26的外周一排的电极3a与基板1的内周一排的内部电极4a，采用丝焊法通过丝5a进行电连接。将第2半导体芯片26的内周一排的电极3b与基板1的外周一排的内部电极4b，通过丝5b进行连接。对于丝5b(以下称为第2丝5b)，选定刚性比丝5a(以下称为第1丝5a)更大的丝。
在该BGA封装中，也由于对于与第2半导体芯片26的最外周一排的电极3a连接的、配置在最下面位置的第1丝5a采用刚性最小的丝，对于配置在上面位置的第2丝5b采用刚性更大的丝，因此能够得到与关于图1所示的BGA封装说明的情况同样的效果。
能够使用的第1丝5a及第2丝5b、和焊接的顺序，与关于图1所示的BGA封装说明的相同。
另外，图中所示为是将下层的半导体芯片25作为较大的尺寸，但对于半导体芯片的层叠位置及尺寸没有限制。例如，下层的半导体芯片25也可以小于半导体芯片26。
说明的层叠的半导体芯片数是假设2个，但若是2个以上，则能够采用上述的结构，能够得到同样的效果。
以上，是使用基板1作为以单体制造BGA封装进行说明的，但不用说也可以使用设置多个安装区域的薄长方形等基板，在多个BGA封装相连接的状态下进行制造，然后形成单片。对于QFP型或其它形态的封装，也可以适用上述的各结构，能够得到同样的效果。
图6所示为QFP型封装。关于与图2的BGA封装相同的构件，附加相同标号，并省略说明。11是作为半导体芯片20、21的支持体的裸芯片底座，12是在裸芯片底座的周围排列多条的引线。裸芯片底座11与引线12由于在制造阶段使用的引线框中连接，因此可作为一体使用。
在该QFP型封装中，对于配置在上面位置的第2丝5b，也采用刚性比配置在最下面位置的第1丝5a更大的丝，通过这样，能够得到与关于图1、图2所示的BGA封装说明的情况同样的效果。
如上所述，本发明的半导体器件，由于将半导体芯片上的多个电极与配置在前述半导体芯片的周围的多个导体部的内部端子连接，并互相上下配置的多个金属细丝内，对于最下面位置的金属细丝采用刚性最小的丝，对于在它上面位置的金属细丝采用刚性更大的丝，因此能够防止金属细丝彼此之间的接触，力图提高合格率。作为刚性更大的金属细丝，若使用Cu或纯度低的Au，则与以往相比，还能够减少Au的使用量，力图实现低成本化。本发明对于移动通信设备等电子设备中安装的小型、多引脚的半导体器件的制造，特别有用。

Claims (20)

1.一种半导体器件，利用金属细丝，电连接形成在半导体芯片的一个主面上的多个电极与配置在所述半导体芯片的周围的多个导体部的内部端子，所述半导体芯片及金属细丝被树脂封装，其特征在于，
在将所述半导体芯片的电极与所述导体部的内部端子连接、并且互相上下配置的多个金属细丝中，最下面的金属细丝的刚性最小。
2.如权利要求1所述的半导体器件，其特征在于，
半导体芯片具有：配置在一个主面的外周部呈排列状的第1电极、以及配置在比所述第1电极靠近所述一个主面的中心呈排列状的至少一排的第2电极，
所述半导体芯片的第1电极与导体部的内部端子，利用第1金属细丝连接，
所述半导体芯片的第2电极与所述导体部的内部端子，利用刚性大于所述第1金属细丝的第2金属细丝连接。
3.如权利要求1所述的半导体器件，其特征在于，
将多个半导体芯片层叠，
最下层的半导体芯片的电极与导体部的内部端子，利用第1金属细丝连接，
第2层以上的上层的半导体芯片的电极与所述导体部的内部端子，利用刚性大于所述第1金属细丝的第2金属细丝连接。
4.如权利要求1所述的半导体器件，其特征在于，
将多个半导体芯片层叠，
最下层的半导体芯片的电极与导体部的内部端子，利用第1金属细丝连接，
第2层以上的上层的半导体芯片的电极与所述导体部的内部端子、以及多个半导体芯片的电极的一部分彼此之间，利用刚性大于所述第1金属细丝的第2金属细丝连接。
5.如权利要求1所述的半导体器件，其特征在于，
最下面位置的金属细丝与其它的金属细丝的刚性的不同，是基于各金属材料的组成来实现的。
6.如权利要求5所述的半导体器件，其特征在于，
最下面位置的金属细丝以金为主要成分，其它的金属细丝以铜为主要成分。
7.如权利要求5所述的半导体器件，其特征在于，
最下面位置的金属细丝及其它金属细丝以金为主要成分，而所述最下面位置的金属细丝的含金率大于其它金属细丝的含金率。
8.如权利要求1所述的半导体器件，其特征在于，
最下面位置的金属细丝的最上部的位置，低于其它的金属细丝的最上部的位置。
9.如权利要求1所述的半导体器件，其特征在于，
在用最下面位置的金属细丝连接的半导体芯片的电极的下方，形成电路元件。
10.如权利要求1所述的半导体器件，其特征在于，
多个导体部形成在装载有半导体芯片的支持体上。
11.如权利要求1所述的半导体器件，其特征在于，
多个导体部排列在装载有半导体芯片的支持体的周围。
12.一种半导体器件的制造方法，具有以下工序：
将在一个主面上形成多个电极的半导体芯片安装在支持体上的第1工序；
将安装在所述支持体上的半导体芯片的多个电极与配置在该半导体芯片的周围的多个导体部的内部端子，利用金属细丝连接的第2工序；以及
将所述半导体芯片与所述金属细丝进行树脂封装的第3工序，其特征在于，
在所述第2工序中，在互相上下配置的多个金属细丝内，配置在最下面位置的金属细丝使用刚性最小的金属细丝进行连接，然后使用刚性更大的金属细丝进行连接。
13.如权利要求12所述的半导体器件的制造方法，其特征在于，进行以下工序：
将具有配置在一个主面的外周部呈排列状的第1电极、以及配置在比所述第1电极靠近所述一个主面的中心呈排列状的至少一排的第2电极的半导体芯片安装在支持体上的第1工序；
将所述半导体芯片的第1电极与该半导体芯片的周围的多个导体部的内部端子利用第1金属细丝连接，然后将所述半导体芯片的第2电极与多个导体部的内部端子利用刚性大于所述第1金属细丝的第2金属细丝连接的第2工序；以及
将所述半导体芯片与所述第1及第2金属细丝进行树脂封装的第3工序。
14.如权利要求12所述的半导体器件的制造方法，其特征在于，进行以下工序：
将多个在一个主面的外周部具有多个电极的半导体芯片层叠安装在支持体上的第1工序；
将最下层的半导体芯片的电极与该半导体芯片的周围的多个导体部的内部端子利用第1金属细丝连接，然后将第2层以上的上层的半导体芯片的电极与多个导体部的内部端子利用刚性大于所述第1金属细丝的第2金属细丝连接的第2工序；以及
将所述多个半导体芯片与所述第1及第2金属细丝进行树脂封装的第3工序。
15.如权利要求12所述的半导体器件的制造方法，其特征在于，进行以下工序：
将多个在一个主面的外周部具有多个电极的半导体芯片层叠安装在支持体上的第1工序；
将最下层的半导体芯片的电极与该半导体芯片的周围的多个导体部的内部端子利用第1金属细丝连接，然后将第2层以上的上层的半导体芯片的电极与多个导体部的内部端子及多个半导体芯片的电极的一部分彼此之间利用刚性大于所述第1金属细丝的第2金属细丝连接的第2工序；以及
将所述多个半导体芯片与所述第1及第2金属细丝进行树脂封装的第3工序。
16.如权利要求12所述的半导体器件的制造方法，其特征在于，
最下面位置的金属细丝与其它的金属细丝的刚性的不同，是基于各金属材料的组成来实现的。
17.如权利要求12所述的半导体器件的制造方法，其特征在于，
最下面位置的金属细丝以金为主要成分，其它的金属细丝以铜为主要成分。
18.如权利要求12所述的半导体器件的制造方法，其特征在于，
最下面位置的金属细丝及其它金属细丝以金为主要成分，而所述最下面位置的金属细丝的含金率大于其它金属细丝的含金率。
19.如权利要求12所述的半导体器件的制造方法，其特征在于，
多个导体部形成在装载有半导体芯片的支持体上。
20.如权利要求12所述的半导体器件的制造方法，其特征在于，
多个导体部排列在装载有半导体芯片的支持体的周围。
CNA2007101529120A 2006-09-22 2007-09-21 半导体器件及其制造方法 Pending CN101150105A (zh)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102163557A (zh) * 2010-02-15 2011-08-24 瑞萨电子株式会社 半导体器件的制造方法
CN103188883B (zh) * 2011-12-29 2015-11-25 无锡华润安盛科技有限公司 一种金属框架电路板的焊接工艺

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102163557A (zh) * 2010-02-15 2011-08-24 瑞萨电子株式会社 半导体器件的制造方法
CN102163557B (zh) * 2010-02-15 2016-02-10 瑞萨电子株式会社 半导体器件的制造方法
CN103188883B (zh) * 2011-12-29 2015-11-25 无锡华润安盛科技有限公司 一种金属框架电路板的焊接工艺

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