CN101142675A - 具有改善的接合焊盘连接的集成电路封装器件、引线框和电子装置 - Google Patents
具有改善的接合焊盘连接的集成电路封装器件、引线框和电子装置 Download PDFInfo
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Abstract
一种具有实质上矩形形状的半导体器件封装(10),包括:管芯附着焊盘(12),具有顶部表面(14)和底部表面(16);多个接触焊盘(261-26n),设置在与封装的矩形形状相对应的至少四行中,每一个接触焊盘具有顶部表面和顶部表面;至少两个连接杆(18),用于支撑管芯附着焊盘直到在封装制造期间切分封装为止,所述连接杆具有顶部表面和底部表面,并从管芯附着焊盘向封装的角落延伸;半导体管芯(20),安装在管芯附着焊盘(12)顶部表面上、并具有在其上形成有接合焊盘(44);多个电连接(22、24),在选定的一些接合焊盘(44)和相应的一些接触焊盘(261-26n)之间;封装物(28),包裹半导体管芯(20)、管芯附着焊盘(12)的顶部表面、电连接、连接杆(18)的顶部表面和接触焊盘(261-26n)的顶部表面,并且留下管芯附着焊盘的底部表面(16)和接触焊盘的底部表面暴露在外;其特征在于:将至少一个具有顶部表面和底部表面的长条(30)设置在管芯附着焊盘(12)和相应行的接触焊盘之间,所述长条(30)具有与所述行中的至少一个接触焊盘相连接的至少一个侧向部分(36),在长条和半导体管芯(20)上与长条相邻的选定焊盘(44)之间提供电连接。
Description
技术领域
本发明涉及根据权利要求1前序部分的集成电路封装器件。
本发明还涉及用于制造集成电路器件封装的引线框。
另外,本发明涉及包括诸如其上连接了半导体器件封装的印刷电路板之类的电子载体的电子装置。
背景技术
例如从US6,229,200已知如第一段所述的封装,其中公开了从引线框矩阵形成的并具有灵活结构的无引线塑料芯片载体。采用了集成了多个接触焊盘(contact pad)和管芯附着焊盘的引线框矩阵以便允许大规模生产。
现有技术封装的问题是它们相对较大的整体尺寸。存在着对更小封装的不断增长的需求,因为它们生产更便宜并且能够在电子装置预设定体积内提供更多功能。
发明内容
本发明的目的是提供根据权利要求1前序部分的集成电路器件封装,具有更小的尺寸并从而和现有技术封装相比提供更便宜的封装。
根据本发明,通过如权利要求1特征部分所述的技术方法来达到该目的。
在管芯附着焊盘和一行接触焊盘行之间放置至少一个长条允许将要求低欧姆连接的接合焊盘和长条相连接,从而将接合焊盘设置在半导体管芯上的不同位置,所述连接只经由长条的侧向部分直接与一个接触焊盘相连接。这减少了所要求的接触焊盘数目并从而减少了封装尺寸和成本。封装尺寸主要由封装中各行的接触焊盘中的接触焊盘数量(有时也称为接触管脚)来决定。
已经发现如果没有长条的话,7×7mm QFN封装中可以接纳56个接触焊盘。通过采用两个长条,看起来48个接触焊盘足以对相同的半导体管芯(即有相同功能的管芯)提供封装。6×6mm QFN封装中可以接纳48个接触焊盘。同样的原理用于具有更多接触焊盘的封装,例如9×9mm封装,或者具有更少的接触焊盘,例如5×5mm封装。
本发明的附加优点是与外部世界改善的连接。位于在半导体管芯上不同位置处的多个接触焊盘要求与外部世界中的相应电子信号(具有类似的电位)的低欧姆连接。例如涉及供电信号的接合焊盘需要这样的连接,以便获得电池的有效能量使用。对于例如移动电话、数码摄像机、游戏机等等电池操作便携式装置尤其如此。在现有技术中,要求低欧姆连接的接合焊盘经由分布在封装不同位置的不同接触焊盘与外部世界相连接,这要求相对较长的接合导线。根据本发明,减少了与外部世界相连接的电阻和电感,因为由于相比于接合焊盘和接触焊盘之间的距离在管芯上的焊盘和长条之间更短的距离,以及给出每单位长度引线框的电阻比每单位长度接合导线电阻更小的事实,可以应用更短的接合导线。
至少对于封装应用的主要部分,封装尺寸主要由接触焊盘数目和它们之间的相互距离来确定。同样至少对于封装应用的主要部分,封装中管芯的尺寸和相应的管芯附着焊盘与封装的整个尺寸相对通常较小,这样留下足够空间来提供一个或多个如上所述的长条。
在本发明的优选实施例中,在管芯附着焊盘和相应行的接触焊盘之间设置两个长条。这允许将本发明的概念应用于管芯上的两个不同区域,每一个区域设置为与相应的长条相邻。在该实施例中,特别优选地是将两个长条设置为与管芯附着焊盘的相对侧相邻,用于根据本发明制造半导体器件封装的引线框矩阵的对称设计是有利的。
在本发明另一个有利实施例中,将与长条电连接的半导体管芯上的接合焊盘用于供电信号和/或者要求低欧姆连接的信号,例如基准电压信号或地信号。这些类型的接合焊盘从与长条的附近电连接受益最多,因为每单位长度引线框材料的电阻比每单位长度接合导线的电阻更小。
在芯片上的不同位置处典型地要求供电(例如电池电压)、模拟和数字地以及基准电压,并且相应的接合焊盘因此从长条的附近位置受益。
在本发明的另外有利实施例中,长条包括与相应行中的两个接触焊盘相连接的侧向部分。这向长条提供了与连接到相应引线框有关的改善的机械稳定性。因此,该特征主要在封装制造工艺期间直到模塑封装物的步骤是有利的。
根据本发明,有利的是长条的底部表面暴露。暴露的长条意味着在优选的用于建立在长条和接合焊盘之间的电连接的导线接合过程中,长条受到支撑,例如通过附在引线框上的支撑带,这将在下面更详细地解释。如果没有正确地支撑长条,例如当长条区域是半刻蚀的(并因此没有暴露)时就是这样的情况,非常难以建立适当的导线接合。在那样的情况下需要至少采取特殊方式来提供适当的支撑,例如提供具有凸出物的支撑。
根据本发明,电连接包括在接合焊盘和接触焊盘和/或在接合焊盘和长条之间接合的导线也是有利的。导线接合是众所周知的并且是在封装内提供电子连接的可靠方法。
附图说明
接下来将参考附图进一步解释本发明,其中:
图1示出了根据本发明优选实施例的半导体器件封装的底部表面的示意图;
图2示出了沿图1的A-A’线得到的剖面图;
图3示出了根据本发明另一个优选实施例的半导体器件封装的底部表面的示意图。
具体实施方式
首先应该注意的是图1分别示意性地示出了暴露的底部表面(由未加阴影线的区域表示)、填充有封装材料的部分(由底部左边到顶部右边的加阴影线的区域表示)、以及半刻蚀部分(由从顶部左边到底部右边加阴影线的区域表示)。后者的部分当一个人看底部表面时一般是是看不到的(代替地这个人会看见封装材料)。至于图2,应该注意的是在横截面中只示出了封装的左半部分,因为封装关于线A-A’是对称的。
现在参考图1和图2,示出了具有实质上矩形形状的半导体器件封装10。封装包括具有顶部表面14和暴露的底部表面16的管芯附着焊盘12,从管芯附着焊盘12向封装相反的对角延伸的四个连接杆18,以及在管芯附着焊盘和接触焊盘行之间设置的多个接触焊盘261-26n,长条具有至少一个与行中至少一个接触焊盘相连接的侧向部分,在与封装的矩形形状相对应的至少4行中设置提供所述接触焊盘。另外(参见图2),封装10包括安装在管芯附着焊盘顶部表面14上的、并且在其上形成有接合焊盘44的半导体管芯20,在接合焊盘44的选定焊盘和相应的接触焊盘261-26n之间的多个电连接22、24。封装物28包裹半导体管芯20、管芯附着焊盘12的顶部表面14、电连接22、24,连接杆18的顶部表面和接触焊盘的顶部表面,并且留下管芯附着焊盘12的底部表面16和接触焊盘的底部表面暴露在外。
如在图1中最佳示出的,在管芯附着焊盘和相应的接触焊盘行之间设置了两个长条30。每个长条30包括与行中至少一个接触焊盘(在图1中分别是焊盘26n和261)相连接的至少一个侧向部分36。长条允许位于半导体管芯20上与长条相邻的不同位置处的焊盘44(在图1中由虚线方块表示)与所述长条相连接,例如通过导线。经由侧向部分36,把这些连接直接与相应的接触焊盘(在图1中分别是焊盘261和26n)相连。这意味着将半导体管芯20上不同位置处的焊盘44只与一个接触焊盘直接相连,否则该接合焊盘将不得不与相应行中的几个接触焊盘相连。因此,长条允许减少接触焊盘数目,并从而减少封装尺寸和成本。
管芯附着焊盘12、连接杆18、长条30和接触焊盘261-26n都由导电材料制成(参见下面引线框设计的典型设计流程描述)。
在制作任何电连接之前,接触焊盘261-26n互相之间以及与管芯附着焊盘12之间是电隔离的。同样长条30与管芯附着焊盘12之间也是电隔离的。
图1示出了将两个长条30设置为与管芯附着焊盘的相对侧面相邻。然而,根据本发明,也可以只将一个或者三个或四个长条设置为与管芯附着焊盘的任意一侧相邻。
在设置了两个或更多长条的情况下,可以想到将两个或更多长条直接相连,产生L状-或U-状长条。也可以将两个相邻长条互连,例如用导线接合。
图2更详细地示出了电连接22、24。所述电连接包括在半导体管芯20上的接合焊盘44和管芯附着焊盘12之间或者在接合焊盘44和长条30之间分别形成的导线接合。尽管图1和2中未示出,逻辑上在接合焊盘44和常规接触焊盘261-26n之间也存在导线接合。
图2更详细地示出了侧向部分36。可以看出这部分是半刻蚀的,并且存在与相应的接触焊盘的直接连接。然而可以想到是在长条和相应的接触焊盘之间采用导线接合,而不是直接连接。另外,可以经由电子载体或印刷电路板来进行非直接连接。
图2还示出了了包裹的顶部表面32,以及长条30的暴露的底部表面34。暴露的底部表面34在导线接合期间当长条需要例如通过支撑带的支撑时是有利的(注意在导线接合期间还不存在封装材料)。
虽然在图1和2中没有示出,长条可以包括一个或者更多与相应行中的两个接触焊盘相连接的侧向部分。优选地,将这些侧向部分与相应的接触焊盘设置在长条的外端附近,以便改善长条的机械稳定性,这在封装制造期间尤其重要(参见下面引线框设计的典型设计流程描述)。
图3示出了根据本发明另一个优选实施例的半导体器件封装的底部表面的示意图。除了在图1和2中所示的两个附加长条30和其它部件之外,示出了两个附加接触焊盘60(如与具有四个连接杆的常规封装相比较),所述附加接触焊盘60通过用这样的附加接触焊盘代替两个连接杆而形成。在图1中所示的优选实施例中,存在两个连接杆18以在封装制造器件向管芯附着焊盘提供必要的支撑。根据本发明,也可以具有三个附加接触焊盘,从而只留下一个连接杆。替代地,可以用附加接触焊盘仅替换一个连接杆,从而留下最多三个连接杆。
附加接触焊盘60允许减少在各自行中的接触焊盘数目。因为封装尺寸主要由行中提供的接触焊盘数目来决定,附加接触焊盘60允许更小的封装尺寸以及因此更便宜的封装。
通过根据图3的实施例,发现可以使用配置有50个接触焊盘的6×6mm封装,而对于同样的半导体管芯正常地需要配置有56个接触焊盘的7×7mm封装。通过采用设置在通常包括4×12=48个接触焊盘的封装的两个角落的两个附加接触焊盘,可以得到50个数目的接触焊盘。
典型地,根据用于本发明封装的接触焊盘总数在10至100之间,更优选地在30至70之间。虽然描述为只包括一个半导体管芯,根据本发明的封装非常适合应用于所谓芯片上芯片封装,如作为例子的WO-A2004/057668中所述。在这样的芯片上芯片封装中,在一个实施例中,从管芯的接合焊盘到接触焊盘的连接可以由从接合焊盘到第二芯片的第一连接、第二芯片上的互连接以及从芯片到接触焊盘的第二连接组成。在这个实施例中,第二芯片具有比管芯焊盘上的半导体焊盘大的表面面积。第二芯片可以是集成电路、图像传感器,但是也可以是无源芯片,例如无源部件的网络,或者包括在选定的一些接合焊盘和相应的一些接触焊盘之间的多个独立电路部分的***芯片,例如ESD保护。包括比一个或几个半导体管芯更多部件的封装(***级封装)也会受益于本发明。这些器件可以存在于相同的管芯焊盘或独立的管芯焊盘上。长条允许供电或者与专用部件附近良好定义的基准电势的供应。由于专用部件可能具有不同要求,这表现出优势。另外,可以将长条用作专用部件的管芯焊盘,例如无源器件或滤波器。然后可以在半导体管芯和部件之间形成导线接合。另外,可以将长条用于向多于一个的部件提供电势或电压供应,或者作为两个部件之间的专用互连焊盘。
根据本发明的封装可能的应用是如用于电源管理半导体的封装,或者更一般地说,产生相对较多热量的半导体。
典型地,本发明适用于所谓QFN(四方扁平无引线)封装。有时这些封装被称为HVQFN、MLF、LPCC、DQFN或MCP封装。然而,也可以想到将本发明应用于所谓QFP封装。在那样的情况下附加接触焊盘会是从封装角落延伸的附加引线。
虽然未说明,根据本发明实施例的引线框设计的典型设计流程总结如下。首先,提供合适尺度的金属带,典型地为铜带。然后将适当构图的第一掩模用于刻蚀所述带的上下表面,从而提供引线框的基本定义,所述引线框包括连接杆、管芯附着焊盘以及根据本发明的长条。然后可以将适当构图的第二掩模用于半刻蚀铜带的下表面。然后可以对适当构图的带镀覆合适的例如镍钯NiPd保护层。然后将已构图的带(即引线框)附加到支撑带上。已经定义和准备好引线框之后,现在可以生产半导体器件封装,其中:将半导体管芯附加到管芯附着焊盘上;制作合适的导线接合;将封装物适当地模塑在引线框和半导体管芯周围;最后通过精确地锯割或者在引线框上冲孔来从长条切分(singulate)最终的多个已封装导体器件。
应该注意的是,上述实施例说明而非限制本发明,本领域的普通技术人员在不脱离如所附权利要求所限定的情况下,能够设计许多替代实施例。在权利要求中,括号中放置的任意参考符号不应该被解释为限制权利要求。动词“包括”及其同义词不应该排除除了在权利要求和说明书整体所列的元件和步骤的存在。单数提及的元件不排除多个这种元件,反之亦然。在该申请中使用的术语“半刻蚀”一般指的是其中将厚度的大约40%至85%去除的刻蚀处理,优选地在45%至55%之间。
Claims (9)
1.一种具有实质上矩形形状的半导体器件封装(10),包括:
管芯附着焊盘(12),具有顶部表面(14)和底部表面(16);
多个接触焊盘(261-26n),设置在与封装的矩形形状相对应的至少四行中,每一个接触焊盘具有顶部表面和顶部表面;
至少两个连接杆(18),用于支撑管芯附着焊盘直到在封装制造期间切分封装为止,所述连接杆具有顶部表面和底部表面,并从管芯附着焊盘向封装的角落延伸;
半导体管芯(20),安装在管芯附着焊盘(12)顶部表面(14)上、并在其上形成有接合焊盘(44);
多个电连接(22、24),在选定的一些接合焊盘(44)和相应的一些接触焊盘(261-26n)之间;
封装物(28),包裹半导体管芯(20)、管芯附着焊盘(12)的顶部表面(14)、电连接(22、24)、连接杆(18)的顶部表面和接触焊盘(261-26n)的顶部表面,并且留下管芯附着焊盘的底部表面(16)和接触焊盘的底部表面暴露在外;其特征在于:
将至少一个具有顶部表面(32)和底部表面(34)的长条(30)设置在管芯附着焊盘(12)和相应行的接触焊盘之间,所述长条具有与所述行中的至少一个接触焊盘相连接的至少一个侧向部分(36),在长条和半导体管芯(20)上与长条相邻的选定焊盘(44)之间提供电连接。
2.如权利要求1所述的半导体器件封装(10),其特征在于:将两个长条(30)设置在管芯附着焊盘(12)和相应行的接触焊盘之间。
3.如权利要求2所述的半导体器件封装(10),其特征在于:将长条(30)设置为与管芯附着焊盘(12)的相对侧面相邻。
4.如任一前述权利要求所述的半导体器件封装(10),其特征在于:将与长条(30)电连接的半导体管芯(20)上的接合焊盘(44)用于供电信号和/或要求低欧姆连接的信号,例如基准电压信号或地信号。
5.如任一前述权利要求所述的半导体器件封装(10),其特征在于:长条(30)包括与相应行中的两个接触焊盘相连接的侧向部分(36)。
6.如任一前述权利要求所述的半导体器件封装(10),其特征在于:长条(30)的底部表面(34)暴露。
7.如任一前述权利要求所述的半导体器件封装(10),其特征在于:电连接(22、24)包括接合在接合焊盘(44)和接触焊盘(261一26n)之间或者接合焊盘(44)和长条(30)之间的导线。
8.一种引线框,用于制造如任一前述权利要求所述的半导体器件封装(10)。
9.一种电子装置,包括诸如印刷电路板之类的电子载体,在所述电子载体上连接如任一前述权利要求所述的半导体器件封装(10)。
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PCT/IB2006/050492 WO2006090304A1 (en) | 2005-02-23 | 2006-02-15 | An integrated circuit package device with improved bond pad connections, a leadframe and an electronic device |
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101540308B (zh) * | 2008-03-18 | 2010-12-08 | 联发科技股份有限公司 | 半导体芯片封装 |
CN102779761A (zh) * | 2011-05-10 | 2012-11-14 | Nxp股份有限公司 | 用于封装半导体管芯的引线框架和方法 |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW200836315A (en) * | 2007-02-16 | 2008-09-01 | Richtek Techohnology Corp | Electronic package structure and method thereof |
EP2140489A1 (en) * | 2007-04-17 | 2010-01-06 | Nxp B.V. | Method for manufacturing an element having electrically conductive members for application in a microelectronic package |
US7763958B1 (en) * | 2007-05-25 | 2010-07-27 | National Semiconductor Corporation | Leadframe panel for power packages |
US7714418B2 (en) | 2007-07-23 | 2010-05-11 | National Semiconductor Corporation | Leadframe panel |
US7677109B2 (en) * | 2008-02-27 | 2010-03-16 | Honeywell International Inc. | Pressure sense die pad layout and method for direct wire bonding to programmable compensation integrated circuit die |
US8138027B2 (en) * | 2008-03-07 | 2012-03-20 | Stats Chippac, Ltd. | Optical semiconductor device having pre-molded leadframe with window and method therefor |
US8455993B2 (en) | 2010-05-27 | 2013-06-04 | Stats Chippac Ltd. | Integrated circuit packaging system with multiple row leads and method of manufacture thereof |
US10068817B2 (en) * | 2016-03-18 | 2018-09-04 | Macom Technology Solutions Holdings, Inc. | Semiconductor package |
US11342260B2 (en) * | 2019-10-15 | 2022-05-24 | Win Semiconductors Corp. | Power flat no-lead package |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5457340A (en) * | 1992-12-07 | 1995-10-10 | Integrated Device Technology, Inc. | Leadframe with power and ground planes |
US6100598A (en) * | 1997-03-06 | 2000-08-08 | Nippon Steel Semiconductor Corporation | Sealed semiconductor device with positional deviation between upper and lower molds |
US6229200B1 (en) | 1998-06-10 | 2001-05-08 | Asat Limited | Saw-singulated leadless plastic chip carrier |
KR100526844B1 (ko) * | 1999-10-15 | 2005-11-08 | 앰코 테크놀로지 코리아 주식회사 | 반도체패키지 및 그 제조방법 |
KR100359304B1 (ko) * | 2000-08-25 | 2002-10-31 | 삼성전자 주식회사 | 주변 링 패드를 갖는 리드 프레임 및 이를 포함하는반도체 칩 패키지 |
KR100369393B1 (ko) * | 2001-03-27 | 2003-02-05 | 앰코 테크놀로지 코리아 주식회사 | 리드프레임 및 이를 이용한 반도체패키지와 그 제조 방법 |
JP2003204027A (ja) * | 2002-01-09 | 2003-07-18 | Matsushita Electric Ind Co Ltd | リードフレーム及びその製造方法、樹脂封止型半導体装置及びその製造方法 |
US20040080025A1 (en) * | 2002-09-17 | 2004-04-29 | Shinko Electric Industries Co., Ltd. | Lead frame, method of manufacturing the same, and semiconductor device manufactured with the same |
US6882035B2 (en) | 2003-07-09 | 2005-04-19 | Agilent Technologies, Inc. | Die package |
-
2006
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CN101540308B (zh) * | 2008-03-18 | 2010-12-08 | 联发科技股份有限公司 | 半导体芯片封装 |
CN102779761A (zh) * | 2011-05-10 | 2012-11-14 | Nxp股份有限公司 | 用于封装半导体管芯的引线框架和方法 |
CN102779761B (zh) * | 2011-05-10 | 2015-04-01 | Nxp股份有限公司 | 用于封装半导体管芯的引线框架和方法 |
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JP2008532277A (ja) | 2008-08-14 |
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US20080265384A1 (en) | 2008-10-30 |
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