CN101089997A

CN101089997A - Storage circuit

Info

Publication number: CN101089997A
Application number: CN 200610021161
Authority: CN
Inventors: 景曙光
Original assignee: Individual
Current assignee: Individual
Priority date: 2006-06-12
Filing date: 2006-06-12
Publication date: 2007-12-19

Abstract

This invention discloses a storage circuit, in which, the data end of a storage is connected with the data end of a microprocessor via a resistor and connected with the supply end via a pull-up resistor and connected with a write protection end of the storage via an interference pulse detection circuit and a high-low level switch circuit, when there is not interference pulse, the high-low level switch circuit outputs a low level and the storage is at a state of allowing writing, and when an interference pulse appears, the circuit outputs a high level, and the storage is at a state of forbidding writing so as to prevent interference pulses from writing data in the storage so as to protect data in the storage.

Description

Memory circuitry

Technical field

The present invention relates to a kind of memory circuitry, specifically, relate to a kind of data protection circuit that is used for electric erasable and alterable read-only memory.

Background technology

At present, adopt electric erasable and alterable read-only memory storage data in many electric equipment products.The electricity erasable and alterable read-only memory also claims EEPROM, often abbreviates storer as.Wherein, 24CXX series or PCF859X series are the most common.Such storer is provided with a write-protect port WP, and high level is effective, promptly stops all write operations during high level.But in actual applications; many circuit are not provided with the terminal that memory write protection port is controlled on microprocessor; but the write-protect port of storer is fixed as low level, promptly be in the permission write state, to make things convenient for the read-write of microprocessor to storer always.Simplified circuit though handle like this, to have made things convenient for data write, when electrical work, machine intimate or outside disturbing pulse also just may enter and rewrite legacy data in the storer from data line, cause the machine can't operate as normal.For this reason, partial circuit seals in resistance in data line, and is connected electric capacity or voltage stabilizing diode between data line and ground, and to cut down the amplitude of disturbing pulse, processing still can not stop the rewriting of disturbing pulse to data in the storer effectively like this.

Summary of the invention

Technical matters to be solved by this invention provides a kind of memory circuitry, is not provided with at microprocessor under the situation of write-protect control end, can stop the rewriting of disturbing pulse to data in the storer effectively.

For realizing purpose of the present invention; the invention provides a kind of memory circuitry; data terminal by microprocessor links to each other with the data terminal of storer through resistance; form the bi-directional transfer of data line; data line links to each other with power end through pull-up resistor; between the data terminal of storer and its write-protect end, insert interference pulse detection circuit and high-low level commutation circuit; the input end of interference pulse detection circuit links to each other with the data terminal of storer; its output terminal links to each other with the input end of high-low level commutation circuit, and high-low level commutation circuit output terminal links to each other with the write-protect end of storer.Interference pulse detection circuit to the memory data end voltage detect, relatively, and smothing filtering becomes DC voltage to send into the high-low level commutation circuit.The high-low level commutation circuit is according to the level state of the height adjustment of input direct voltage output, and is sent to the write-protect end of storer, storer is in allows to write or forbid write state.

The invention has the beneficial effects as follows, when on the memory data end during noiseless pulse, high-low level commutation circuit output low level, storer is in the permission write state, does not influence microprocessor to data write operation in the storer; When having on the memory data end than the strong jamming pulse; under the DC voltage effect of interference pulse detection circuit output; high-low level commutation circuit output high level; storer is in forbids write state; stop the write operation of data; thereby prevent the data in the disturbing pulse rewriting storer, reach the purpose that data in the storer are protected.

Below in conjunction with accompanying drawing the specific embodiment of the present invention is described further.

Description of drawings

Fig. 1 is the data transmission circuit figure of storer in the prior art.

Fig. 2 is the data transmission circuit block diagram of storer among the present invention.

Fig. 3 is the physical circuit figure of first embodiment of interference pulse detection circuit and high-low level commutation circuit among the present invention.

Fig. 4 is the physical circuit figure of second embodiment of interference pulse detection circuit and high-low level commutation circuit among the present invention.

Embodiment

Fig. 1 is the data transmission circuit figure of storer in the prior art.The data terminal 2 of microprocessor 1 links to each other with the data terminal 4 of storer 3 through resistance 10; Write-protect end 5 ground connection of storer 3; Resistance 10 is formed low-pass filter with electric capacity 11, absorbs disturbing pulse, to cut down the disturbing pulse amplitude.Because storer is in the permission write state always, amplitude still might be rewritten data in the storer by the disturbing pulse after subduing.

In Fig. 2, interference pulse detection circuit 6 and high-low level commutation circuit 7 have been inserted between the data terminal 4 of storer 3 and its write-protect end 5.Wherein, the voltage of 6 pairs of data terminals 4 of interference pulse detection circuit detects and compares, and exports control voltage according to the result; High-low level commutation circuit 7 is adjusted the level state of output under the effect of control voltage; The write-protect end 5 of storer 3 is according to the automatic change state of output level height of high-low level commutation circuit 7.

Fig. 3 is the physical circuit figure of first embodiment of interference pulse detection circuit 6 and high-low level commutation circuit 7.Voltage stabilizing diode DW1 and capacitor C 1 are formed interference pulse detection circuit 6 among the figure; Resistance R 1 to resistance R 6 has been formed high-low level commutation circuit 7 with triode Q1, Q2.The type of attachment of this high-low level commutation circuit 7 is the emitter-coupled bistable circuit, claims Schmidt trigger again, and triode Q2 collector links to each other with the write-protect end 5 of storer 3 in this trigger.

During noiseless pulse, voltage stabilizing diode DW1 ends, and triode Q1 ends, the Q1 current collection is high level very, is added to triode Q2 base stage, the Q2 saturation conduction after resistance R 3 and R4 dividing potential drop, the Q2 current collection is low level very, and promptly the write-protect end 5 of storer 3 is a low level, and storer is in the permission write state; When disturbing pulse arrives; voltage stabilizing diode DW1 conducting; triode Q1 conducting; triode Q1 collector voltage descends; triode Q2 base voltage descends, and triode Q2 withdraws from state of saturation, and the emitter current of Q2 reduces; the both end voltage of resistance R 6 descends; be that triode Q1 emitter voltage descends, triode Q1 base current is bigger, under the effect of this positive feedback process; triode Q1 enters state of saturation rapidly; triode Q2 enters cut-off state rapidly, triode Q2 collector output high level, and promptly the write-protect end 5 of storer 3 is a high level; storer is in forbids write state, stops all write operations.

Fig. 4 is the physical circuit figure of another embodiment of interference pulse detection circuit 6 and high-low level commutation circuit 7.The in-phase input end of voltage comparator 8 connects memory data end 4 through diode D10, resistance R 10 in this example; Its inverting input connects the negative pole of voltage stabilizing diode DW10, voltage stabilizing diode DW10 plus earth.Voltage stabilizing diode DW10 is under the effect of the current limliting step-down of resistance R 11, for the inverting input of voltage comparator 8 provides a reference voltage.The output terminal of voltage comparator 8 links to each other with the write-protect end 5 of storer 3.

During noiseless pulse, capacitor C 10 both end voltage are lower than the voltage stabilizing value of voltage stabilizing diode DW10, and promptly voltage comparator 8 inverting input voltages are higher than its in-phase input end voltage, voltage comparator 8 output low levels, the write-protect end 5 that is storer 3 is low level, and storer 3 is in the permission write state; When disturbing pulse arrives; disturbing pulse raises the both end voltage of capacitor C 10 through resistance R 10 current limlitings and diode D10, capacitor C 10 rectifying and wave-filterings; and the very fast voltage stabilizing value that surpasses voltage stabilizing diode DW10; be that voltage comparator 8 in-phase input end voltages are higher than its inverting input voltage; voltage comparator 8 input high levels; the write-protect end 5 that is storer 3 is high level, and storer is in forbids write state, stops all write operations.

Claims

1. memory circuitry; link to each other with the data terminal (4) of storer (3) through resistance (10) by the data terminal (2) of microprocessor (1) and to form the data line of transmitted in both directions; data line links to each other with power end (8) through pull-up resistor (9); it is characterized in that; between the data terminal (4) of described storer (3) and its write-protect end (5), insert interference pulse detection circuit (6) and high-low level commutation circuit (7); the input end of described interference pulse detection circuit (6) links to each other with the data terminal (4) of storer (3); its output terminal links to each other with the input end of high-low level commutation circuit (7), and described high-low level commutation circuit (7) output terminal links to each other with the write-protect end (5) of storer (3).

2. memory circuitry according to claim 1, wherein said high-low level commutation circuit (7) is a bistable circuit.

3. memory circuitry according to claim 1, wherein said high-low level commutation circuit (7) is a voltage comparator.

4. memory circuitry according to claim 2, wherein said bistable circuit are emitter-coupled bistable circuit, i.e. Schmidt trigger.