CN203069654U - Power failure detection circuit - Google Patents
Power failure detection circuit Download PDFInfo
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- CN203069654U CN203069654U CN 201220741436 CN201220741436U CN203069654U CN 203069654 U CN203069654 U CN 203069654U CN 201220741436 CN201220741436 CN 201220741436 CN 201220741436 U CN201220741436 U CN 201220741436U CN 203069654 U CN203069654 U CN 203069654U
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Abstract
The utility model provides a power failure detection circuit, which comprises a voltage division circuit, a voltage detection circuit and a surge current suppression circuit, wherein the voltage division circuit is connected to first DC voltage and carries out voltage division on the first DC voltage, the voltage detection circuit is connected with the voltage division circuit, the surge current suppression circuit is connected with the voltage division circuit and the voltage detection circuit, an output end of the voltage detection circuit is connected to a processor, and the voltage detection circuit outputs a power failure signal to the processor when the first DC voltage is smaller than a set value. The power failure detection circuit provided by the utility model improves the reliability of products, and has the advantages of simple and reliable circuit, small occupied area on a PCB, low cost and the like.
Description
Technical field
The utility model relates to electronic circuit, especially, relates to a kind of power-fail detection circuit for the preservation of power down data.
Background technology
The development of modern communication and industrial technology, more and more higher to the reliability of equipment work.When meeting accident when machine, need in time to record the state etc. of communication data, warning message and the equipment work of current device and other equipment.This just requires unexpected when machine, and the processor of equipment in time fast detecting is kept desired data to power-off signal in the extremely short time, and need make a distinction the power-off signal that causes because of interference with real power-off signal.
The utility model content
In order to address the above problem, the purpose of this utility model is to provide a kind of power-fail detection circuit for the preservation of power down data, to improve the equipment reliability during operation.
The technical scheme that its technical matters that solves the utility model adopts is:
A kind of power-fail detection circuit, comprise the inhibition in-rush current limiting circuit that inserts one first DC voltage and first DC voltage is carried out the bleeder circuit of dividing potential drop, the voltage detecting circuit that is connected with bleeder circuit, is connected respectively with bleeder circuit and voltage detecting circuit, the output terminal of voltage detecting circuit is connected to a processor, and voltage detecting circuit is exported a power-off signal to processor in first DC voltage during less than setting value.
Advantage of the present utility model is:
Promoted reliability of products, have circuit simple and reliable, take advantages such as the PCB area is little and with low cost.
Description of drawings
Fig. 1 is the circuit module synoptic diagram of the utility model power-fail detection circuit;
Fig. 2 is the physical circuit figure of Fig. 1.
Embodiment
The utility model is described in further detail below in conjunction with drawings and Examples:
See also Fig. 1 and Fig. 2, a kind of power-fail detection circuit 100, comprise and insert one first DC voltage and first DC voltage is carried out the bleeder circuit 10 of dividing potential drop, the voltage detecting circuit 20 that is connected with bleeder circuit 10, the inhibition in-rush current limiting circuit 30 that is connected respectively with bleeder circuit 10 and voltage detecting circuit 20, the output terminal of voltage detecting circuit 20 is connected to a processor 40, and exports a power-off signal to processor in first DC voltage during less than setting value.
Described bleeder circuit 10 comprises first resistance R 62 and first resistance R 62 and the second resistance R 63 back ground connection of second resistance R, 63, the first DC voltage through being connected in series.In the present embodiment, first resistance be second resistance 5-10 doubly about.One preferred embodiment in, described first resistance is 7 times of second resistance.
Described inhibition in-rush current limiting circuit 30 comprises TVS pipe D10, the plus earth of described TVS pipe D10, and the negative electrode of described TVS pipe D10 is connected between first resistance R 62 and second resistance R 63, forms first node A.In the present embodiment, the voltage breakdown of described TVS pipe D10 is 5V, to realize the inhibition to the first DC voltage surge, protection voltage detecting circuit 20.
Described voltage detecting circuit 20 comprises voltage detecting IC, the input end Vcc of described voltage detecting IC is connected to first node A, the first output terminal OUT of described voltage detecting IC is connected to processor 40, one second direct current pressure side is connected between the first output terminal OUT and processor 40 of described voltage detecting IC by the 3rd resistance R 65, form Section Point B, the second output terminal Vss ground connection of described voltage detecting IC.
Concrete, in the present embodiment, first resistance is 210K Ω, described second resistance is 30K Ω, and described voltage detecting IC is STM 1061, and its threshold voltage is made as 2.2V, the voltage breakdown of described TVS pipe is 5V, the voltage of the described second direct current pressure side is 3V, and the 3rd resistance is 10K Ω, and first DC voltage is input as about 24V when operate as normal.
Under normal circumstances, the voltage of first node A is 24*[30K Ω/(30K Ω+210K Ω)] V, that is, be 3V, because STM1061 inner valve threshold voltage is 2.2V, less than input voltage 3V, thereby its first output terminal OUT can not export power-off signal to processor 40.When first DC voltage is reduced to less than 17.6V, the voltage of first node A will be lower than STM1061 inner valve threshold voltage less than 2.2V, thereby the output terminal OUT of STM1061 will export a low level power-off signal to processor 40.Processor 40 is carried out data power down hold function immediately after detecting this low level power-off signal.In other embodiments, processor 40 also can be after detecting this low level power-off signal, and do not understand and carry out data power down hold function, but detect the whether also existence of this low level power-off signal again after the schedule time (as 10ms) at interval, if also exist, then carry out data power down hold function, if power-off signal has not existed, then be judged as external disturbance, thereby do not carry out data power down hold function.
Because the utility model adopts voltage-level detector STM1061 and TVS pipe, reduced the complicacy of circuit, can avoid simultaneously first DC voltage input surge to the infringement of voltage-level detector STM1061 and processor 40 etc., promoted reliability of products, compared with similar products, have circuit simple and reliable, take advantages such as the PCB area is little and with low cost.
The above only is preferred embodiment of the present utility model, and is in order to limit the utility model, not all within spirit of the present utility model and principle, any modification of doing, is equal to replacement, improvement etc., all should be included within the protection domain of the present utility model.
Claims (8)
1. power-fail detection circuit, it is characterized in that: comprise the inhibition in-rush current limiting circuit that inserts one first DC voltage and first DC voltage is carried out the bleeder circuit of dividing potential drop, the voltage detecting circuit that is connected with bleeder circuit, is connected respectively with bleeder circuit and voltage detecting circuit, the output terminal of voltage detecting circuit is connected to a processor, and voltage detecting circuit is exported a power-off signal to processor in first DC voltage during less than setting value.
2. power-fail detection circuit according to claim 1, it is characterized in that: described bleeder circuit comprises first resistance and second resistance, first DC voltage through first resistance that is connected in series and second resistance after ground connection.
3. power-fail detection circuit according to claim 2 is characterized in that: described inhibition in-rush current limiting circuit comprises the TVS pipe, the plus earth of described TVS pipe, and the negative electrode of described TVS pipe is connected between first resistance and second resistance, forms first node.
4. power-fail detection circuit according to claim 3, it is characterized in that: described voltage detecting circuit comprises voltage detecting IC, the input end of described voltage detecting IC is connected to first node, first output terminal of described voltage detecting IC is connected to processor, one second direct current pressure side is connected between first output terminal and processor of described voltage detecting IC by the 3rd resistance, form Section Point, second output head grounding of described voltage detecting IC.
5. power-fail detection circuit according to claim 4, it is characterized in that: described first resistance is 7 times of second resistance.
6. according to claim 4 or 5 described power-fail detection circuits, it is characterized in that: described first resistance is 210K Ω, and described second resistance is 30K Ω, and described voltage detecting IC is STM 1061, and the threshold voltage of STM1061 is made as 2.2V.
7. power-fail detection circuit according to claim 6, it is characterized in that: the voltage breakdown of described TVS pipe is 5V.
8. power-fail detection circuit according to claim 6, it is characterized in that: described the 3rd resistance is 10K Ω, the voltage of the second direct current pressure side is 3V.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220741436 CN203069654U (en) | 2012-12-30 | 2012-12-30 | Power failure detection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220741436 CN203069654U (en) | 2012-12-30 | 2012-12-30 | Power failure detection circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203069654U true CN203069654U (en) | 2013-07-17 |
Family
ID=48768426
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201220741436 Expired - Fee Related CN203069654U (en) | 2012-12-30 | 2012-12-30 | Power failure detection circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203069654U (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104062548A (en) * | 2014-06-13 | 2014-09-24 | 苏州华徕光电仪器有限公司 | Commercial power power-down alarm circuit |
| CN104749423A (en) * | 2013-12-31 | 2015-07-01 | 东莞钜威新能源有限公司 | Power failure detection circuit for direct current power supply |
| CN108336786A (en) * | 2018-02-11 | 2018-07-27 | 深圳市显控科技股份有限公司 | A kind of anti-load power source oscillating circuit for farad capacitor backup power supply |
-
2012
- 2012-12-30 CN CN 201220741436 patent/CN203069654U/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104749423A (en) * | 2013-12-31 | 2015-07-01 | 东莞钜威新能源有限公司 | Power failure detection circuit for direct current power supply |
| CN104062548A (en) * | 2014-06-13 | 2014-09-24 | 苏州华徕光电仪器有限公司 | Commercial power power-down alarm circuit |
| CN108336786A (en) * | 2018-02-11 | 2018-07-27 | 深圳市显控科技股份有限公司 | A kind of anti-load power source oscillating circuit for farad capacitor backup power supply |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20130717 Termination date: 20161230 |